阅读说明：本技术 晶圆键合结构、晶圆键合方法及芯片键合结构 (Wafer bonding structure, wafer bonding method and chip bonding structure ) 是由 叶国梁 易洪昇 于 2020-07-31 设计创作，主要内容包括：本发明提供了一种晶圆键合结构、晶圆键合方法及芯片键合结构,第一晶圆包括非金属层区域和分布有所述第一金属层的金属层区域；位于非金属层区域的第一调整层低于位于金属层区域的所述第一调整层；第二调整层覆盖第一调整层；化学机械研磨所述第二调整层和所述第一调整层,研磨液对第一调整层和第二调整层的研磨速率不同,使在非金属层区域剩余的第二调整层高于或低于在金属层区域剩余的第一调整层,在非金属层区域形成第一凸起部或第一凹陷部,以匹配与其键合的有凹陷或凸起的晶圆或芯片。减少键合间隙,提高工艺质量以及产品良率。消除或减少由于化学机械研磨工艺带来的局部位置凹陷,修正上下晶圆的键合空隙,提高键合强度以及质量。(The invention provides a wafer bonding structure, a wafer bonding method and a chip bonding structure, wherein a first wafer comprises a non-metal layer area and a metal layer area distributed with a first metal layer; the first adjusting layer positioned in the non-metal layer area is lower than the first adjusting layer positioned in the metal layer area; the second adjusting layer covers the first adjusting layer; and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of the grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area so as to match with the wafer or chip which is bonded with the wafer or chip and has a concave or convex part. Reduce bonding clearance, improve technology quality and product yield. The local position depression caused by the chemical mechanical polishing process is eliminated or reduced, the bonding gap between the upper wafer and the lower wafer is corrected, and the bonding strength and the bonding quality are improved.)

1. A wafer bonding method, comprising:

providing a first wafer, wherein the first wafer comprises a first substrate and a first metal layer positioned above the first substrate; the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

forming a first adjusting layer covering the first metal layer and the first substrate, wherein the first adjusting layer in the non-metal layer area is lower than the first adjusting layer in the metal layer area;

forming a second adjustment layer overlying the first adjustment layer;

and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area.

2. The wafer bonding method of claim 1, wherein the first adjustment layer is formed using a high density plasma chemical vapor deposition process; and forming the second adjusting layer by adopting an ethyl orthosilicate deposition process.

3. The wafer bonding method of claim 2, wherein a polishing rate of the second adjustment layer by the polishing slurry is less than a polishing rate of the first adjustment layer.

4. The wafer bonding method of claim 2, wherein the process parameters for forming the first adjustment layer using a high density plasma chemical vapor deposition process comprise: the pressure of the cavity is set to be 5 mTorr-10 mTorr, the top source radio frequency power is set to be 1200W-1300W, the side source radio frequency power is set to be 3000W-3100W, and the bias radio frequency is 3200W-3300W.

5. The wafer bonding method of claim 4, wherein the process gas parameters for forming the first adjustment layer using a high density plasma chemical vapor deposition process comprise: the flow rate of argon is 105sccm to 115sccm, the flow rate of oxygen is 120sccm to 130sccm, and the flow rate of silane is 115sccm to 125 sccm.

6. The wafer bonding method of claim 2, wherein forming the second adjustment layer using an ethyl orthosilicate deposition process comprises:

gasifying the tetraethoxysilane liquid to generate tetraethoxysilane gas;

introducing oxygen and the tetraethoxysilane gas into a reaction chamber;

and dissociating the oxygen and the tetraethoxysilane gas to react to generate the second adjusting layer.

7. The wafer bonding method of claim 6,

the temperature for gasifying the tetraethoxysilane liquid is 80-120 ℃;

the flow rate of the oxygen introduced into the reaction chamber is 2000 sccm-4500 sccm, and the flow rate of the tetraethoxysilane gas is 500 sccm-1500 sccm;

and dissociating the oxygen and the tetraethoxysilane gas by radio frequency, wherein the power of the radio frequency is 300-800W.

8. The wafer bonding method of any one of claims 2 to 7, wherein the first adjustment layer and the second adjustment layer are both made of silicon oxide layers.

9. The wafer bonding method according to any one of claims 1 to 7, wherein the non-metal layer region comprises a dicing street region and/or a region in which no metal layer is distributed in a single chip structure in the first wafer.

10. The wafer bonding method of any of claims 1 to 7, wherein after the chemical mechanical polishing of the second adjustment layer and the first adjustment layer, further comprising:

forming a first interconnection layer, forming a first dielectric layer above the rest of the second adjusting layer and the rest of the first adjusting layer, etching an opening in the first dielectric layer, and filling the opening with the first interconnection layer; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

providing a second wafer, wherein the second wafer is provided with a third convex part or a third concave part; the third convex part is matched with the second concave part, and the third concave part is matched with the second convex part;

and bonding the first wafer and the second wafer.

11. The wafer bonding method according to claim 1, wherein a polishing rate of the polishing liquid for the first adjustment layer is higher than a polishing rate for the second adjustment layer, and the first protrusion is formed in the non-metal layer region.

12. The wafer bonding method according to claim 1, wherein a polishing rate of the polishing liquid for the first adjustment layer is lower than a polishing rate for the second adjustment layer, and the first recess is formed in the non-metal layer region.

13. A wafer bonding structure, comprising:

a first wafer comprising a first substrate and a first metal layer over the first substrate; the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

a first adjustment layer covering the first metal layer and the first substrate, the first adjustment layer located in the non-metal layer region being lower than the first adjustment layer located in the metal layer region;

the second adjusting layer is located in the non-metal layer area and covers the first adjusting layer, the second adjusting layer is higher than or lower than the first adjusting layer located in the metal layer area, and a first protruding portion or a first recessed portion is formed in the non-metal layer area.

14. The wafer bonding structure of claim 13, further comprising:

the first dielectric layer covers the first adjusting layer and the second adjusting layer; the first dielectric layer is distributed with openings; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

a first interconnect layer filled in the opening;

a second wafer having a third protrusion or a third depression;

the first wafer is bonded with the second wafer, and the third protruding portion is matched with the second recessed portion, or the third recessed portion is matched with the second protruding portion.

15. A chip bonding structure, comprising:

a first chip comprising a first substrate and a first metal layer over the first substrate; the first chip comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

a first adjustment layer covering the first metal layer and the first substrate, the first adjustment layer located in the non-metal layer region being lower than the first adjustment layer located in the metal layer region;

the second adjusting layer is located in the non-metal layer area and covers the first adjusting layer, the second adjusting layer is higher than or lower than the first adjusting layer located in the metal layer area, and a first protruding portion or a first recessed portion is formed in the non-metal layer area.

16. The die bond structure of claim 15, further comprising:

the first dielectric layer covers the first adjusting layer and the second adjusting layer; the first dielectric layer is distributed with openings; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

a first interconnect layer filled in the opening;

a second chip having a third protrusion or a third recess;

the first chip is bonded to the second chip, and the third protruding portion is matched with the second recessed portion, or the third recessed portion is matched with the second protruding portion.

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a wafer bonding structure, a wafer bonding method and a chip bonding structure.

Background

In the 3D-IC wafer bonding process, a mixed bonding of a metal layer to a metal layer and a dielectric layer to a dielectric layer is often used. The bonding surface has intermolecular bonding of the dielectric layer and electrical connection of the metal layer to the metal layer, so the bonding surface has high requirements. On two wafers, a dielectric layer is generally used for electrical isolation and adjustment of bonding morphology, and the dielectric layer can obtain an ideal morphology at a wafer level by using Chemical Mechanical Polishing (CMP). In addition, at the micron and submicron microscopic scale, the surface unevenness of the metal layer filled in the single opening can be controlled within the micron level by utilizing the selection ratio of the grinding fluid to the bonding surface dielectric layer and the metal layer, and the unevenness of the surface of the metal layer in the opening is acceptable for bonding.

After the chemical mechanical polishing process is adopted on the current bonding surface, although the wafer level and the bonding morphology of the surface of the metal layer in a single opening can be controlled, on the microscopic scale of 0.1-10 mm, the bonding morphology is found to be uneven, particularly, a dielectric layer at the position where the metal layer is not filled on a cutting channel around a chip is limited by the selectivity characteristic of CMP polishing solution, the polishing rate of the dielectric layer at the position is relatively high, the obtained microscopic morphology can be sunken by about several nanometers, and the sunken parts of an upper wafer and a lower wafer can form gaps during bonding, so that the bonding strength and the bonding quality are finally influenced. In some application occasions, the dielectric layer is locally raised and uneven, and the bonding strength and quality are also affected.

Disclosure of Invention

The invention aims to provide a wafer bonding structure, a wafer bonding method and a chip bonding structure, which improve the micro-morphology, form a wafer structure or a chip structure with bulges or depressions, match the wafer or the chip with the bulges or the depressions bonded with the wafer or the chip, and improve the bonding strength and the bonding quality.

The invention provides a wafer bonding method, which comprises the following steps:

providing a first wafer, wherein the first wafer comprises a first substrate and a first metal layer positioned above the first substrate; the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

forming a first adjusting layer covering the first metal layer and the first substrate, wherein the first adjusting layer in the non-metal layer area is lower than the first adjusting layer in the metal layer area;

forming a second adjustment layer overlying the first adjustment layer;

and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area.

Further, a high-density plasma chemical vapor deposition process is adopted to form the first adjusting layer; and forming the second adjusting layer by adopting an ethyl orthosilicate deposition process.

Further, the polishing rate of the second adjustment layer by the polishing liquid is smaller than that of the first adjustment layer.

Further, the process parameters for forming the first adjustment layer by using the high-density plasma chemical vapor deposition process include: the pressure of the cavity is set to be 5 mTorr-10 mTorr, the top source radio frequency power is set to be 1200W-1300W, the side source radio frequency power is set to be 3000W-3100W, and the bias radio frequency is 3200W-3300W.

Further, the process gas parameters for forming the first adjustment layer by using the high-density plasma chemical vapor deposition process include: the flow rate of argon is 105sccm to 115sccm, the flow rate of oxygen is 120sccm to 130sccm, and the flow rate of silane is 115sccm to 125 sccm.

Further, the forming the second adjustment layer by using an ethyl orthosilicate deposition process includes:

gasifying the tetraethoxysilane liquid to generate tetraethoxysilane gas;

introducing oxygen and the tetraethoxysilane gas into a reaction chamber;

and dissociating the oxygen and the tetraethoxysilane gas to react to generate the second adjusting layer.

Further, the temperature for gasifying the tetraethoxysilane liquid is 80-120 ℃;

the flow rate of the oxygen introduced into the reaction chamber is 2000 sccm-4500 sccm, and the flow rate of the tetraethoxysilane gas is 500 sccm-1500 sccm;

and dissociating the oxygen and the tetraethoxysilane gas by radio frequency, wherein the power of the radio frequency is 300-800W.

Furthermore, the first adjusting layer and the second adjusting layer are both made of silicon oxide layers.

Further, the non-metal layer region includes a dicing street region and/or a region in which no metal layer is distributed in a single chip structure in the first wafer.

Further, after the chemical mechanical polishing of the second adjustment layer and the first adjustment layer, the method further includes:

forming a first interconnection layer, forming a first dielectric layer above the rest of the second adjusting layer and the rest of the first adjusting layer, etching an opening in the first dielectric layer, and filling the opening with the first interconnection layer; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

providing a second wafer, wherein the second wafer is provided with a third convex part or a third concave part; the third convex part is matched with the second concave part, and the third concave part is matched with the second convex part;

and bonding the first wafer and the second wafer.

Further, the polishing rate of the polishing liquid for the first adjustment layer is greater than the polishing rate for the second adjustment layer, and the first protrusion is formed in the non-metal layer region.

Further, the polishing rate of the polishing liquid for the first adjustment layer is smaller than that for the second adjustment layer, and the first recess portion is formed in the non-metal layer region.

The present invention also provides a wafer bonding structure, including:

a first wafer comprising a first substrate and a first metal layer over the first substrate; the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

a first adjustment layer covering the first metal layer and the first substrate, the first adjustment layer located in the non-metal layer region being lower than the first adjustment layer located in the metal layer region;

the second adjusting layer is located in the non-metal layer area and covers the first adjusting layer, the second adjusting layer is higher than or lower than the first adjusting layer located in the metal layer area, and a first protruding portion or a first recessed portion is formed in the non-metal layer area.

Further, the method also comprises the following steps:

the first dielectric layer covers the first adjusting layer and the second adjusting layer; the first dielectric layer is distributed with openings; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

a first interconnect layer filled in the opening;

a second wafer having a third protrusion or a third depression;

the first wafer is bonded with the second wafer, and the third protruding portion is matched with the second recessed portion, or the third recessed portion is matched with the second protruding portion.

The present invention also provides a chip bonding structure, comprising:

a first chip comprising a first substrate and a first metal layer over the first substrate; the first chip comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

a first adjustment layer covering the first metal layer and the first substrate, the first adjustment layer located in the non-metal layer region being lower than the first adjustment layer located in the metal layer region;

the second adjusting layer is located in the non-metal layer area and covers the first adjusting layer, the second adjusting layer is higher than or lower than the first adjusting layer located in the metal layer area, and a first protruding portion or a first recessed portion is formed in the non-metal layer area.

Further, the method also comprises the following steps:

the first dielectric layer covers the first adjusting layer and the second adjusting layer; the first dielectric layer is distributed with openings; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

a first interconnect layer filled in the opening;

a second chip having a third protrusion or a third recess;

the first chip is bonded to the second chip, and the third protruding portion is matched with the second recessed portion, or the third recessed portion is matched with the second protruding portion.

Compared with the prior art, the invention has the following beneficial effects:

in the wafer bonding structure, the wafer bonding method and the chip bonding structure provided by the invention, the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer; the first adjusting layer located in the non-metal layer area is lower than the first adjusting layer located in the metal layer area; the second adjusting layer covers the first adjusting layer; and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area so as to match with a wafer or a chip which is bonded with the wafer or the chip and has a concave or convex part. Reduce bonding clearance, improve technology quality and product yield. The local position depression caused by the chemical mechanical polishing process is eliminated or reduced, the bonding gap between the upper wafer and the lower wafer is corrected, and the bonding strength and the bonding quality are improved.

Drawings

Fig. 1 is a schematic view of a wafer bonding method according to an embodiment of the invention.

Fig. 2 to 7 are schematic diagrams illustrating steps of a wafer bonding method according to an embodiment of the invention.

Wherein the reference numbers are as follows:

10-a first wafer; 101-a first substrate; 102-a first insulating layer; 103-a first metal layer; 104 a-a first adjustment layer; 104 b-a second adjustment layer; 105-a first dielectric layer; 106 — a first interconnect layer;

20-a second wafer; 201-a second substrate; 202-a second insulating layer; 203-a second metal layer; 204-an isolation layer; 205-a second dielectric layer; 206-a second interconnect layer;

i-a metal layer region; II-non-metallic layer area; a. the₁-a first boss; a. the₂-a first recess; b is₁-a second boss; c₂-a third recess.

Detailed Description

Based on the above research, the embodiment of the invention provides a wafer bonding structure and a wafer bonding method. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.

An embodiment of the present invention provides a wafer bonding method, as shown in fig. 1, including:

providing a first wafer, wherein the first wafer comprises a first substrate and a first metal layer positioned above the first substrate; the first wafer comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

forming a first adjusting layer covering the first metal layer and the first substrate, wherein the first adjusting layer in the non-metal layer area is lower than the first adjusting layer in the metal layer area;

forming a second adjustment layer overlying the first adjustment layer;

and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area.

The steps of the wafer bonding method according to the embodiment of the invention will be described with reference to fig. 2 to 7.

As shown in fig. 2, a first wafer is provided, which includes a first substrate 101 and a first metal layer 103 located above the first substrate 101; the first wafer comprises a non-metal layer area II and a metal layer area I distributed with the first metal layer 103. The first wafer is provided with chip structures in an array mode, and the non-metal layer area II comprises a cutting channel area between the chip structures arranged in the array mode on the first wafer and/or an area where no metal layer is distributed in a single chip structure in the first wafer. Specifically, a first insulating layer 102 is further distributed on the first substrate 101, and the first metal layer 103 is located on the first insulating layer 102.

Forming a first adjustment layer 104a covering the first metal layer 103 and the first substrate 101, wherein the first adjustment layer 104a in the non-metal layer region II is lower than the first adjustment layer 104a in the metal layer region I.

As shown in fig. 3, a second adjustment layer 104b is formed to cover the first adjustment layer 104 a.

As shown in fig. 4a and 4b, the second adjustment layer 104b and the first adjustment layer 104a are chemically and mechanically polished, and the polishing rates of the first adjustment layer 104a and the second adjustment layer 104b by the polishing slurry are different, so that the second adjustment layer 104b remaining in the non-metal layer region II is higher or lower than the first adjustment layer 104a remaining in the metal layer region I, and a first protrusion a is formed in the non-metal layer region II₁Or the first recess A₂。

A first adjustment layer 104a and a second adjustment layerThe adjusting layer 104b can be made of different materials, and the same grinding liquid is used for different grinding rates of different materials, so that the first protruding part A is formed on the non-metal layer area II₁Or the first recess A₂. The polishing rate of the first adjustment layer 104a or the second adjustment layer 104b by the polishing liquid may also be changed by adding some impurities to the polishing liquid.

As shown in fig. 4a, the first protrusion portion a is formed on the non-metal layer region II₁The polishing rate of the first adjustment layer 104a by the polishing liquid is higher than that of the second adjustment layer 104 b.

As shown in fig. 4b, the first recess portion a is formed in the non-metal layer region II₂The polishing rate of the first adjustment layer 104a by the polishing liquid is smaller than that of the second adjustment layer 104 b. Illustratively, the polishing liquid is, for example, an alkaline solution, and may include: the silicon dioxide, the hydrogen peroxide and the organic additive are mixed in a ratio of 1: 10-1: 20, the first adjusting layer 104a can be any one of silicon nitride, tantalum nitride and titanium nitride, and the second adjusting layer 104b can be any one of silicon oxide, tantalum oxide, aluminum oxide, hafnium oxide and FSG. The first adjustment layer 104a and the second adjustment layer 104b may be formed by different deposition methods, and the polishing rates of the same polishing slurry may be different by different deposition methods, thereby forming different features. The first adjustment layer 104a and the second adjustment layer 104b with different polishing rates are formed by deposition, and finally polished to form a profile having protrusions or depressions.

Specifically, as shown in fig. 2, a first adjustment layer 104a may be formed by using an HDP-CVD (high density plasma-chemical vapor deposition) process, and the first adjustment layer 104a covers the first metal layer 103 and the first substrate 101. The HDP-CVD process performs deposition and etching processes synchronously in the same reaction chamber. Specifically, the deposition process is usually from SiH₄And O₂Is carried out by reaction of (a) and the etching process is usually carried out by Ar and O₂Sputtering is performed.

The method for forming the first adjustment layer 104a by the HDP-CVD process of the embodiment includes a preheating step and a deposition step, wherein the preheating step forms a high density plasma in the chamber and heats the first wafer by the high density plasma, so that the temperature of the first wafer is raised from the initial temperature of the chamber. The final temperature of the first wafer after the preheating step is greater than or equal to 400 ℃ and less than or equal to the temperature of the first wafer in the deposition step. The temperature of the first wafer in the deposition step is, for example, 640 to 720 ℃. The heating time of the preheating step may be 15 seconds to 90 seconds.

In a preferred embodiment, the process parameters of the deposition step include: the pressure of the cavity is set to be 5-10 mTorr; the top source RF power is set to 1200W-1300W, the side source RF power is set to 3000W-3100W, and the bias RF power is 3200W-3300W. The process gas comprises: the flow rate of argon flowing from the top of the cavity is 105 sccm-115 sccm, and the flow rate of oxygen is 120 sccm-130 sccm. The silicon source adopts silane, and the flow rate of the silane is 115 sccm-125 sccm. When the deposition is carried out by adopting the process parameters, the temperature of the cavity and the first wafer is 680-700 ℃ after the chamber and the first wafer are stabilized.

The HDP-CVD process achieves deposition at a lower temperature in a high-density plasma reaction chamber, and the deposited first adjustment layer 104a has advantages of high density, low impurity defects, and the like, while having excellent adhesion to the first metal layer 103 and the second insulating layer 102.

Next, as shown in fig. 3, a second adjustment layer 104b is formed by a tetraethyl orthosilicate (TEOS) deposition process, and the second adjustment layer 104b covers the first adjustment layer 104 a. The method for forming the second adjustment layer 104b by using a tetraethyl orthosilicate (TEOS) deposition process includes:

the TEOS (tetraethyl orthosilicate) liquid is vaporized at a temperature of, for example, 80 to 120 ℃ to generate a TEOS gas.

Oxygen (O)₂) And introducing the TEOS gas into the reaction chamber, wherein the flow of the oxygen introduced into the reaction chamber is 2000 sccm-4500 sccm, and the flow of the TEOS is 500 sccm-1500 sccm. The T isThe EOS gas enters the reaction chamber through an inert gas as a carrier, wherein the inert gas includes, but is not limited to, helium (He). The reaction temperature in the reaction chamber is 380-420 ℃.

The oxygen gas and the TEOS gas are dissociated and reacted to form the second adjustment layer 104 b. And dissociating the oxygen and the TEOS gas through radio frequency, wherein the radio frequency power is 300-800W. The second adjustment layer 104b prepared by the preparation method of this embodiment has better compactness and is resistant to grinding.

Next, as shown in fig. 3 and 4a, a Chemical Mechanical Polishing (CMP) process is performed to polish the second adjustment layer 104b, exposing at least the first adjustment layer 104a in the metal layer region I. The polishing rate of the second adjustment layer 104b formed by the ethyl orthosilicate deposition process is lower than the polishing rate of the first adjustment layer 104a formed by the high-density plasma chemical vapor deposition process. Forming a first bulge part A on the non-metal layer region II₁. Specifically, the first adjustment layer 104a and the second adjustment layer 104b are made of, for example, silicon oxide layers.

After the CMP process is used to polish the wafer to a target thickness, the non-metal layer region II (e.g., the region including the scribe line region and/or the region of the single chip structure in the first wafer where the metal layer is not distributed) has two silicon oxide layers, and since the polishing rate of the second adjustment layer 104b formed by the TEOS process is low, a microscopic bump, i.e., a first bump a, is formed at this position₁. The protruding amount can be accurately controlled by controlling the thickness of the silicon oxide layer and the thickness removed by grinding.

Forming a first adjusting layer 104a by adopting a High Density Plasma (HDP) deposition process above the first metal layer 103, forming a second adjusting layer 104b by adopting a tetraethyl orthosilicate (TEOS) deposition process, and using the first adjusting layer 104a and the second adjusting layer 104b as adjusting layers, wherein the two silicon oxide layers are obtained by controlling the growth thickness and the grinding thickness of the two silicon oxide layers and the non-metal layer area II (such as a cutting channel area and/or an area without a metal layer distributed in a single chip structure in the first wafer), and the second adjusting layer 104b formed by the TEOS process and the selection ratio characteristic of the CMP process grinding are utilizedThe grinding rate is slow, and a first bulge part A is formed on the non-metal layer area II₁。

As shown in fig. 5, a first interconnect layer 106 is formed, and a first dielectric layer 105 is formed over the remaining second adjustment layer 104b and the remaining first adjustment layer 104 a. An opening is etched in the first dielectric layer 105, the opening penetrating through the first dielectric layer 105 and a portion of the thickness of the first adjustment layer 104 a. Filling the opening with the first interconnect layer 106; the first interconnect layer 106 is electrically connected (not shown) to the first metal layer 103 for leading out electrical signals of the first wafer 10. The material of the first interconnect layer 106 is a metal, such as copper or tungsten. After the CMP process, the polishing amount is small, the shape of the entire upper surface is inherited, and the first dielectric layer 105 also forms a protrusion in the non-metal layer region II, that is, the second protrusion B₁. The second convex part B₁Is positioned at the first bulge part A₁Right above, and the second convex part B₁Located at the bonding surface.

As shown in fig. 6, providing a second wafer 20, the second wafer 20 comprising a second substrate 201 and a second metal layer 203 located above the second substrate 201; the second wafer comprises a non-metal layer region II and a metal layer region I distributed with the second metal layer 203. The array of the second wafer 20 is provided with chip structures, and the non-metal layer area includes a dicing street area between the chip structures arranged in the array on the second wafer 20 and/or an area where no metal layer is distributed in a single chip structure in the second wafer 20. Specifically, a second insulating layer 202 is further distributed on the second substrate 201, and the second metal layer 203 is located on the second insulating layer 202. An isolation layer 204 covers the second metal layer 203. A second dielectric layer 205 is formed on the isolation layer 204, and a second interconnect layer 206 is embedded in the second dielectric layer 205 and the isolation layer 204. The second interconnect layer 206 is electrically connected (not shown) to the second metal layer 203 for leading out an electrical signal of the second wafer 20. The second wafer 20 has a third convex portion (not shown) or a third concave portion C₂. The first wafer may be controlled to create bumps or depressions to correspondingly mate with the second wafer 20. The second wafer 20 has a thirdDepressed part C₂Illustratively, the third recess C₂Formed in the second dielectric layer 205 of the non-metallic layer region II of the second wafer 20.

The isolation layer 204 in the second wafer 20 may have a single-layer structure or a composite isolation layer structure. When the isolation layer 204 is a composite isolation layer structure, it may include a first isolation layer and a second isolation layer (not shown), which may be the same as the adjustment layers (the first adjustment layer 104a and the second adjustment layer 104b) of the first wafer 10. Illustratively, a first isolation layer covers the second metal layer 203 and the second substrate 201, and the first isolation layer located in the non-metal layer region II is lower than the first isolation layer located in the metal layer region I. The second isolation layer is located nonmetal layer region II and covers first isolation layer, the second isolation layer is higher than or is less than and is located metal level region I first isolation layer forms protruding or sunken in nonmetal layer region II. The second dielectric layer 205 covers the isolation layer 204, and a third protrusion or a third recess is correspondingly formed in the non-metal layer region II. The formation methods, structures and materials of the first isolation layer and the second isolation layer are the same as those of the first adjustment layer 104a and the second adjustment layer 104b, and the formation methods, structures and materials of the first adjustment layer 104a and the second adjustment layer 104b can be referred to, and are not described herein again.

As shown in fig. 6 and 7, the first wafer 10 and the second wafer 20 are mixed-bonded, and the second protrusions B₁And the third recessed part C₂And (6) matching. Third recess C of non-metal layer area II of second wafer 20₂And the second protrusion B of the first wafer 10₁And occlusion is realized, and bonding gaps are reduced. Finally, projections or depressions on the microscopic scale are formed on the bonding surface, and can be occluded with the non-metal layer region II (such as a cutting path region) of the second wafer, so that the bonding gap is reduced, and the process quality and the product yield are improved.

The present invention also provides a wafer bonding structure, as shown in fig. 4a to 7, including:

a first wafer 10, the first wafer 10 including a first substrate 101 and a first metal layer 103 located above the first substrate 101; the first wafer 10 includes a non-metal layer region II and a metal layer region I on which the first metal layer 103 is distributed;

a first adjustment layer 104a, wherein the first adjustment layer 104a covers the first metal layer 103 and the first substrate 101, and the first adjustment layer 104a in the non-metal layer region II is lower than the first adjustment layer 104a in the metal layer region I;

a second adjustment layer 104b, wherein the second adjustment layer 104b is located in the non-metal layer region II and covers the first adjustment layer 104a, the second adjustment layer 104b is higher or lower than the first adjustment layer 104a located in the metal layer region I, and a first protrusion a is formed in the non-metal layer region II₁Or the first recess A₂。

Specifically, the first adjustment layer 104a and the second adjustment layer 104b are configured to be polished at different rates by the same polishing slurry.

Further, the wafer bonding structure further includes:

a first dielectric layer 105, the first dielectric layer 105 covering the first adjustment layer 104a and the second adjustment layer 104 b; the first dielectric layer 105 is distributed with openings; in the non-metal layer region II, the first dielectric layer 105 has a second protrusion B₁Or a second recess;

a first interconnect layer 106, the first interconnect layer 106 filling in the opening;

a second wafer 20, the second wafer 20 having a third convex portion (not shown) or a third concave portion C₂；

The first wafer is bonded with the second wafer, the third convex part is matched with the second concave part, or the third concave part C₂And the second convex part B₁And (6) matching.

As shown in fig. 7, in the wafer bonding structure of this embodiment, the non-metal layer region II includes a scribe line region between the chip structures arranged in an array on the first wafer 10 and/or a region without a metal layer distributed in a single chip structure in the first wafer. The non-metal layer region further includes a dicing street region between chip structures arranged in an array on the second wafer 20 and/or a region where no metal layer is distributed in a single chip structure in the second wafer 20.

When the non-metal layer region II is a region in which a metal layer is not distributed in each of the single chip structures of the first wafer 10 and the second wafer 20, or the non-metal layer region II is a dicing channel region between a region in which a metal layer is not distributed in each of the single chip structures of the first wafer 10 and the second wafer 20 and each of the array-arranged chip structures, the wafer bonding structure is diced to obtain the following chip bonding structure of this embodiment, which is consistent with the structure shown in fig. 7. The present invention also provides a chip bonding structure, comprising:

a first chip comprising a first substrate and a first metal layer over the first substrate; the first chip comprises a non-metal layer area and a metal layer area distributed with the first metal layer;

a first adjustment layer covering the first metal layer and the first substrate, the first adjustment layer located in the non-metal layer region being lower than the first adjustment layer located in the metal layer region;

the second adjusting layer is located in the non-metal layer area and covers the first adjusting layer, the second adjusting layer is higher than or lower than the first adjusting layer located in the metal layer area, and a first protruding portion or a first recessed portion is formed in the non-metal layer area.

Further, the method also comprises the following steps:

the first dielectric layer covers the first adjusting layer and the second adjusting layer; the first dielectric layer is distributed with openings; in the non-metal layer region, the first medium layer is provided with a second convex part or a second concave part;

a first interconnect layer filled in the opening;

a second chip having a third protrusion or a third recess;

the first chip is bonded with the second chip, and the third protruding portion is matched with the second recessed portion, or the third recessed portion is matched with the second protruding portion.

In summary, in the wafer bonding structure, the wafer bonding method and the chip bonding structure provided by the present invention, the first wafer includes the non-metal layer region and the metal layer region on which the first metal layer is distributed; the first adjusting layer located in the non-metal layer area is lower than the first adjusting layer located in the metal layer area; the second adjusting layer covers the first adjusting layer; and chemically and mechanically grinding the second adjusting layer and the first adjusting layer, wherein the grinding rates of grinding liquid to the first adjusting layer and the second adjusting layer are different, so that the second adjusting layer remained in the non-metal layer area is higher or lower than the first adjusting layer remained in the metal layer area, and a first convex part or a first concave part is formed in the non-metal layer area so as to match with a wafer or a chip which is bonded with the wafer or the chip and has a concave or convex part. Reduce bonding clearance, improve technology quality and product yield. The local position depression caused by the chemical mechanical polishing process is eliminated or reduced, the bonding gap between the upper wafer and the lower wafer is corrected, and the bonding strength and the bonding quality are improved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is simple because the method is matched with the device disclosed by the embodiment, and the relevant part can be referred to the description of the method part.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.