阅读说明：本技术 一种集成后偏移量的测量方法 (Method for measuring offset after integration ) 是由 戴家赟 王飞 王元 许理达 刘俊修 朱健 陈堂胜 于 2020-06-04 设计创作，主要内容包括：本发明公开了一种集成后偏移量的测量方法,所述方法包括如下步骤：在第一、第二待集成衬底上分别设置键合偏差测试矩阵,测试矩阵中布置有键合结构和与键合结构一一对应并相连的金属布线；采用直流测试设备分别对测试矩阵里的键合结构进行直流测试,得到键合导通结果；根据测试矩阵中的键合导通结果,得到集成后偏移量的偏离方向和偏离数值。本发明的测量方法能够提高键合偏差的测试准确性和便捷性,减少失效分析时间,增加工艺监控质量,为三维异质异构集成工艺的良率提升和成本降低提供保障。(The invention discloses a method for measuring an integrated offset, which comprises the following steps: respectively arranging bonding deviation test matrixes on a first substrate to be integrated and a second substrate to be integrated, wherein the test matrixes are internally provided with bonding structures and metal wiring lines which are in one-to-one correspondence with the bonding structures and are connected with the bonding structures; respectively carrying out direct current test on the bonding structures in the test matrix by adopting direct current test equipment to obtain bonding conduction results; and obtaining the deviation direction and the deviation value of the integrated deviation quantity according to the bonding conduction result in the test matrix. The measuring method can improve the testing accuracy and convenience of the bonding deviation, reduce failure analysis time, increase process monitoring quality and provide guarantee for yield improvement and cost reduction of the three-dimensional heterogeneous integrated process.)

1. A method for measuring an integrated offset amount is characterized by comprising the following steps:

(1) Respectively arranging bonding deviation test matrixes on a first substrate to be integrated and a second substrate to be integrated, wherein the test matrixes are internally provided with bonding structures and metal wiring lines which are in one-to-one correspondence with the bonding structures and are connected with the bonding structures;

(2) respectively carrying out direct current test on the bonding structures in the test matrix by adopting direct current test equipment to obtain bonding conduction results;

(3) and obtaining the deviation direction and the deviation value of the integrated deviation quantity according to the bonding conduction result in the test matrix.

2. The method as claimed in claim 1, wherein the first and second substrates to be integrated are any one of semiconductor chips or wafers of Si, GaAs, GaN, InP.

3. The method of claim 1, wherein the bonding deviation test matrix comprises a cross-shaped bonding pattern on the first substrate to be integrated, the cross-shaped bonding pattern being symmetrical with respect to the center, and metal wires connected to the bonding pattern, the cross-shaped bonding pattern having a horizontal axis corresponding to the X-axis, a right direction corresponding to the X-axis, a vertical axis corresponding to the Y-axis, and an upper direction corresponding to the positive direction.

4. The method as claimed in claim 3, characterized in that the width w of the "cross" bar-shaped bonding pattern on the first substrate to be integrated ranges from 2 μm to 10 μm and the length h ranges from 10 μm to 200 μm.

5. The method of claim 3, wherein the bonding deviation test matrix comprises a set of discrete bonding pattern blocks crossing each other and metal wires connected to each discrete bonding pattern block on the second substrate to be integrated;

arranging N bonding pattern blocks with vertical spacing a and horizontal spacing c on a positive half shaft and a negative half shaft of an X axis, arranging N bonding pattern blocks with vertical spacing c and horizontal spacing a on the positive half shaft and the negative half shaft of a Y axis, wherein the value of a is 0.2-2 mu m, the value of c is 1-5 mu m, and a metal wiring connected with each discrete bonding pattern block is used as a direct current test output end;

the X-axis positive half shaft part is provided with a bonding pattern block on the upper side of the positive half shaft, and the X-axis negative half shaft part is provided with a bonding pattern block on the lower side of the negative half shaft; in the Y-axis positive half shaft part, the bonding pattern block is positioned on the right side of the positive half shaft, and in the negative half shaft part, the bonding pattern block is positioned on the left side of the negative half shaft.

6. The method as claimed in claim 5, characterized in that the discrete bonding pattern blocks on the second substrate to be integrated are square with a side length d of between 1 μm and 10 μm.

7. The method as claimed in claim 6, characterized in that the relationship between the width w of the cross-shaped bar-shaped bonding pattern on the first substrate to be integrated and the number N of discrete bonding pattern blocks on the second substrate to be integrated, the fixed value a and the fixed value d is in accordance with (a × N-d/2) ═ w/2, and the relationship between the length h of the cross-shaped bar-shaped bonding pattern on the first substrate to be integrated and the number N and c of discrete bonding pattern blocks on the second substrate to be integrated and the side length d is in accordance with c × N + d/2< h/2; that is, on the positive and negative half axes of X, Y, in the perfect alignment condition, there is and only the nth key pattern block just outside the bar-shaped key pattern, and the remaining 1 st to N-1 st key pattern blocks are all overlapped with the bar-shaped key pattern.

8. The method according to any of claims 1-7, characterized in that, in the fully aligned condition, the center points of the bonding patterns in the bonding variation test matrix on the first and second substrates to be integrated coincide.

9. The method according to any one of claims 1 to 7, wherein each group of test modules is subjected to current test by using a direct current test device, and the direct current test method comprises the following steps: the voltage is-2 to 2V, and the current is 0.01mA to 1 mA.

10. The method of claim 7, wherein when the two substrates are fully aligned, the X, Y direction is offset by an amount β_X＝β_YWhen the number is 0, only the Nth group of bonding pattern blocks on the second substrate are just not contacted with the cross-shaped bonding pattern on the first substrate, and the rest bonding pattern blocks and the cross-shaped bonding pattern are mutually contacted and conducted; at this time, the test results of the four half shafts of the positive X axis, the negative X axis, the positive Y axis and the negative Y axis are (1, 1 … … 1, 0), namely the test results except the Nth bonding graph block are all 1;

if the two substrates have deviation, firstly judging the deviation direction according to the test result of the Nth group of bonding pattern blocks on different half shafts in the bonding deviation test matrix; if the N-th bit test result on a certain half shaft is changed from 0 to 1, the direction represented by the half shaft is deviated; if the test result of the Nth group of patterns on the positive half axis of the X axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the Y axis; if the test result of the Nth group of patterns on the X-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the Y-axis negative direction; if the test result of the Nth group of patterns on the positive half axis of the Y axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the X axis; if the test result of the Nth group of patterns on the Y-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the X-axis negative direction;

And then judging the deviation amount according to the test results of the rest bonding pattern blocks in the test matrix, if the test result of the M +1 th group of bonding pattern blocks is 0, and the test result of the M th group of bonding pattern blocks is 1, the value of the deviation amount represented on the half axis is a x (N-M-1) < beta < a x (N-M), wherein M is any integer between 0,1 and 2 … … N-1, and the absolute value of the deviation amount is beta < a x N.

Technical Field

The invention relates to the technical field of semiconductor processes, in particular to a method for measuring an integrated offset.

Background

The semiconductor chip three-dimensional stacking integration technology is one of the key ways for further miniaturization, light weight, multiple functions and intellectualization of electronic components in the post-molar age, and the multilayer semiconductor devices or wafers are stacked and integrated in the vertical direction, so that the limitation of the existing integrated circuit in the aspects of physics and materials is broken through. However, due to the characteristics of the materials, the alignment method and the introduction of various factors during the process, the integrated chips and the wafers have alignment deviation after being bonded. The alignment precision between the chip wafers directly determines the precision of subsequent integrated interconnection and the comprehensive performance of the circuit. When the alignment deviation is large, the bonded pattern which should be aligned and bonded up and down in the layout design will be offset and dislocated, resulting in the occurrence of abnormal circuit breaking or short circuit in the interconnection structure, and further affecting the product yield.

In addition, since compound semiconductor materials such as silicon, GaAs, InP and the like are not transparent under visible light, and are limited by the very low infrared transmittance of low-resistance substrate materials and the accuracy problem of the infrared characterization method, it is difficult to directly and accurately characterize bonding deviation by an optical detection method, and the requirement for accurate monitoring of the process cannot be satisfied. The existing analysis means generally comprises the steps of cutting a section of an integrated sample, and then measuring alignment deviation through a high-resolution scanning tunnel microscope, wherein the method belongs to destructive analysis and is complex to use and time-consuming. Therefore, it is urgently needed to develop a method for conveniently and accurately measuring the deviation value of the integrated chip or the wafer after bonding.

Disclosure of Invention

The invention aims to provide a method for measuring the offset after integration, which measures and calculates the offset value and the offset direction of alignment offset after bonding by setting an offset test matrix and performing direct current electrical test.

The technical solution for realizing the purpose of the invention is as follows: a method for measuring an offset after integration comprises the following steps:

(1) respectively arranging bonding deviation test matrixes on a first substrate to be integrated and a second substrate to be integrated, wherein the test matrixes are internally provided with bonding structures and metal wiring lines which are in one-to-one correspondence with the bonding structures and are connected with the bonding structures;

(2) Respectively carrying out direct current test on the bonding structures in the test matrix by adopting direct current test equipment to obtain bonding conduction results;

(3) and obtaining the deviation direction and the deviation value of the integrated deviation quantity according to the bonding conduction result in the test matrix.

Preferably, the first substrate to be integrated and the second substrate to be integrated are any one of semiconductor material chips or wafers of Si, GaAs, GaN, InP.

Preferably, the bonding deviation test matrix includes a cross-shaped bar-shaped bonding pattern which is mutually crossed and is in central symmetry on the first substrate to be integrated, and a metal wiring connected with the bonding pattern, wherein a transverse axis of the cross-shaped bar-shaped bonding pattern corresponds to an X axis, a rightward direction is a positive direction, a longitudinal axis is a Y axis, and an upward direction is a positive direction.

Preferably, the width w of the "cross" shaped bar-shaped bonding pattern on the first substrate to be integrated ranges from 2 μm to 10 μm, and the length h ranges from 10 μm to 200 μm.

Preferably, the bonding deviation test matrix comprises a group of discrete bonding pattern blocks which are intersected with each other and a metal wiring connected with each discrete bonding pattern block on a second substrate to be integrated;

the arrangement method of the discrete bonding graph blocks comprises the following steps: arranging N bonding pattern blocks with vertical spacing a and horizontal spacing c on a positive half shaft and a negative half shaft of an X shaft, arranging N bonding pattern blocks with vertical spacing c and horizontal spacing a on the positive half shaft and the negative half shaft of the Y shaft, wherein the numerical value of a is 0.2-2 mu m, the numerical value of c is 1-5 mu m, and metal wiring connected with each discrete bonding pattern block is used as a direct current test output end;

The X-axis positive half shaft part is provided with a bonding pattern block on the upper side of the positive half shaft, and the X-axis negative half shaft part is provided with a bonding pattern block on the lower side of the negative half shaft; in the Y-axis positive half shaft part, the bonding pattern block is positioned on the right side of the positive half shaft, and in the negative half shaft part, the bonding pattern block is positioned on the left side of the negative half shaft.

Preferably, the discrete bonding pattern block on the second substrate to be integrated is a square with a side length d between 1 μm and 10 μm.

Preferably, the relationship between the width w of the cross-shaped strip-shaped bonding pattern on the first substrate to be integrated and the number N, the fixed value a and the fixed value d of the discrete bonding pattern blocks on the second substrate to be integrated is in accordance with (a × N-d/2) ═ w/2, and the relationship between the length h of the cross-shaped strip-shaped bonding pattern on the first substrate to be integrated and the number N, the fixed value c and the side length d of the discrete bonding pattern blocks on the second substrate to be integrated is in accordance with c × N + d/2< h/2; that is, on the positive and negative half axes of X, Y, in the perfect alignment condition, there is and only the nth key pattern block just outside the bar-shaped key pattern, and the remaining 1 st to N-1 st key pattern blocks are all overlapped with the bar-shaped key pattern.

Preferably, under the condition of perfect alignment, the central points of the bonding patterns in the bonding deviation test matrix on the first and second substrates to be integrated are coincident.

Preferably, a direct current test device is used for performing current test on each group of test modules, and the direct current test method comprises the following steps: the voltage is-2 to 2V, and the current is 0.01mA to 1 mA.

Preferably, when the two substrates are perfectly aligned, i.e., X, Y is offset by an amount β_X＝β_YWhen the number is 0, only the Nth group of bonding pattern blocks on the second substrate are just not contacted with the cross-shaped bonding pattern on the first substrate, and the rest bonding pattern blocks and the cross-shaped bonding pattern are mutually contacted and conducted; at this time, the test results of the four half shafts of the positive X axis, the negative X axis, the positive Y axis and the negative Y axis are (1, 1 … … 1, 0), namely the test results except the Nth bonding graph block are all 1;

if the two substrates have deviation, firstly judging the deviation direction according to the test result of the Nth group of bonding pattern blocks on different half shafts in the bonding deviation test matrix; if the N-th bit test result on a certain half shaft is changed from 0 to 1, the direction represented by the half shaft is deviated; if the test result of the Nth group of patterns on the positive half axis of the X axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the Y axis; if the test result of the Nth group of patterns on the X-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the Y-axis negative direction; if the test result of the Nth group of patterns on the positive half axis of the Y axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the X axis; if the test result of the Nth group of patterns on the Y-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the X-axis negative direction;

And then judging the deviation amount according to the test results of the rest bonding pattern blocks in the test matrix, if the test result of the M +1 th group of bonding pattern blocks is 0, and the test result of the M th group of bonding pattern blocks is 1, the value of the deviation amount represented on the half shaft is a x (N-M-1) < beta < a x (N-M), wherein M is any integer between 0,1 and 2 … … N-1, and the absolute value of the deviation amount is beta < a x N.

Compared with the prior art, the invention has the following remarkable advantages: the testing method of the invention tests the conduction result of each group of bonding patterns by arranging a bonding deviation testing matrix on a substrate to be integrated and taking a metal pressing block led out by the bonding patterns in the testing matrix as a testing port; obtaining deviation direction and deviation of the integrated deviation according to the conduction result of each group of bonding patterns; the method can conveniently and accurately test the alignment deviation direction and deviation amount after bonding removal on the premise of not damaging the sample, and ensures effective monitoring of the integration process.

Drawings

For a more complete understanding of the objects, features and advantages of the present invention, reference is now made to the following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a schematic flow chart of measuring alignment deviation after integration according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a bonding variation test matrix.

FIG. 3 is a schematic view of a bonding bias configuration with full alignment.

Fig. 4 is a schematic diagram showing the case where the first substrate is shifted in the positive X-axis direction with respect to the second substrate.

Fig. 5 is a schematic view showing a case where the first substrate is shifted in the positive Y-axis direction with respect to the second substrate.

FIG. 6 is a schematic diagram of a bonding alignment deviation test bonding configuration with a first substrate being deviated in a negative X-axis direction and a positive Y-axis direction relative to a second substrate.

X⁺ _M: the Mth keying graph block in the positive direction of the X axis;

Y^- _N: the Nth key map block in the Y-axis negative direction;

β_x: a positional deviation in the X direction;

β_y: y-direction position deviation;

β_xy: the diagonal direction position is shifted.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

The invention discloses a precise characterization method of an integrated offset, which comprises the following steps as shown in figure 1:

step S01, respectively arranging bonding deviation test matrixes on the first substrate to be integrated and the second substrate to be integrated, wherein the test matrixes are internally provided with bonding structures and metal wiring lines which are in one-to-one correspondence with the bonding structures and are connected with the bonding structures;

specifically, the bonding deviation test matrix shown in fig. 2 is respectively disposed on a first substrate to be integrated and a second substrate to be integrated, where the substrate to be integrated may be a semiconductor material chip or wafer including but not limited to Si, GaAs, GaN, InP, etc., such as a Si CMOS wafer and a GaAs chip;

furthermore, a proper test area is selected to arrange a bonding deviation test matrix on the first substrate and the second substrate according to the actual situation, wherein the bonding deviation test matrix shown in fig. 2 comprises a cross-shaped bar-shaped bonding pattern which is mutually crossed and is centrosymmetric and is similar to a coordinate axis on the first substrate to be integrated, the transverse axis of the cross-shaped bar-shaped bonding pattern corresponds to an X axis, the rightward direction is taken as the positive direction, the longitudinal axis corresponds to a Y axis, and the upward direction is taken as the positive direction;

furthermore, the width w of the cross-shaped strip-shaped bonding pattern on the first substrate to be integrated ranges from 2 micrometers to 20 micrometers, and the length h ranges from 10 micrometers to 200 micrometers. In the embodiment shown in FIG. 6, w is 10 μm and h is 80 μm;

Furthermore, the bonding deviation test matrix comprises a group of discrete bonding pattern blocks which are mutually crossed on a second substrate to be integrated, the discrete bonding pattern blocks are arranged by arranging N bonding pattern blocks with vertical spacing a and horizontal spacing c on a positive half shaft and a negative half shaft of an X axis, arranging N bonding pattern blocks with vertical spacing c and horizontal spacing a on a positive half shaft and a negative half shaft of a Y axis and uniformly distributing the N bonding pattern blocks and the Y axis, wherein the value of a is 0.2-2 mu m, the value of c is 1-5 mu m, and the specific value depends on the test precision to be obtained, and metal wiring connected with each discrete bonding pattern block is used as a direct current test output end. The X-axis positive half shaft part is provided with a bonding pattern block on the upper side of the positive half shaft, and the X-axis negative half shaft part is provided with a bonding pattern block on the lower side of the negative half shaft; in the Y-axis positive half shaft part, the bonding pattern block is positioned on the right side of the positive half shaft, and in the Y-axis negative half shaft part, the bonding pattern block is positioned on the left side of the negative half shaft. In the embodiment shown in FIG. 6, N has a value of 6, a has a value of 1 μm, and c has a value of 5 μm;

further, the discrete bonding pattern block on the second substrate to be integrated as shown in fig. 6 is a square with a side length d between 1 μm and 10 μm, and in this embodiment, the value of d is 2 μm;

Furthermore, the relationship between the width w of the "cross" shaped bar-shaped bonding pattern on the first substrate to be integrated and the number N of discrete bonding pattern pieces on the second substrate to be integrated and the fixed value a and the side length d is in accordance with (a × N-d/2) ═ w/2, as in the embodiment shown in fig. 6, (a × N-d/2) ═ 1 × 6-2/2 ═ 5 ═ 10/2 ═ w/2;

furthermore, the relationship between the length h of the cross-shaped bar-shaped bonding pattern on the first substrate to be integrated and the number N of discrete bonding pattern pieces on the second substrate to be integrated and the fixed value c and the side length d is c × N + d/2< h/2, as in the embodiment shown in fig. 6, (c × N-d/2) ═ 5 × 6+2/2 ═ 31 < 80/2 ═ h/2;

further, the embodiment shown in fig. 2 and 3 has the positive and negative half shafts X, Y with the N-th key pattern block just not contacting the bar-shaped key pattern and the rest of the key pattern blocks contacting the bar-shaped key pattern in perfect alignment;

further, as shown in fig. 2 and 3, in the fully aligned condition, the center points of the bonding patterns in the bonding deviation test matrix on the first and second substrates coincide;

step S02, performing direct current test on the bonding patterns in the test matrix by using direct current test equipment to obtain bonding conduction results;

Specifically, direct current electrical test equipment is adopted to respectively carry out direct current test on 1-N groups of bonding patterns on positive and negative half shafts of X, Y, and whether corresponding input and output ends are conducted or not is tested. By applying a voltage to the input end, if the current is successfully detected by the output end, the input end and the output end are turned on;

further, under a positive load condition, if the port is conducted, outputting 1; if not, 0 is output;

furthermore, the adopted voltage value range is-2V, and the output current is 0.01 mA-1 mA.

And step S03, obtaining the deviation direction and the deviation value of the integrated deviation quantity according to the bonding conduction result in the test matrix.

When the two substrates are perfectly aligned, i.e. X, Y is offset by an amount beta_X＝β_YWhen the number is 0, only the Nth group of bonding pattern blocks on the second substrate are just not contacted with the cross-shaped bonding pattern on the first substrate, and the rest bonding pattern blocks and the cross-shaped bonding pattern are mutually contacted and conducted; at this time, the test results of the four half shafts of the positive X axis, the negative X axis, the positive Y axis and the negative Y axis are (1, 1 … … 1, 0), namely the test results except the Nth bonding graph block are all 1;

if the two substrates have deviation, firstly judging the deviation direction according to the test result of the Nth group of bonding pattern blocks on different half shafts in the bonding deviation test matrix; if the N-th bit test result on a certain half shaft is changed from 0 to 1, the direction represented by the half shaft is deviated; if the test result of the Nth group of patterns on the positive half axis of the X axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the Y axis, as shown in FIG. 5; if the test result of the Nth group of patterns on the X-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the Y-axis negative direction; if the test result of the Nth group of patterns on the positive half axis of the Y axis is 1, the deviation direction of the first substrate relative to the second substrate is the positive direction of the X axis, as shown in FIG. 4; if the test result of the Nth group of patterns on the Y-axis negative half shaft is 1, the deviation direction of the first substrate relative to the second substrate is the X-axis negative direction;

Specifically, the test results of each group of deviation test modules in step S02 are collected to obtain four groups of nth test results on the positive and negative half shafts X, Y, and the deviation direction is determined according to the nth test results, wherein the deviation direction measured in the method includes a positive X direction, a negative X direction, a positive Y direction, a negative Y direction and a combination of several directions; in the embodiment shown in FIG. 3, the Nth test results of the four sets are all 0, indicating that the two chips or wafers are completely aligned; if the result of the test of the Nth bit on a certain half axis changes from 0 to 1, the direction represented by the half axis is deviated. In the embodiment shown in fig. 6, the nth bit test results in the Y-axis negative half axis and the X-axis positive half axis are both 1, which illustrates that the deviation directions of the first substrate with respect to the second substrate in this embodiment are the X-axis negative direction and the Y-axis positive direction;

further, the deviation is judged according to the test result of the bonding pattern block in the test matrix, wherein the absolute value of the deviation beta is beta<a is multiplied by N; if the test result of the M +1 th group of the bonding pattern blocks is 0 and the test result of the M-th group of the bonding pattern blocks is 1, the value of the offset represented by the half shaft is a x (N-M-1)<β<a × (N-M), wherein M is any integer between 0,1,2 … … N-1; in the embodiment shown in FIG. 6, on the negative half axis of the X-axis, X ^- ₄Test result of (2) is 0, and X^- ₃The test result of (1) indicates that the first substrate is opposite to the second substrateThe substrate was deviated in the positive Y-axis direction by 1X (6-3-1)<β_y<1 × (6-3), i.e. 2<β_y<3; while on the positive half-axis of the Y-axis, Y⁺ ₃Test result of (2) is 0, and Y is⁺ ₂The result of the test of (1) shows that the first substrate is deviated from the second substrate by 1X (6-2-1) in the negative X-axis direction<β_x<1 × (6-2), i.e. 3<β_x<4。

In summary, according to the method for measuring the offset after integration, the offset direction and the offset value of the offset after integration are obtained according to the conduction result of the bonding structure in the test matrix by setting the offset test matrix and performing the direct current electrical test. The method can improve the accuracy and convenience of the test of the bonding deviation, reduce failure analysis time, increase process monitoring quality and provide guarantee for the yield improvement and cost reduction of the three-dimensional heterogeneous integrated process.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.