阅读说明：本技术 功耗管理电路及芯片 (Power consumption management circuit and chip ) 是由 姜文奇 刘苏 苏孟豪 于 2020-03-20 设计创作，主要内容包括：本发明实施例提供一种功耗管理电路及芯片,包括：信息采集单元、控制器、调节单元,控制器分别与信息采集单元和调节单元连接,其中,信息采集单元用于采集芯片的参数信息,并向控制器发送参数信息,参数信息包括温度和/或芯片的输入输出IO控制器的状态；控制器用于,根据参数信息生成控制指令,并向调节单元发送控制指令；调节单元用于,根据控制指令控制芯片中的预设部件,以对芯片的功耗进行管理。提高了功耗管理的及时性。(The embodiment of the invention provides a power consumption management circuit and a chip, comprising: the chip comprises an information acquisition unit, a controller and an adjusting unit, wherein the controller is respectively connected with the information acquisition unit and the adjusting unit, the information acquisition unit is used for acquiring parameter information of the chip and sending the parameter information to the controller, and the parameter information comprises temperature and/or the state of an input/output (IO) controller of the chip; the controller is used for generating a control instruction according to the parameter information and sending the control instruction to the adjusting unit; the adjusting unit is used for controlling preset components in the chip according to the control instruction so as to manage the power consumption of the chip. The timeliness of power consumption management is improved.)

1. A power management circuit, comprising: an information acquisition unit, a controller and an adjusting unit, wherein the controller is respectively connected with the information acquisition unit and the adjusting unit,

the information acquisition unit is used for acquiring parameter information of a chip and sending the parameter information to the controller, wherein the parameter information comprises temperature and/or the state of an input/output (IO) controller of the chip;

the controller is used for generating a control instruction according to the parameter information and sending the control instruction to the adjusting unit;

and the adjusting unit is used for controlling a preset component in the chip according to the control instruction so as to manage the power consumption of the chip.

2. The power management circuit of claim 1, wherein the information acquisition unit comprises a temperature acquisition unit and/or a status monitor, wherein,

the temperature acquisition unit comprises a temperature sensor and is used for acquiring the temperature;

the state monitor is used for acquiring the state of the IO controller.

3. The power consumption management circuit according to claim 1 or 2, wherein the adjusting unit comprises a first adjusting unit and/or a second adjusting unit, and the controller is specifically configured to:

generating a first control instruction according to the temperature, and sending the first control instruction to the first adjusting unit; and/or the presence of a gas in the gas,

and generating a second control instruction according to the state of the IO controller, and sending the second control instruction to the second adjusting unit.

4. The power consumption management circuit of claim 3, wherein the controller is specifically configured to:

and when the temperature is greater than or equal to a preset threshold value, generating the first control instruction.

5. The power consumption management circuit of claim 3, wherein the controller is specifically configured to:

and generating the second control instruction when the state of the IO controller is an idle state.

6. The power consumption management circuit of claim 3, wherein the first adjustment unit is specifically configured to:

and reducing the voltage and/or frequency of a preset component in the chip according to the first control instruction, wherein the preset component comprises a processor and/or an IO controller.

7. The power consumption management circuit of claim 3, wherein the second adjustment unit is specifically configured to:

and the clock and the power supply of the IO controller are turned off according to the second control instruction.

8. The power management circuit of claim 1 or 2, further comprising a memory connected to the information acquisition unit and the controller, respectively, wherein,

the memory is used for storing the parameter information acquired by the information acquisition unit.

9. The power management circuit of claim 8, wherein the memory is further coupled to the processor.

10. A chip, comprising: a processor, an IO controller, and the power management circuit of any of claims 1-9;

the power consumption management circuit is respectively connected with the processor and the IO controller.

Technical Field

The embodiment of the invention relates to the technical field of circuits, in particular to a power consumption management circuit and a chip.

Background

With the development of semiconductor process technology, the performance of a chip is significantly improved, and meanwhile, the overall power consumption of the chip is higher and higher, so that the power consumption management of the chip is also a problem which needs to be considered in a key manner at present.

In the prior art, a method for managing power consumption of a chip includes: an application system software layer is arranged in the chip and can collect the working log of the chip, whether the power consumption of the chip is in a normal range or not is analyzed through the working log of the chip, and when the power consumption of the chip is higher or lower than the normal range, the chip adjusts the voltage, the clock frequency and other parameters of the chip through the application system software layer, so that the purpose of power consumption management of the chip is achieved.

However, this method needs to perform power consumption control through a system software layer, and before performing power consumption control, it needs to collect a working log of a chip first and analyze whether the power consumption of the chip is normal through the working log.

Disclosure of Invention

The embodiment of the invention provides a power consumption management circuit and a chip, which are used for improving the timeliness of power consumption management.

In a first aspect, the present invention provides a power management circuit, including: an information acquisition unit, a controller and an adjusting unit, wherein the controller is respectively connected with the information acquisition unit and the adjusting unit,

the information acquisition unit is used for acquiring parameter information of a chip and sending the parameter information to the controller, wherein the parameter information comprises temperature and/or the state of an input/output (IO) controller of the chip;

the controller is used for generating a control instruction according to the parameter information and sending the control instruction to the adjusting unit;

and the adjusting unit is used for controlling a preset component in the chip according to the control instruction so as to manage the power consumption of the chip.

In one possible embodiment, the information acquisition unit comprises a temperature acquisition unit and/or a status monitor, wherein,

the temperature acquisition unit comprises a temperature sensor and is used for acquiring the temperature;

the state monitor is used for acquiring the state of the IO controller.

In a possible embodiment, the adjusting unit comprises a first adjusting unit and/or a second adjusting unit, and the controller is specifically configured to:

generating a first control instruction according to the temperature, and sending the first control instruction to the first adjusting unit; and/or the presence of a gas in the gas,

and generating a second control instruction according to the state of the IO controller, and sending the second control instruction to the second adjusting unit.

In a possible embodiment, the controller is specifically configured to:

and when the temperature is greater than or equal to a preset threshold value, generating the first control instruction.

In a possible embodiment, the controller is specifically configured to:

and generating the second control instruction when the state of the IO controller is an idle state.

In a possible embodiment, the first adjusting unit is specifically configured to:

and reducing the voltage and/or frequency of a preset component in the chip according to the first control instruction, wherein the preset component comprises a processor and/or an IO controller.

In a possible embodiment, the second adjusting unit is specifically configured to:

and the clock and the power supply of the IO controller are turned off according to the second control instruction.

In a possible implementation manner, the power consumption management circuit further comprises a memory, and the memory is respectively connected with the information acquisition unit and the controller, wherein,

the memory is used for storing the parameter information acquired by the information acquisition unit.

In a possible embodiment, the memory is further connected to the processor.

In a second aspect, an embodiment of the present invention provides a chip, including: a processor, an IO controller, and the power management circuit of any of the first aspects;

the power consumption management circuit is respectively connected with the processor and the IO controller.

The embodiment of the invention provides a power consumption management circuit and a chip, comprising: the chip comprises an information acquisition unit, a controller and an adjusting unit, wherein the controller is respectively connected with the information acquisition unit and the adjusting unit, the information acquisition unit is used for acquiring parameter information of the chip and sending the parameter information to the controller, and the parameter information comprises temperature and/or the state of an input/output (IO) controller of the chip; the controller is used for generating a control instruction according to the parameter information and sending the control instruction to the adjusting unit; the adjusting unit is used for controlling preset components in the chip according to the control instruction so as to manage the power consumption of the chip. In the process, the controller can control the adjusting unit to change the instantaneous power consumption of the preset part of the chip in real time through the information acquired by the information acquisition unit, namely, the technical scheme is adopted, the information related to the power consumption of the chip is acquired in real time through the hardware circuit, namely, before power consumption management, a working log of the preset part is not required to be collected, and the power consumption of the preset part is analyzed through the working log, so that the real-time management of the power consumption of the chip is realized, and the timeliness of the power consumption management is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a power consumption management circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another power management circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another power management circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a workflow of a power management circuit of an SOC chip according to an embodiment of the present invention;

fig. 7 is a schematic diagram of another operation flow of the power consumption management circuit of the SOC chip according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a power consumption management circuit according to an embodiment of the present invention. Referring to fig. 1, the power management circuit 10 includes: the system comprises an information acquisition unit 11, a controller 12 and an adjusting unit 13, wherein the controller 12 is respectively connected with the information acquisition unit 11 and the adjusting unit 13; the information acquisition unit 11 is configured to acquire parameter information of a chip and send the parameter information to the controller 12, where the parameter information includes a temperature and/or a state of an Input-Output (IO) controller 22 of the chip; the controller 12 is configured to generate a control instruction according to the parameter information, and send the control instruction to the adjusting unit 13; the regulating unit 13 is configured to control a preset component 20 in the chip according to the control instruction, so as to manage the power consumption of the chip.

Optionally, the parameter information may reflect power consumption of the chip, and the parameter information may include, but is not limited to, the following information: temperature of the chip, status of the chip's IO controller 22; the temperature may include the temperature of a chip and the temperature of a module with higher power consumption in the chip; the states of the chip's IO controller 22 may include the IO controller 22 being in an idle state and the IO controller 22 being in a busy state.

Optionally, when the information collecting unit 11 includes a temperature sensor, the parameter information may include a temperature, and the temperature sensor may collect the temperature of the chip or the temperature of a module with higher power consumption in the chip in real time and send the temperature data to the controller 12. The module with higher power consumption in the chip can be determined according to a preset module power consumption threshold value, that is, if the power consumption of any module in the chip is greater than the preset module power consumption threshold value, the any module is determined as the module with higher power consumption in the chip; otherwise, the arbitrary module is not the module with larger power consumption in the chip; in addition, the power consumption threshold of the preset module can be comprehensively determined according to various factors such as different chip types or working environments of the chips.

Optionally, when the information collecting unit 11 includes a state monitor, the parameter information may include a state of the IO controller 22, the information collecting unit 11 may collect an operating state of the IO controller 22 in real time, and the operating state of the IO controller 22 may include an idle state and a busy state. The information collecting unit 11 may send the collected operating state of the IO controller 22 to the controller 12 in real time.

Optionally, the Controller 12 may include, but is not limited to, a Micro Controller Unit (MCU), and the MCU may integrate a Memory, a counter, a Universal Serial Bus (USB), an analog-to-digital converter (adc), a Universal Asynchronous Receiver/Transmitter (UART), a Programmable Logic Controller (PLC), a Direct Memory Access (DMA), and other peripheral interfaces, and even a Laser Cladding Deposition (LCD) driving circuit on a single chip, so as to form a chip-level computer.

Alternatively, the Chip is an integrated circuit manufactured on the surface of a semiconductor wafer by miniaturizing a circuit including a semiconductor device, and for example, the Chip may include a System-on-a-Chip (SOC) Chip.

IO controller 22 may be a system that implements control of peripheral devices, for example, IO controller 22 may include an input-output device controller, and the functions of IO controller 22 may include: sending action command to peripheral equipment, controlling the transmission of input and output data and detecting the state of the peripheral equipment.

The controller 12 may generate a control instruction according to the parameter information, and control the adjusting unit 13 through the control instruction, thereby implementing management of chip power consumption.

The adjusting unit 13 can control the preset component 20 in the chip according to the control instruction; optionally, the preset component 20 may include a processor 21 and/or an IO controller 22; the processor 21 may include a Central Processing Unit (CPU).

Alternatively, the adjusting unit 13 may control the preset component 20 in the chip according to the control instruction through the following feasible implementation manners: when the parameter information acquired by the information acquisition unit 11 is temperature and the preset component 20 in the chip is a CPU, the adjustment unit 13 may adjust the clock frequency or the voltage amplitude of the CPU according to the control instruction, thereby implementing adjustment of the chip power.

Alternatively, the adjusting unit 13 may control the preset components in the chip according to the control instruction through the following feasible implementation manners: when the parameter information acquired by the information acquisition unit 11 is the state of the IO controller of the chip and the preset component 20 in the chip is the IO controller, the adjustment unit 13 may turn off the clock and the power supply of the IO controller according to the control instruction, thereby reducing the power consumption of the chip and realizing the adjustment of the chip power.

Next, the operation of the power consumption management circuit 10 will be described.

The information collecting unit 11 may collect parameter information of the chip in real time and transmit the parameter information to the controller 12.

After receiving the parameter information sent by the information acquisition unit 11, the controller 12 determines whether to generate a control command according to the parameter information. Optionally, when the parameter information acquired by the information acquisition unit 11 is temperature, the controller 12 determines whether to generate a control instruction according to the received temperature. When the collected temperature is less than the preset threshold, the controller 12 does not generate a control command. When the collected temperature is greater than or equal to the preset threshold, the controller 12 generates a control command and sends the control command to the adjusting unit 13. Wherein the control instructions may be used to adjust the power consumption of the chip. Optionally, when the parameter information acquired by the information acquisition unit 11 is the state of the preset component 20, the controller 12 determines whether to generate the control instruction according to the received state of the preset component 20. When the status of the preset section 20 is a busy status, the controller 12 does not generate a control command. When the state of the preset section 20 is an idle state, the controller 12 generates a control command and sends the control command to the adjusting unit 13.

After receiving the control instruction sent by the controller 12, the adjusting unit 13 controls the preset component 20 in the chip according to the control instruction. Optionally, when the parameter information is temperature, the adjusting unit 13 may perform frequency reduction processing on the clock frequency of the preset component 20 according to the control instruction and a first preset step size, optionally, the frequency reduction processing mode may include, but is not limited to, a fine-grained frequency reduction processing mode, optionally, the first preset step size in the fine-grained frequency reduction processing process may be determined according to a chip manufacturing process and a power supply requirement of the chip, for example, if the change range of the clock frequency is set to ± 5Hz, the first preset step size of the fine-grained frequency reduction processing may be set to 0.1Hz or 0.2 Hz.

Optionally, after the clock frequency of the preset component 20 meets the preset condition, performing voltage reduction processing on the voltage amplitude of the preset component 20 according to the control instruction and a second preset step length; the preset condition may include, but is not limited to, that the clock frequency of the preset component 20 is equal to the preset clock frequency, and the step-down processing manner may include, but is not limited to, a fine-grained step-down processing manner; alternatively, the second preset step size in the fine-grained voltage reduction processing may be determined according to the process conditions of the preset component 20 and the power supply requirement, for example, if the change range of the voltage amplitude is set to ± 0.5V, the second preset step size in the fine-grained voltage reduction processing may be set to 0.01V or 0.02V.

Optionally, when the parameter information is the state of the IO controller 22 of the chip, the adjusting unit 13 may perform the shutdown isolation process on the preset component 20 according to the control instruction. Specifically, the adjusting unit 13 may perform the shutdown isolation process on the clock unit and/or the power supply unit of the preset component 20.

Optionally, when the parameter information is temperature, a glitch filtering process may be added in the process of down-converting the clock frequency of the preset component 20. Specifically, a filter circuit is arranged in the adjusting unit 13 to implement filtering processing of the glitch, so that the accuracy of power consumption management can be improved in the clock frequency down-conversion process. Alternatively, the filter circuit may be a hardware circuit that is described by a hardware description language and performs a glitch filtering process on the clock frequency in the frequency down process of the preset component 20. Alternatively, the filter circuit may be connected to the controller 12 and the adjusting unit 13, respectively, i.e. before the adjusting unit 13, or may be connected to the adjusting unit 13, i.e. after the adjusting unit 13.

The embodiment of the invention provides a power consumption management circuit, which comprises an information acquisition unit, a controller and an adjusting unit, wherein the controller is respectively connected with the information acquisition unit and the adjusting unit, the information acquisition unit is used for acquiring parameter information of a chip and sending the parameter information to the controller, and the parameter information comprises temperature and/or the state of an input/output (IO) controller of the chip; the controller is used for generating a control instruction according to the parameter information and sending the control instruction to the adjusting unit; the adjusting unit is used for controlling preset components in the chip according to the control instruction so as to manage the power consumption of the chip. In the process, the control unit can control the adjusting unit to change the instantaneous power consumption of the preset part of the chip in real time through the information acquired by the information acquisition unit, namely, the technical scheme is adopted, the information related to the power consumption of the chip is acquired in real time through the hardware circuit, namely, a working log of the preset part is not required to be collected before power consumption management is carried out, and the power consumption of the preset part is analyzed through the working log, so that the real-time management of the power consumption of the chip is realized, and the timeliness of the power consumption management is improved.

On the basis of the above-described embodiments, the structure of the power consumption management circuit shown in fig. 1 will be described in further detail below with reference to fig. 2 to 4.

Fig. 2 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention. Referring to fig. 2, the information collecting unit 11 may include a temperature collecting unit 111, and the temperature collecting unit 111 may include a temperature sensor for collecting temperature information. Accordingly, the adjusting unit 13 may include a first adjusting unit 131.

A temperature sensor is a sensor that senses temperature and converts it into a usable output signal. The temperature sensors may include semiconductor thermocouple sensors, PN junction temperature sensors, and integrated temperature sensors.

Optionally, when the parameter information of the chip collected by the temperature sensor is the temperature of the module with higher power consumption in the chip, the temperature sensor may be disposed near the module with higher power consumption in the chip.

Alternatively, the controller 12 may generate a first control instruction according to the temperature collected by the temperature collecting unit 111, and send the first control instruction to the first adjusting unit 131. The first adjusting unit 131 may adjust the clock frequency and/or the voltage amplitude of the preset part 20.

Alternatively, the controller 12 may generate the first control instruction when the temperature is greater than or equal to the preset threshold.

Alternatively, the controller 12 may decrease the voltage and/or frequency of the preset component 20 in the chip according to the first control instruction.

Optionally, the preset component 20 may include a processor 21 and/or an IO controller 22. The processor 21 is an operation and control core of a chip, and is a final execution unit for information processing and program running, for example, the processor 21 may include a CPU.

Optionally, the chip exterior may comprise a power supply part 30, the power supply part 30 being used to power the chip, e.g. the power supply part 30 may be used to power the processor 21 in the chip.

In practical applications, the temperature collecting unit 111 may collect temperature information of the chip and send the temperature information to the controller 12. After receiving the temperature information, the controller 12 determines whether to generate a control command based on the temperature information. When the temperature information is less than the preset threshold, the controller 12 does not generate the first control instruction. When the collected temperature information is greater than or equal to the preset threshold, the controller 12 generates a first control instruction and sends the first control instruction to the first adjusting unit 131. The first control instruction can be used for adjusting the power consumption of the chip.

After receiving the first control instruction sent by the controller 12, the first adjusting unit 131 performs frequency reduction processing on the clock frequency of the preset component 20 according to the first control instruction and a first preset step length; optionally, after the clock frequency of the preset component 20 meets the preset condition, the first adjusting unit 131 performs voltage reduction processing on the voltage amplitude of the preset component 20 according to the first control instruction and the second preset step length; further, the first adjusting unit 131 may perform a voltage reduction process on the voltage amplitude of the power supply component 30 according to the first control instruction and the second preset step length, so as to reduce the voltage amplitude of the preset component 20.

Fig. 3 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention. Referring to fig. 3, the information collecting unit 11 may include a status monitor 112, and the status monitor 112 may be used to acquire the status of the IO controller 22. Accordingly, the adjusting unit 13 may include a second adjusting unit 132.

Alternatively, the controller 12 may generate a second control instruction according to the state of the IO controller 22, and send the second control instruction to the second adjusting unit 132.

Optionally, the controller 12 may turn off the clock and/or power of the IO controller 22 according to the second control instruction.

Optionally, the status monitor 112 may also obtain a transmission rate of the bus, an occupancy of the bus, and the like, and the invention is not limited in particular.

In an actual application process, the status monitor 112 may collect the status of the IO controller 22, and send the status information of the IO controller 22 to the controller 12, and after receiving the status information, the controller 12 determines whether to generate the second control instruction according to the status information. When the status of the IO controller 22 is the idle status of the IO controller 22, the controller 12 generates a second control instruction and sends the second control instruction to the first adjusting unit 131. The second control instruction may be used to turn off the clock unit and/or the power supply unit of the IO controller 22, so as to reduce power consumption of the chip and achieve the purpose of power consumption management.

Fig. 4 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention. Referring to fig. 4, the information collecting unit 11 may include a temperature collecting unit 111 and a status monitor 112, and the temperature collecting unit 111 may include a temperature sensor for collecting temperature information. Accordingly, the adjusting unit 13 may include a first adjusting unit 131 and a second adjusting unit 132.

Wherein, the temperature acquisition unit 111 and the state monitor are respectively connected with the controller 12, and the first adjustment unit 131 and the second adjustment unit 132 are respectively connected with the controller 12.

Optionally, the first adjusting unit 131 may include a Dynamic Voltage and Frequency Scaling (DVFS) unit, the DVFS unit may be a unit that is described by a hardware description language and may dynamically adjust an operating Frequency and Voltage of the chip, the hardware description language is a language that describes a structure and a behavior of the digital system hardware in a text form, and the hardware description language may include but is not limited to: very High Speed Integrated Circuit Hardware Description Language (VHDL) and Verilog Hardware Description Language (Verilog Hardware Description Language, Verilog HDL).

Optionally, the second adjusting unit 132 may include a Dynamic Power Management (DPM) unit, where the DPM unit may be a unit that is described by a hardware description language and may dynamically manage Power, and specifically, the DPM unit may turn off a clock unit and/or a Power supply unit of the processor and/or the IO controller.

Alternatively, the status monitor 112 may be a hardware unit described by a hardware description language, and the status monitor 112 may acquire the status of the IO controller 22 in real time and send the status information of the IO controller 22 to the controller 12.

In the practical application process, the information collecting unit 11 may collect parameter information of the chip, specifically, temperature information that the temperature collecting unit 111 may collect, and send the temperature information to the controller 12. After receiving the temperature information, the controller 12 may determine whether to generate the first control command according to the temperature information. When the temperature information is less than the preset threshold, the controller 12 does not generate a control instruction. When the collected temperature information is greater than or equal to the preset threshold, the controller 12 generates a first control command and sends the first control command to the first adjusting unit 131.

The state monitor may obtain the state of the IO controller 22, and send the state information of the IO controller 22 to the controller 12, and after receiving the state information, the controller 12 determines whether to generate a control command according to the state information. When the status of the IO controller 22 is the idle status of the IO controller 22, the controller 12 generates a second control instruction and sends the second control instruction to the first adjusting unit 131.

After receiving the first control instruction sent by the controller 12, the first adjusting unit 131 performs frequency reduction processing on the clock frequencies of the CPU and the IO controller 22 in the preset component 20 according to the first control instruction and the first preset step length, and when the clock frequencies of the CPU and the IO controller 22 meet the preset condition, performs voltage reduction processing on the voltage amplitudes of the CPU and the IO controller 22 according to the first control instruction and the second preset step length. By reducing the clock frequency and the voltage amplitude of the CPU and the IO controller 22, the temperature of the CPU and the IO controller 22 in the chip is reduced, the power consumption of the chip is further reduced, and the purpose of power consumption management is achieved.

After receiving the second control instruction sent by the controller 12, the second adjusting unit 132 turns off the clock unit and/or the power supply unit of the IO controller 22 according to the second control instruction, so that the IO controller 22 in the idle state is in the power-off state, thereby further reducing the idle power consumption of the chip and achieving the purpose of power consumption management.

The embodiment of the invention provides a power consumption management circuit, which comprises a temperature acquisition unit, a state monitor, a controller, a first adjusting unit and a second adjusting unit, wherein the temperature acquisition unit and the state monitor are respectively connected with the controller, and the first adjusting unit and the second adjusting unit are respectively connected with the controller, wherein the temperature acquisition unit can acquire temperature information of a chip, the state monitor can acquire a working state of an IO controller, the temperature information acquired by the temperature acquisition unit and the state monitor can be respectively sent to the controller, the controller can generate a first control instruction according to parameter information acquired by the temperature acquisition unit and send the first control instruction to the first adjusting unit, and the controller can also generate a second control instruction according to the working state of the IO controller acquired by the state monitor and send the second control instruction to the second adjusting unit. The first adjusting unit can reduce the clock frequency and the voltage amplitude of a CPU and an IO controller in real time according to a first control instruction, so that the temperature of the CPU and the IO controller in a chip is reduced, the power consumption of the chip is reduced, the purpose of power consumption management is achieved, the timeliness of the power consumption management is improved, the second adjusting unit can turn off the clock unit and/or the power unit of the IO controller in real time according to a second control instruction, the IO controller in an idle state is in a power-off state, the no-load power consumption of the chip is further reduced, the purpose of power consumption management is achieved, and the timeliness of the power consumption management is further improved.

Based on any of the above embodiments, the following describes in further detail the structures of the power consumption management circuits shown in fig. 2 to 4 with reference to fig. 5.

Fig. 5 is a schematic structural diagram of another power consumption management circuit according to an embodiment of the present invention. Referring to fig. 5, the power consumption management circuit 10 further includes a memory 14, the memory 14 is respectively connected to the temperature acquisition unit 111, the status monitor 112 and the controller 12, wherein the memory 14 is used for storing the parameter information acquired by the information acquisition unit 11.

The memory 14 may operate by storing or reading various types of data according to the addresses of the memory cells. Optionally, the type of the memory 14 may be various, for example, the type of the memory 14 may include a random access memory, a read only memory, a programmable read only memory, and the invention is not limited thereto.

The memory 14 may be configured to store parameter information acquired by the information acquisition unit 11 in real time, specifically, the memory 14 may be configured to store the temperature information acquired by the temperature acquisition unit 111 and the operating state of the IO controller 22 acquired by the state monitor 112 in real time, so that the controller 12 may acquire the chip power consumption state in real time, and may also be configured to store instructions required by normal operation of the controller 12, for example, the required instructions may include a start instruction, a data operation instruction, a state judgment instruction, a first adjustment unit 131 instruction, a second adjustment unit 132 instruction, an interrupt processing instruction, and the like.

Optionally, the memory 14 may also be connected to the processor 21. The controller 12 may share data stored in the memory 14 with the processor 21 in real time. Specifically, the processor 21 may perform information query and state sharing with the controller 12 in real time, confirm the temperature information acquired by the temperature acquisition unit 111 and the operating state of the IO controller 22 acquired by the state monitor 112, perform information feedback, authorization processing, and the like, and perform data backup on data stored in the memory 14, thereby further improving the accuracy and reliability of the power consumption management circuit 10.

The chip 1 provided by the embodiment of the invention comprises: a processor 21, an IO controller 22, and any one of the power consumption management circuits 10 shown in fig. 1-5; the power consumption management circuit 10 is connected to the processor 21 and the IO controller 22, respectively.

Alternatively, the chip 1 is an SOC chip, which is a dedicated integrated circuit that integrates the microprocessor 21, the analog IP core, the digital IP core, and the memory 14 (or an off-chip memory control interface) into a single chip, and the SOC chip may be a standard product customized for a customer or for a specific application.

Next, the operation of the SOC chip 1 will be described with reference to fig. 6 to 7.

Fig. 6 is a schematic diagram of a work flow of a power consumption management circuit of the SOC chip 1 according to an embodiment of the present invention. Referring to figure 6 of the drawings, in which,

in an actual application process, the temperature collecting unit 111 may collect temperature information of the SOC chip 1 in real time, store the collected temperature information in the first adjusting unit 131, and the controller 12 may obtain the temperature information from the first adjusting unit 131 in real time and determine whether to generate the first control instruction according to the temperature information.

When the temperature information is less than the preset threshold, the controller 12 does not generate the first control instruction. When the collected temperature information is greater than or equal to the preset threshold, the controller 12 may send an authorization request message to the processor 21 of the SOC chip 1, the processor 21 may generate an authorization response message according to the authorization request message and send the authorization response message to the controller 12, and the controller 12 may receive the authorization response message sent by the processor 21 and generate a first control instruction according to the authorization response message and the temperature information. After that, the controller 12 sends a first control instruction to the first adjusting unit 131.

After receiving the first control instruction sent by the controller 12, the first adjusting unit 131 performs frequency reduction processing on the clock frequencies of the processor 21 and the IO controller 22 according to the first control instruction and a first preset step length; further, after the clock frequency of the preset component 20 meets the preset condition, the voltage amplitude of the preset component 20 is subjected to voltage reduction processing according to the first control instruction and the second preset step length.

Fig. 7 is a schematic diagram of another operation flow of a power consumption management circuit of a chip according to an embodiment of the present invention.

In an actual application process, the status monitor 112 may collect status information of the IO controller 22, and send the status information of the IO controller 22 to the controller 12, and after receiving the status information, the controller 12 determines whether to generate a control instruction according to the status information.

When the state of the IO controller 22 is the idle state of the IO controller 22, the controller 12 may send an authorization request message to the processor 21 of the chip, the processor 21 may generate an authorization response message according to the authorization request message and send the authorization response message to the controller 12, and the controller 12 may receive the authorization response message sent by the processor 21 and generate a second control instruction according to the authorization response message and the state information.

After receiving the second control instruction sent by the controller 12, the second adjusting unit 132 turns off the clock unit and/or the power supply unit of the IO controller 22 according to the second control instruction, thereby reducing the power consumption of the chip and achieving the purpose of power consumption management.

The controller 12 may query the states of the processor 21 and the IO controller 22 in real time, confirm that the power consumption of the processor 21 and the IO controller 22 is within a preset range, and store the current working states of the processor 21 and the IO controller 22; optionally, the controller 12 may perform data backup for the real-time collected data and the circuit configuration information. Thereafter, the controller 12 may send a release adjustment instruction to the processor 21, and after the processor 21 receives the release adjustment request instruction, may send a release adjustment response instruction to the controller 12. Then, the power management circuit 10 can perform data acquisition and status monitoring of the chip in real time.

On the basis of the work flows of the power management circuit 10 of the SOC chip shown in fig. 6 to fig. 7, further, the power management circuit 10 of the SOC chip may further increase the power consumption of the SOC chip, that is, the power management circuit 10 may further cause the processor 21 to recover the processing performance and/or the IO controller 22 to exit the low power consumption mode. The specific implementation mode is as follows:

optionally, when monitoring that the SOC chip needs to improve the power consumption performance of the processor 21, the controller 12 may send a first unit scheduling authorization request instruction to the processor 21, after the processor 21 receives the first unit scheduling authorization request instruction, the controller 12 may generate a first unit scheduling authorization response instruction according to the first unit scheduling authorization request instruction, and send the first unit scheduling authorization response instruction to the controller 12, the controller 12 generates a third control instruction according to the first unit scheduling authorization response instruction, and sends the third control instruction to the first adjusting unit 131, where the third control instruction is used to increase the voltage amplitude of the processor 21 in the preset unit 20. After receiving the third control instruction sent by the controller 12, the first adjusting unit 131 performs boosting processing on the voltage amplitude of the processor 21 in the preset component 20 according to the third control instruction and the third preset step length. Optionally, after the voltage amplitude of the processor 21 in the preset component 20 meets the preset condition, the clock frequency of the preset component 20 is subjected to frequency up processing according to a third control instruction and a fourth preset step length.

Optionally, when it is monitored that the IO controller 22 needs to exit the low power consumption mode, the controller 12 may send a second unit scheduling authorization request instruction to the processor 21, after the processor 21 receives the second unit scheduling authorization request instruction, the second unit scheduling authorization response instruction may be generated according to the second unit scheduling authorization request instruction, and the second unit scheduling authorization response instruction is sent to the controller 12, the controller 12 generates a fourth control instruction according to the second unit scheduling authorization response instruction, and sends the fourth control instruction to the second adjusting unit 132, where the fourth control instruction is used to recover the power supply unit and the clock unit of the IO controller 22. After receiving the fourth control instruction sent by the controller 12, the second adjusting unit 132 turns on the power unit and/or the clock unit of the IO controller 22 according to the fourth control instruction, and the operating state of the IO controller 22 is recovered to the normal state.

Optionally, the controller 12 may query the states of the processor 21 and the IO controller 22 in real time, confirm that the power consumptions of the processor 21 and the IO controller 22 are within the preset range, and store the current working states of the processor 21 and the IO controller 22.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the embodiments of the present invention.