阅读说明：本技术 多线路时偏校正方法和系统 (Multi-line time offset correction method and system ) 是由 罗杰·乌尔里克 阿明·塔亚丽 阿里·霍马提 理查德·辛普森 于 2019-01-28 设计创作，主要内容包括：所描述的方法和系统用于：经连续的多个信令间隔接收多个码字,每一个码字均以多个符号的形式经多线路总线的各线路被接收,所述多个符号由多个多输入比较器(MIC)接收,其中,每一个符号均由至少两个MIC接收；对于每一个码字,均生成所接收的符号的对应的一组线性组合；经所述连续的多个信令间隔,生成多个复合时偏测量信号,每一个复合时偏测量信号均基于一个或多个线性组合的样本；以及更新所述多线路总线的各线路的线路特定时偏值,其中,一个或多个线路特定时偏值根据与由至少两个不同MIC形成的线性组合相关联的复合时偏测量信号进行更新。(The described method and system are used for: receiving a plurality of codewords over a consecutive plurality of signaling intervals, each codeword being received over a respective line of a multi-line bus in the form of a plurality of symbols, the plurality of symbols being received by a plurality of multiple-input comparators (MICs), wherein each symbol is received by at least two MICs; for each codeword, generating a corresponding set of linear combinations of the received symbols; generating a plurality of composite time offset measurement signals over the successive plurality of signaling intervals, each composite time offset measurement signal being based on one or more linearly combined samples; and updating line-specific timing offset values for lines of the multi-line bus, wherein one or more line-specific timing offset values are updated according to a composite timing offset measurement signal associated with a linear combination formed by at least two different MICs.)

1. A method, comprising:

receiving a plurality of codewords over a consecutive plurality of signaling intervals, wherein each codeword is received over a respective line of a multi-line bus as a plurality of symbols, the plurality of symbols being received by a plurality of multi-input comparators, wherein each symbol is received by at least two multi-input comparators;

for each codeword, generating a corresponding set of linear combinations of received symbols by the plurality of multiple-input comparators;

Generating a plurality of composite time offset measurement signals over the consecutive plurality of signaling intervals, wherein each composite time offset measurement signal is based on one or more linearly combined samples; and

updating line-specific timing offset values for the lines of the multi-line bus, wherein one or more line-specific timing offset values are updated according to a composite timing offset measurement signal associated with a linear combination formed by at least two different multi-input comparators.

2. The method of claim 1, wherein at least one of the plurality of composite time offset measurement signals includes line specific time offset components for all lines connected to a given multiple-input comparator.

3. The method of claim 1, wherein at least one of the plurality of composite time offset measurement signals is generated from a linear combination generated by at least two multiple-input comparators.

4. The method of claim 1, wherein the line specific time offset value is updated in response to identification of a valid codeword sequence.

5. The method of claim 4, wherein updating the line-specific time offset values for the lines of the multi-line bus comprises: updating a line associated with the valid codeword sequence.

6. The method of claim 1, wherein the line-specific time offset value for a given line is updated in response to a subset of the composite time offset measurement signals generated over the consecutive plurality of signaling intervals exceeding an action threshold.

7. The method of claim 1, wherein each linear combination is performed by a respective multi-input comparator among the plurality of multi-input comparators, the respective multi-input comparator implementing a linear combination defined by a respective subchannel vector of a plurality of mutually orthogonal subchannel vectors.

8. The method of claim 1, wherein updating the line-specific timing offset value for a given line comprises: adjusting a capacitance associated with the given line.

9. The method of claim 8, wherein adjusting the capacitance comprises: controlling a switched capacitor network connected to the given line.

10. The method of claim 1, wherein the one or more linearly combined samples are generated compared to a preset offset voltage, and wherein the composite time offset measurement signal represents an early-late indication signal.

11. An apparatus, comprising:

A plurality of multi-input comparators to receive a plurality of codewords over a consecutive plurality of signaling intervals, wherein each codeword is received as a plurality of symbols by the plurality of multi-input comparators, each multi-input comparator to generate a respective linear combination for each received codeword;

a time offset correction circuit for generating a plurality of composite time offset measurement signals, wherein each composite time offset measurement signal is formed from one or more linear combinations generated within a single signaling interval of the consecutive plurality of signaling intervals; and

a plurality of line-specific delay elements for storing line-specific delay values, wherein each line-specific delay value is coupled to a single line of a multi-line bus, the plurality of line-specific delay elements further for storing line-specific delay values associated with the single line, wherein one or more of the line-specific delay elements are updated with a composite timing offset measurement signal associated with a linear combination formed by at least two multi-input comparators in the consecutive plurality of signaling intervals.

12. The apparatus of claim 11, wherein at least one of the plurality of composite time offset measurement signals includes a line-specific time offset component for all lines connected to a given multiple-input comparator.

13. The apparatus of claim 11, wherein at least one of the plurality of composite time offset measurement signals is generated from a linear combination generated by at least two multiple-input comparators.

14. The apparatus of claim 11, further comprising code sequence detection circuitry for identifying valid codeword sequences, wherein the plurality of line-specific delay elements are updated in response to the identification of the valid codeword sequences.

15. The apparatus of claim 14, wherein the code sequence detection circuit is further for determining a subset of lines associated with the valid codeword sequence.

16. The apparatus of claim 11, wherein the line-specific time offset value for a given line is updated in response to a subset of the composite time offset measurement signals generated over the consecutive plurality of signaling intervals exceeding an action threshold.

17. The apparatus of claim 11, wherein each multi-input comparator is operative to implement a respective linear combination defined by a respective subchannel vector of the plurality of mutually orthogonal subchannel vectors.

18. The apparatus of claim 11, wherein the line-specific delay element is to adjust a line-specific delay value for a given line by adjusting a capacitance associated with the given line.

19. The apparatus of claim 18, wherein the line specific delay element comprises a switched capacitor network connected with the given line, wherein the switched capacitor network is to control the capacitance associated with the given line.

20. The apparatus of claim 11, wherein the one or more linear combinations are compared to a preset offset voltage, and the composite time offset measurement signal represents an early-late indication signal.

Technical Field

Embodiments of the present invention relate generally to communication system circuitry and, more particularly, to measuring and reducing differential signal arrival times of received communication signals transmitted via a high-speed multi-wire interface for inter-chip communication.

Background

In modern digital systems, digital information must be processed efficiently and reliably. In this context, digital information is understood to be information contained within discrete values (i.e., non-continuous values). Digital information may be represented not only by bits and bit sets, but also by numbers within a limited set.

To increase the overall bandwidth, most inter-chip or inter-device communication systems employ multiple lines for communication. Each or each pair of these lines may be referred to as a channel or link, and the multiple channels make up a communication bus between the electronic devices. At the physical circuit level, buses within an inter-chip communication system are typically made up of encapsulated electrical conductors between the chip and the motherboard, on a Printed Circuit Board (PCB), or within inter-PCB cables and connectors. Furthermore, in high frequency applications, microstrip or strip PCB lines may also be employed.

Common bus line signaling methods include single-ended signaling and differential signaling, which are referred to herein as non-return-to-zero (NRZ) signaling. In applications requiring high-speed communication, these methods may be further optimized in terms of power consumption and pin utilization, particularly in high-speed communication. Recently proposed vector signaling approaches can achieve more optimal trade-offs in power consumption, pin utilization, and noise robustness of inter-chip communication systems. Such vector signaling systems convert the digital information of the transmitter into a different representation space in the form of vector codewords, and select different vector codewords according to the characteristics of the transmission channel and the design constraints of the communication system to make a better trade-off between power consumption, pin utilization, and speed. This process is referred to as "encoding" in this application. The encoded codewords are transmitted from the transmitter to one or more receivers in the form of a set of signals, and these signals are typically transmitted in a substantially parallel fashion over a plurality of lines or communication channels. The receiver inverts the received signal corresponding to the codeword into the original digital information representation space. This process is referred to as "decoding" in this application.

Regardless of the encoding method employed, the signals received by the receiving device must be sampled at intervals (or otherwise have their signal values recorded), and the sampling intervals must be such that the sampled values represent the original transmitted values in an optimal manner, regardless of the delay, interference and noise conditions of the transmission channel. The timing of this sampling (or slicing) operation is controlled by a corresponding clock-data alignment (CDA) timing system and the appropriate sampling time is determined by the system. When a group of signals is transmitted in a substantially parallel manner over a plurality of lines or communication channels, propagation delay fluctuations occurring in those lines or channels may cause the reception times of the elements (i.e., codewords) that make up the group of signals to differ from one another. When such "time offsets" are not corrected, they may cause the received codeword to lose internal correlation, and thus be difficult to decode.

Disclosure of Invention

In order to reliably detect data values transmitted via a communication system, the receiver needs to accurately measure the amplitude of the received signal values at carefully selected points in time. For the vector signaling code transmitted basically in parallel, the time selection consists of the following two links: accurately sampling each codeword received from each line or communication channel; the entire received codeword can be accurately interpreted no matter what time differences exist between the constituent symbols of the entire received codeword at the time of reception.

The propagation time difference within a codeword of a vector signaling code may be caused by a transmission path length or propagation speed difference and may be either constant or time varying. The identification and correction of this time difference of arrival, i.e., the "time offset", can increase the time window that allows correct reception, thereby improving received signal quality. Therefore, whether the receiver can accurately measure the time offset is crucial to the subsequent time offset correction. An example of time offset correction is the introduction of a variable time delay in each line or symbol data path prior to decoding of a codeword.

The described method and system are used for: receiving a plurality of codewords over a consecutive plurality of signaling intervals, each codeword being received over a respective line of a multi-line bus in the form of a plurality of symbols, the plurality of symbols being received by a plurality of multiple-input comparators (MICs), wherein each symbol is received by at least two MICs; for each codeword, generating a corresponding set of linear combinations of received symbols by the plurality of multiple-input comparators; generating a plurality of composite time offset measurement signals over the consecutive plurality of signaling intervals, each composite time offset measurement signal being based on one or more linearly combined samples; and updating line specific timing offset values for lines of the multi-line bus, wherein one or more line specific timing offset values are updated according to a composite timing offset measurement signal associated with a linear combination formed by at least two different MICs.

Drawings

Fig. 1 shows a system in which a transmitter 110 transmits information to a receiver 130 via a channel 120 comprising a multi-wire bus having a plurality of wires 125.

Fig. 2 shows a receiver implementation for an ENRZ code that uses a receive clock derived from received data transitions.

Fig. 3 illustrates one embodiment of a clock recovery subsystem used by the receiver of fig. 2.

Fig. 4 is a block diagram of a time offset detection system according to some embodiments.

Fig. 5 illustrates one embodiment of an adjustable delay element for a line in a multi-line bus used in the receiver of fig. 2.

Fig. 6 is a block diagram of an example sampler that may be used to provide data decision results and early-late indication information according to some embodiments.

Fig. 7 is a block diagram of another sampler that may be used to provide data decision results and early-late indication information according to some embodiments.

FIG. 8 is a block diagram of a code sequence detection circuit according to some embodiments.

FIG. 9 is a block diagram of logic circuitry for generating a line delay adjustment enable signal according to some embodiments.

Fig. 10 is a block diagram of a circuit that combines line delays according to some embodiments.

Fig. 11 is a receiver eye diagram sampled at the center of the eye diagram.

Fig. 12 is a state diagram showing the relationship between specific code transitions and line transitions.

FIG. 13 is a block diagram of a method according to some embodiments.

FIG. 14 is a block diagram of a method according to some embodiments.

Detailed Description

As described in Cronie 1, vector signaling codes may be used to form very high bandwidth data communication links between two integrated circuit devices within a system, for example. Wherein the plurality of data communication channels collectively transmit the codewords of the vector signaling code by transmitting respective symbols of the vector signaling code, respectively. Depending on the particular vector signaling code used, the number of channels making up a communication link may be as few as two, as many as eight or more than eight. Furthermore, each symbol (e.g., each symbol transmitted in any single communication channel) may use multiple (typically three or more) signal levels.

The embodiments described herein may also be applied to any communication or storage method that requires the generation of consistent overall results through the mutual coordination of multiple channels or channel elements.

Input sampling circuit

Conventional practice for high speed integrated circuit receivers involves terminating each data line within the sampling device (the line has previously undergone all relevant front end processing such as amplification and frequency equalization). Wherein the sampling device simultaneously performs the measurement under the constraint conditions of two dimensions of time and amplitude. In an exemplary embodiment, the sampling means is comprised of a sample and hold circuit for constraining the measurement time interval and a downstream threshold detector or digital comparator for determining whether the signal within the measurement time interval is above or below a reference value (or, in some embodiments, within upper and lower limits set by the reference value). In another embodiment, the sampling device may be similar to an edge-triggered flip-flop, which samples the state of the input signal upon a transition of the clock signal. In the following, the above-mentioned input measurement function of the receiver is indicated by the term "sampling means" or more simply "sampler", rather than by the equivalent "slicer" used synonymously in the art but with less intuitive meaning. The above two terms, when used, imply that the measurements are performed under constraints in both time and amplitude dimensions.

The schematic receive "eye diagrams" shown in fig. 11 show input signal values that can and cannot, respectively, produce accurate and reliable detection results (i.e., within the upper and lower allowable limits of the sampler time and amplitude measurement windows) from the above-described measurements.

The sampling measurement employs a Clock Data Alignment (CDA) circuit that extracts time information from the data line itself or a dedicated clock input signal and uses the extracted information to generate a clock signal that controls the time interval used by the data line sampling device. In practical applications, the clock extraction operation may be implemented by well-known circuits such as a phase-locked loop (PLL) or a delay-locked loop (DLL), wherein the circuit may also generate a high-frequency internal clock, multiple clock phases, etc. during its operation to support the operation of the receiver. Typically, the CDA is arranged to sample when the signal to be sampled is in a steady state, i.e. within a so-called "eye-centered" time interval denoted a and D in fig. 11, so that the sampling clock is "aligned" with the data to be sampled, thereby achieving an optimization of the quality and accuracy of the sampling results.

System environment

FIG. 1 illustrates an example system according to some embodiments. As shown, the system includes: a transmitter 110 receiving the source data S₀～S ₂100 and Clk 105; and an encoder 112 that encodes the information for transmission by the line driver 118 in a channel 120 comprising a multi-line bus having a plurality of lines 125. The system of fig. 1 further comprises a receiver 130 comprising a detector 132 and, in some embodiments, a decoder 138 for generating the received data R on demand₀～R ₂140 and a receive clock Rclk 145.

For purposes of illustration and not limitation, the following examples assume a communication system environment having a transmitting integrated circuit device and a receiving integrated circuit device connected to each other by four lines of substantially the same path length and having the same transmission line characteristics, a signaling rate of 25 Gb/sec/line, and a corresponding unit transmission time interval of 40 picoseconds. Wherein the Hadamard 4 x 4 vector signalling code in Cronie 1, also referred to as enhanced nrz (enrz) code in Fox 1, is used, three data values are transmitted on four lines (each carried by one sub-channel of the vector signalling code as described below), and the receive clock is derived from transitions of received data values. Other embodiments may include a transmitting integrated circuit device and a receiving integrated circuit device connected to each other via six lines of substantially the same path length and having the same transmission line characteristics, with a signaling rate of 25 Gb/sec/line and a corresponding unit transmission time interval of 40 picoseconds. Wherein five data values are transmitted over six lines (each carried by one subchannel of the vector signaling code, as described below) using a transwing vector signaling code (also known as the 5b6w code or the chordal nrz (cnrz) code) in Shokrollahi I, and the receive clock is derived from transitions of the received data values.

In order for the receiver to achieve a sufficiently high signal quality, it is also assumed that known methods of pre-enhancing transmission performance, such as finite impulse response filtering and continuous time linear equalization at the receiver, Decision Feedback Equalization (DFE), etc., are employed.

The communication channel may, for example, contain a time offset that may be caused by differences in the way the printed circuit board is constructed or the way the traces are routed, but for descriptive purposes the size of such a time offset is assumed to be less than one unit time interval. The overall problem to be solved by each time offset correction embodiment is how to achieve the maximum horizontal eye opening for an already partially open eye pattern in the system. However, the present invention is not limited to this, and other embodiments with larger channel time offset can achieve "opening" of the eye diagram through the training sequence and training method described in Hormati 2, while other embodiments with much larger time offset than the above time offset can use the above time offset correction method and other known time offset correction methods in combination in corresponding environments.

Figure 2 illustrates an exemplary embodiment of a vector signaling code communication receiver. In this block diagram, the four data line inputs W0-W3 from the multi-line bus are each processed by a delay element 200, and the resulting signals are then passed to a continuous-time linear equalizer (CTLE)210 for selective amplification and/or frequency compensation processing. In addition, CTLE circuits are also commonly used to provide additional high frequency gain (also referred to as high frequency "peaking") to compensate for frequency dependent transmission medium losses. The resulting processed line signals are provided to a Multiple Input Comparator (MIC)220 for decoding the sub-channels of the vector signaling codes MIC 0-MIC 2. These subchannel output signals are sampled 140 by sampling circuitry 230 at intervals determined by clock recovery (CDA) subsystem 300 to produce subchannel 1-subchannel 3 data outputs. As shown in fig. 2, the receiver may operate on multiple phases and may include a multiplexer 240 for outputting the sampled data for each phase in turn. In an alternative, the above-described processing is performed by a delay element 200 disposed downstream of the CTLE 210 and upstream of the MIC 220.

In some embodiments, an apparatus comprises: a plurality of multiple-input comparators (MICs) 220 for receiving a plurality of codewords for a plurality of signaling time intervals, each received codeword of the plurality of MICs being received in the form of a plurality of symbols, each MIC for generating a respective linear combination for each received codeword; a time offset correction circuit (an example of which is shown in fig. 4) for generating a plurality of composite time offset measurement signals, each formed from one or more linear combinations generated from a single one of the plurality of signalling time intervals, the linear combinations being generated by the MICs 220 forming a combination of received codeword symbols; and a plurality of line-specific delay elements 200 for storing line-specific delay values, each connected to a single line of the multi-line bus, the plurality of line-specific delay elements 200 further for storing line-specific delay values associated with the single line, wherein one or more line-specific delay elements are updated by a composite timing offset measurement signal associated with a linear combination formed by at least two MICs in the consecutive plurality of signaling time intervals.

In some embodiments, at least one of the plurality of composite time offset measurement signals comprises a line specific time offset component from all lines connected to a given MIC. In some embodiments, at least one of the plurality of composite time offset measurement signals is generated from a linear combination generated by at least two MICs.

In some embodiments, the apparatus further comprises a code sequence detection circuit 440 for determining a valid codeword sequence, wherein the plurality of line-specific delay elements are updated in response to the determination of the valid codeword sequence. In some such embodiments, the code sequence detection circuitry is also for determining a subset of lines associated with the valid codeword sequence.

In some embodiments, the line-specific time offset value for a given line is updated in response to a subset of the composite time offset measurement signals generated over the successive plurality of signaling time intervals exceeding an action threshold.

In some embodiments, each MIC is configured to perform a respective linear combining operation determined by a respective subchannel vector of a plurality of mutually orthogonal subchannel vectors. Linear combinations based on the subchannel vectors are, for example, see the following formulas 2 to 4.

In some embodiments, the line-specific delay element is configured to adjust a line-specific delay value for a given line by adjusting a capacitance associated with the given line. In some such embodiments, the line-specific delay element comprises a switched capacitor network connected to the given line.

In some embodiments, the one or more linearly combined samples are compared to a preset offset voltage, and the composite time offset measurement signal represents an early-late indication signal.

In some embodiments, some or all of the subchannel outputs are also provided with additional samplers to facilitate analysis and/or management of timing. As an example, such additional samplers may be triggered by the early or late arrival of the clock to detect signal transitions to optimize the operation of the CDA. As another example, such additional samplers may be provided with adjustable offset slice voltages for facilitating vertical eye opening measurements. As described in Hormati1 and shown in FIG. 6, the offset slice voltage may further contain DFE correction factors for providing data information and clock edge information simultaneously. Fig. 6 includes at least one speculative DFE processing stage 650 supported by two data samplers that perform time sampling operations simultaneously at two different magnitude thresholds. As shown, the data samplers each include comparators 620 that generate comparator outputs that slice signals received from CTLE 210 and sample the comparator outputs according to a sampling clock. Wherein the output of one of the comparators is selected as the data value D and the output of the other comparator is selected as the error signal in the form of the early-late indication information, depending on the most recent data decision. This signal is referred to in this application as the signal time-bias signature. Using the past data values 640, the pattern detection module 670 can identify the pattern containing the transition and then determine the line involved in the corresponding transition using the time offset measurement signal (shown as early-late indication information E/L), and then increment or decrement the counter for the corresponding particular line. The selection of the data signal and the early-late time offset measurement signal may be performed by multiplexers 630 and 660. It is further described in Tajalli 1 how to combine clock edge information from two or more sub-channels with each other and how to filter out from such combined results time offset measurement information from sub-channels where no transition occurs to provide better feedback to the CDA subsystem in terms of timing.

Fig. 7 illustrates another sampling mechanism that may be used in some embodiments. As shown, the output of the MIC 0610 is processed by CTLE 210 as described above, while the output of CTLE 210 is sampled by data sampler 702 and transition sampler 704. In such embodiments, the data signals from CTLE 210 may be down-sampled at double rate. In at least one embodiment, the data may be sampled twice according to the sampling clocks ck _000 and ck _180 provided by the sampling clock module 706. In some embodiments, the early-late indication information in the form of a composite time offset measurement signal may be obtained using clocks 180 degrees out of phase, where one clock samples the "eye center" (see fig. 11) and the other clock samples the transition region. Alternatively, the data may be sent twice while using a full speed clock, effectively halving the data rate. In such embodiments, only one sampler may be used and the output of that sampler is alternately switched between data sampling operations and edge sampling operations. In such embodiments, full-speed data transmission may be turned on or resumed after the half-speed time offset training period is completed. Subsequent measurements and adjustments can then be made using the full speed methods and circuits described herein.

The difference between the arrival times of the respective line signals (i.e., "time offset") can delay or interfere with the correct detection time of the vector signaling code. The time offset may be caused by differences in the length or propagation velocity of the transmission path elements and may be either constant or time varying. Therefore, accurate measurement of the time offset by the receiver facilitates subsequent time offset correction. An example of time offset correction is the introduction of a variable delay in the symbol data path prior to decoding of the codeword. In another example, the time offset measurement may also be fed back to the transmitter, and the transmitter may implement line-specific time adjustments by adjusting the time of the codeword symbols provided to each line of the multi-line bus, so that the signal received by the receiver is a signal that has been previously time offset compensated.

Time offset adjustment and compensation

The elimination of the time offset involves progressively offsetting the signals of the various lines in time to achieve compensation for the arrival time differences. Some time offset measurement methods, such as those described in Hormati II, also provide interactive line delay adjustment during testing and analysis.

At the receiver, the line delay implementation may include prior art methods in the analog or digital domain employing variable delay elements, time-adjustable sample-and-hold elements, adjustable FIFO buffers, and the like.

Hormati II describes a method of inserting a low insertion loss resistive/capacitive filtering process into each line signal received, the resistive/capacitive filter implementing this process being operable to minimise the effect on the signal amplitude whilst introducing a small adjustable amount of delay. One such delay element 200 embodiment is shown in fig. 5. Although the controllable delay circuit is shown for a single line, each line of the multi-line bus may be provided with a similar circuit 200 for implementing an adjustable signal time offset. Wherein, the transistors 501, 502, 503 can be respectively controlled by the time bias to input B₀，B₁，B₂Conducting to raise the ground capacitance of the line input node by the capacitor C₀，C₁，C₂The determined amount. The amount of boost in the node capacitance works in conjunction with the source and termination impedances of the input transmission line to introduce a greater amount of delay in the line signal. In an alternative embodiment, the delay element 200 is located elsewhere in the line signal path, such as but not limited to the output of each CTLE processing stage rather than the line input of the receiver.

In one embodiment, when C₀、C₁、C₂With values of 5fF, 10fF, 20fF, respectively, a binary incrementing of the capacitance by a binary time-offset control codeword can be achieved, The maximum total capacitance boost is 35 femtofarads (femtofarads), which corresponds to a delay increase of about 5 picoseconds. In another embodiment, capacitors having the same capacitance value may also be used, where the corresponding control word is a thermometer code word rather than a binary code word. As a side effect of the capacitance increase, the high frequency response performance will be slightly degraded. In the above embodiment, when the amount of delay introduced is 5 picoseconds at maximum, the return loss (also commonly referred to as S) at 12.5GHz will be made₁₁) A 1.5dB drop in performance occurs.

In another embodiment for correcting larger time offsets, each line signal is sampled at a time offset correction instant at which each line signal remains stable with an analog track-and-hold circuit or an analog sample-and-hold circuit as delay element 200, and the sampling clock used in the sampling operation 140 of the resulting MIC subchannel output is delayed by clock recovery circuit 150 to at least the latest instant among the time offset correction instants. To increase delay time or reduce sampled signal artifacts, some embodiments may place a series of such post-sampling delay elements on each line.

As described in Ulrich 1, the time offset can also be eliminated by adjusting the transmission time of each line. In such a manner, the receiver sends information such as the relative reception time of each line it collects to the transmitter, thereby enabling the transmitter to adjust its line transmission time accordingly. In some embodiments, the communication line mapping relationship to be identified and corrected, including transpose and reverse order, is allowed to be adjusted by sending other information. This communication operation may be either receiver driven or distributed by another command/control processor. In each of these two cases, communication may be via a return data channel, an out-of-band command/control channel, or other communication interface, using protocols and methods known in the art outside the scope hereof.

Receiver data detection

Efficient detection of vector signaling codes can be achieved by linearly combining sets of input signals with multiple input comparators or Mixers (MIC), as described in Holden I. Wherein it is sufficient to detect all ENRZ code words by operating on various permutations and combinations of the same set of four input signals with three such multi-input comparator circuits. That is, if a multiple input comparator is assumed that performs the following operations:

r ═ J + L) - (K + M) (formula 1)

Wherein J, K, L, M is a variable representing the four input signal values, then as a non-limiting example, three linear combination result values R are generated according to the following equations representing the sub-channel vectors of the Hadamard H4 matrix₀、R₁、R₂The input signal permutation and combination form is as follows:

R₀(W + Y) - (X + Z) (formula 2)

R₁Becoming (Y + Z) - (W + X) (formula 3)

R₂Becoming (Y + X) - (Z + W) (formula 4)

The above linear combination is sufficient to unambiguously represent each ENRZ code word represented by the received signal input value W, X, Y, Z. Wherein the result value R₀、R₁、R₂Commonly referred to as ENRZ subchannels, each of which is modulated with one bit of data in this example.

By reconstructing equations 1-4 such that they each represent the sum of two differences, a functionally equivalent corresponding MIC configuration can be obtained, as described in Ulrich II.

Various methods and systems described herein obtain early-late indication information and time offset measurements from a total data signal that is a signal formed by linearly combining the data signals of each line of a multi-line bus. The total data signal is referred to herein as a sub-channel data signal and is formed by a multiple input comparator circuit (MIC)220, 610. Such MICs achieve the above linear combination by combining the input signals according to decoder coefficients or decoder weight values represented by the rows of an orthogonal matrix, such as a hadamard matrix or other orthogonal matrix described herein. It follows that each row of the orthogonal matrix defines a symbol of the subchannel codeword, which symbols are then summed to obtain an orthogonal codeword, each symbol of which is the sum of the corresponding symbols of the subchannel codeword. Depending on the code used (ENRZ code, CNRZ code or other orthogonal code with multiple orthogonal subchannels), each subchannel data signal may use either all lines (as in the case of ENRZ codes) or a subset of lines formed by a portion of the lines. In some embodiments, some of the sub-channel data signals may use all of the lines, while other sub-channel data signals use only a subset of the lines formed by some of the lines (as in the case of CNRZ codes).

In each MIC that implements subchannel decoding by combining the line signals, any signal time offset present in the line for a particular subchannel data signal of interest appears as a degree of time offset to the combined subchannel data signal itself. The degree to which a particular line time offset affects a given MIC subchannel output depends on several factors including at least the signal level transitions that occur on the corresponding line and the relative amplitude of the signal applied to that line (determined by the subchannel rows of the matrix, and therefore ultimately the structure of the MIC circuit). While the MIC is a linear combiner in the voltage domain, it acts as a phase interpolator when used to extract time information. The time offset measurement output by a MIC subchannel is typically a determination of "too early" or "too late" relative to the clock received from the CDR subsystem, and may then be converted into a composite time offset measurement signal corresponding to the line involved in the transition, and may even be distributed among the lines according to the relative contribution of each line, where the factors considered in determining the relative contribution of the lines are the level transitions of each line and the corresponding subchannel decoder coefficients of the MIC. The results of the plurality of time offset indicator signals may then be accumulated to generate a time offset compensation value for each particular line. In some embodiments, the line-specific time offset compensation value may be generated by determining whether the cumulative composite time offset measurement signal exceeds a threshold, or based on a particular threshold that is exceeded for a given length of time.

Since the time offset measurement is derived from the amount of signal level change of a particular line and the line-specific MIC coefficient, either a training pattern containing known signal level transition types in known lines needs to be sent, or a codeword detection circuit for determining the signal level transition type and the corresponding line to which the identified codeword transition relates can be provided in the receiver. The mode detection circuitry 670 may be used, among other things, to determine the particular transition type and the identified line to which the corresponding transition relates. Thus, the pattern detection circuit 670 is also capable of determining the magnitude of a signal level transition on a particular line (based on the identified code type), and the increment of the counter can be adjusted accordingly to reflect the relative contribution of the corresponding line to the amount of time offset.

In some embodiments, a method comprises: generating a total data signal by linearly combining line signals received in parallel from lines of a multi-line bus during first and second signalling time intervals, wherein at least part of the line signals have signal level transitions during the first and second signalling time intervals; measuring a signal time offset of the total data signal; and generating line specific time offset compensation values, each of which is based on the signal time offset measurement. That is, if the signal time offset measurement is in the form of a "too early" indication, the counter of the line involved in the transition may be decremented, thereby reducing the time offset compensation value for the corresponding line; the counter may be incremented if the time offset measurement of the signal is in the form of an "too late" indication. In some embodiments, the time offset measurement corresponds to a composite time offset measurement representing an ensemble of combinations of respective line time offset components for each line involved in the transition. In some embodiments, a plurality of linearly combined measurements produced by two or more MICs may be combined with one another to form a composite time offset measurement signal containing line-specific time offset components for each line associated with the two or more MICs. Wherein the final count value may be used as the line-specific time offset compensation value, or the number of times the count value exceeds the threshold value may be used as the line-specific time offset compensation value. In some embodiments, the line-specific time offset compensation value may be used directly as a delay adjustment control signal by adjusting the capacitive load of the respective line at the receiver. In other embodiments, the time offset compensation values may be transmitted to the transmitter via a reverse channel, so that the transmitter can perform time offset pre-compensation. In some embodiments, the time offset compensation value may also be transmitted to the transmitter only when the time offset correction capability of the receiver reaches a limit. That is, when the capacitive load or other delay mechanism capability at the receiver is exhausted, the receiver may send the transmitter a time offset correction value for the particular line. Upon receiving the conditioned signal back from the transmitter, the receiver can compensate for this value, thereby shifting the line time back to the range that the receiver can compensate for. The receiver can send specific values of the time offset control signal for specific lines, or can send only up and down indication information indicating progressive correction amounts for specific lines.

For a physical multi-wire bus system with m MICs (MIC, i ═ 0, …, m-1), each MIC can be expressed as:

MICi＝{ai_j,r_i0, …, n-1 (formula 5)

Wherein n represents the number of lines, a_ijRepresenting the corresponding decoder coefficient, r_iA comparative reference level (normally set to zero for simplicity) is indicated. This expression can be converted into:

wherein VMIC represents MIC voltage domain operation for linear combination of input signals, a_ijTo represent real numbers of MIC coefficients, w_jIs a real number corresponding to the instantaneous signal value on each line. Wherein, relative to any reference time, if each input line has a specific time offset Δ t_w(j)Then the time offset of the MICi output signal s (i) can be calculated as:

wherein the signal level transition of line j is represented by Δ w_j＝w_j[ currently, the]-w_j[ conventional methods of]And, in some embodiments, -1<Δw_j<+1 denotes the signal w on line j_jIs normalized (if there is no transition, w is_j0). In addition, the voltage swing can also be normalized by the maximum voltage value. It can be seen that the time offset of the MIC output depends on the data pattern. That is, the time offset may be at max, depending on the input data pattern _(tj)And min_(tj)To change between. Since the time offset of each subchannel output depends on the specific data, even in an ideal system without any inter-symbol interference (ISI), the eye diagram may be max due to the presence of the time offset_(tj)-min_(tj)The amount of eye closure. The MIC defined by a linear encoding/decoding scheme such as NRZ or ENRZ does not have the eye closing phenomenon of which the degree changes with time deviation. However, some decoding schemes such as CNRZ suffer from a time bias due to their susceptibility to deterministic or random Common Mode (CM) noise, resulting in "closed-eye" MIC outputs.

Here, assuming that | tj | < < T (T denotes a data period, i.e., a signaling time interval, corresponding to one unit time interval), the signal value of each line at T < < T around the transition time can be approximately expressed as:

wj ═ bj (t + tj) (formula 8)

According to equations 8 and 6, the transition time of the subchannel output can be approximately represented by equation 7.

As can be seen from equation 7, each MIC acts as a phase interpolator in the time domain. That is, the transition time of the output of the MIC processing stage is the weighted interpolation result of the transition time of the input signal. Thus, if the multi-line receiver can be represented as [ a ]_ij,r_i]Then the crossing time of the MIC output can be expressed as [ a ]_ijbi_j]. If the matrix is an invertible matrix, the time offset of the receiver input can be accurately calculated. Conversely, if [ a ] _ijb_ij]And if the input offset is not reversible, the input offset cannot be calculated. In this case, e.g.Still to implement the time offset calculation, other algorithms must be used.

In some embodiments using turbo codes, the time-offset pattern for some transmitter embodiments is T ═ 0,0, T₁,t₁,t₂,t₂]The corresponding line is W ═ W0, …, W5]. This time-offset mode is due to the structure of the transmitter. Using equation 7, the time offset of the receiver subchannel output can be calculated as:

T_subch＝[(t₁+t₂)/3,t₁/2,0,t₁/2+t₂/2,t₂](formula 9)

From this equation, it can be seen that the time offset of the subchannel 5 output is the largest, while the time at which the subchannel 2 output transitions is the earliest. As shown in fig. 15, the calculation results of equation 9 are in close agreement with the experimental data. Thus, equation 9 can be used to calculate the line (t)₁And t₂) Time offset in between.

In one embodiment, a time offset compensation algorithm for a system using turbo codes may comprise:

(1) from the open-eye condition of sub-channel 4 (only line 4 and line 5 are involved), measuring a phase interpolation code (or other signal that can be used to measure the time offset between sub-channels) that can determine the intersection of sub-channels;

(2) similar measurements are made for other sub-channels;

(3) the corresponding time offset for each line is calculated according to equation 9.

In some embodiments, the measurement algorithm comprises: the zero crossing point of each received subchannel output is measured. The receiver includes five subchannels (five MICs). The output of each MIC is sampled by four slicers corresponding to the quarter-rate architecture of the receiver (i.e. each slicer runs at quarter-rate to take turns processing the full-speed total data signal for a given MIC). The measurement process of some embodiments is as follows:

(1) Generating a set of periodic data (e.g., 16 unit interval data, 8 of which are high and 8 of which are low) on one of the phases of the transmitter (i.e., assuming the transmitter has multiple phases);

(2) taking cross-point measurements of the 5 MIC outputs, wherein each output is sampled by 4 slicers, thus yielding 20 independent measurements;

(3) return to step 1 and transmit a new set of periodic data on another phase of the transmitter. This process is repeated until data is obtained for all four phases of the transmitter.

Assume that M0 is the measurement result obtained after the slicer of the receiver measures the periodic data sequence transmitted by the transmitter for subchannel 0. The received signal at the crossing point of the received MIC output can be measured by rotating the sampling clock with a phase interpolator consisting of four slicers connected to each MIC.

Wherein each column is a measurement of a different phase of the receive clock. For example, column 0 is four independent measurements from a subchannel 0 slicer, and the slicer is controlled by receive clock phase 000(0 degrees). At the same time, each row represents four different sets of data sent by the transmitter. For example, row 0 is transmitting periodic data generated by phase 000.

Further, wherein:

x: represents the error or time offset of the receive sampling clock;

y: representing the error or time offset of the transmit clock used to generate the output signal. For example, y0 represents a timing error of transmit clock phase 000.

z: representing the nonlinear effects originating from the Phase Interpolator (PI).

It can be seen that 16 measurements obtained at the output of the MIC corresponding to subchannel 0 can be used to calculate (or estimate) 12 independent parameters.

When all sub-channels are considered, then there are five sets of measurements for the five MICs, each set comprising 16 measurements, thus there are 80 independent measurements in total. Comparison of the measured values M0, M1, M2, M3, M4 facilitates time offset measurement between lines. In some embodiments, the following items may be extracted using a maximum likelihood method:

(a) time offset value between five lines

(b) Time offset value of phase time clock of receiving end

(c) Time offset value of clock between phases of transmitting terminal

(d) Four values representing the phase interpolator non-linearity. It should be noted that the value of the non-linearity of the phase interpolator can only be measured at a few data points.

ENRZ encoding: in some embodiments of the ENRZ scheme, | a for all values of i and j _ijAnd | ═ 0.25. In some embodiments, the respective circuits are configured to perform line time offset measurements by selecting a particular mode, while other embodiments employ a subset of transitions in an ENRZ transceiver, as described further below.

Relationship between lines and codes in ENRZ

From the above and the detection expressions 2-4, it is known that the measurement of the received sub-channel signal and the inverse mapping of this information to the variation of the received line signal are inherently difficult to achieve. Since each subchannel is associated with all four received line signals, there is currently no accepted mathematical method that can segment, parse or otherwise determine the individual line signal information.

Code	Line 0	Line 1	Line 2	Line 3	R0	R1	R2
								7	+1	-1/3	-1/3	-1/3	1	1	1
1	-1/3	+1	-1/3	-1/3	0	0	1
								2	-1/3	-1/3	+1	-1/3	0	1	0
4	-1/3	-1/3	-1/3	+1	1	0	0
								0	-1	+1/3	+1/3	+1/3	0	0	0
6	+1/3	-1	+1/3	+1/3	1	1	0
								5	+1/3	+1/3	-1	+1/3	1	0	0
3	+1/3	+1/3	+1/3	-1	0	1	1

TABLE 1

As shown in table 1, the line signal used to encode code 7, 1, 2, 4 uses one "+ 1" signal value and three "-1/3" signal values (ENRZ is an equalization vector signaling code, and the sum of all signal values for a given codeword is zero). Similarly, the line signal used to encode codes 0, 6, 5, 3 uses one "-1" signal value and three "+ 1/3" signal values. More importantly, a transition between any of the codes 7, 1, 2, 4 or 0, 6, 5, 3 only changes the signal on both lines. Thus, for example, for codes 7, 1, 2, 4, if a different code within the group is received after any one of the codes is received, the transition between the two codes must be accompanied by a change on two lines, and the two lines on which the change occurred can be determined from table 1. The same applies to two codes received one after the other from the set of 0, 6, 5, 3.

Such a well-defined two-wire transition must accompany the reception of a data "word" R₀，R₁，R₂The change in the two values. However, this rule is not sufficient by itself for determining the two lines on which a change has occurred, since, for example, although a transition between code 7 and code 1 or between code 0 and code 6 due to a change of line 0 and line 1 only causes R₀，R₁Change but only R₀，R₁The reason for the change may also be a transition between code 2 and code 4 or between code 3 and code 5 due to a change of line 2 and line 3. Therefore, it is necessary to use an algorithm or circuit to screen out the pairs of lines corresponding to the subchannel transitions that are capable of determining a particular set of code sequences. The particular line sequence and codeword values chosen in this example are for ease of description and are in no way limiting.

Determination of the time of a transition

As described above, the system environment of the present specification performs clock recovery of a receiver based on detected transitions of sub-channel data. To maximize the amount of information available to keep the clocks properly aligned, it is common practice to monitor all receiving sub-channels. Tajalli I describes a clock recovery system of this type in which phase error results are generated by individual phase detectors capable of sensing transitions occurring within the respective sub-channels, and then a total error signal for updating the phase of the clock PLL is generated by summing these phase error results. In one such embodiment, only the results of the sub-channels for which valid transitions occur within the target time interval are summed; in another embodiment, the addition is performed using only a simple binary (Bang-Bang) phase comparator, the transition filtering function described above is not provided, and any anomalous error results from subchannels where no transition occurs are simultaneously spread out over time. In addition, implementations known in the art that employ Baud rate (Baud) clock edge detection methods or double rate clock edge sampling methods may also be used.

Fig. 3 illustrates a clock recovery circuit 300 used in some embodiments. As shown in FIG. 3, the circuit includes a plurality of partial phase comparators 310, each of which receives the output of a respective subchannel. In such embodiments, each partial phase comparator outputs only a partial phase error result when a transition occurs for the corresponding subchannel. Each partial phase error signal is received by a summing circuit 320 to generate a composite phase error signal. The composite phase error signal is filtered by a loop filter 330, which may be a Low Pass Filter (LPF) that generates a low frequency error signal, and provided to a Voltage Controlled Oscillator (VCO) 340. The clock recovery circuit 300 may further include a frequency divider 350 that divides the received output of the VCO 340 and provides the resulting signal to a phase interpolator 360 for providing an interpolated signal to the phase comparator 310. As shown, the phase interpolator also receives a phase offset correction signal from clock/data phase control logic 370. The correction signal can be used to compensate for fluctuations that occur during processing by the system. The output of the VCO 340 may be used as a sampling clock in a multi-phase system, one of the phases of which is shown in fig. 4.

In the two-wire transition scenario of interest in the present application, the results of the two sub-channels change substantially simultaneously, except for the occurrence of random fluctuations in the circuitry. Thus, when such a transition occurs, two substantially identical phase error results are added to the total error signal. The algorithm described below achieves correction of line time bias by obtaining an overall "too early" or "too late" state of the total error signal.

Time offset correction algorithm

The input to the algorithm comprises the received data, i.e. the detected subchannel results R₀，R₁，R₂. For purposes of illustration, the data values are referred to herein as identifying "codes", i.e., the specific circuitry and resulting combinations described above in connection with Table 1. In which the information received in at least two successive unit time intervals, here called code (N) and code (N +1), carries a time offset detection or measurement in the form of a clock phase error corresponding to the time interval, either a value with positive or negative properties indicating the amount by which the received transition is earlier or later than the target clock time, or a simple binary positive or negative sign indicating only "too early/too late". Thus, when a transition occurs between one or more sub-channel detections within two subsequent receive unit time intervals, such transition will contain information for generating a composite time offset measurement signal corresponding to the total time offset of one or more lines undergoing a change in transmission state within the multi-line bus.

The information is obtained by any one of the following methods: continuously monitoring the received data stream (e.g., via a finite state machine); the data stream is effectively sampled statistically (e.g., by a software process running on a control or management processor that periodically requests and receives a received data sequence and corresponding clock phase error information, such sampling spanning at least two successive receive unit time intervals).

The output of the algorithm is a dynamic estimate of the relative arrival times of the four line signals, which can be used to adjust the line-specific timing offset values of the line signal delay elements on-the-fly or periodically, or to request or indicate similar time adjustments to be performed by the transmitter for each line. In one embodiment, the dynamic estimation result is used to adjust receiver line delay on the fly. In another embodiment, the dynamic estimation results are held in memory as a variable and adjustments are initiated when the absolute positive or negative value of the variable exceeds a preset threshold, thereby filtering small fluctuations.

Another embodiment of the algorithm, expressed in Verilog language, is shown in appendix I.

The "if" statements therein correspond exactly one-to-one to the transition states shown in the state diagram of fig. 12, wherein the successive codes 7 (front) and 1 (back) or 1 (front) and 7 (back) correspond to line 0 and line 1, as do codes 0 and 6.

Since it is not possible to determine which of the two lines on which the transition occurred, caused the composite time offset measurement signal to be "too early" or "too late" in time, the variables representing the time offset measurement values for both lines are updated in the same way. Thus, for example, if subsequent transitions corresponding to codes 0 and 5 also update line 0 and line 2 in the same direction, it is suggested that line 0, which is commonly referenced by both measurements, may be the source of the time error. Therefore, by processing several different sampling results with this algorithm, a reasonable estimation of the individual line time errors can be achieved. As described above, in at least one embodiment, by introducing an action threshold before the accumulated time error value causes a temporal change to actually occur, random time adjustments due to measurement artifacts can be reduced. In some such embodiments, the time adjustment for a given line is achieved by adjusting the preset step value in response to the cumulative condition of the time error values. Such a preset step value may be a change in capacitance associated with a timing delay representative of the action threshold, which may for example correspond to a change that occurs when the count value exceeds the threshold. In some embodiments, each line may be individually updated when the accumulated value of time error exceeds the action threshold. In an alternative embodiment, all routes may be updated according to their current corresponding route-specific delay values when the accumulated value of time errors for a single route exceeds the action threshold. In other embodiments, the line time employs an instantaneous adjustment scheme, with the assumption that even a small amount of adjustment is introduced in the opposite direction, no large error results, and that continuing adjustments in the same direction can actually achieve an optimization of the openness.

Fig. 4 is a block diagram of a receiver that may be used to perform the time offset detection algorithm described above. As shown in fig. 4, the receiver includes circuitry for receiving the signals in each line and generating a representative sub-channel output R therefrom as described above₀～R₂The MIC220 of the total data signal. The sampler provides a data output D for each subchannel by sampling 430 the output of the subchannel₀～D₂And including the early-late indication signal E/L of each sub-channel₀～E/L₂A composite time offset measurement signal. In some embodiments, sampler 430 may take the form of the sampler described above in fig. 6 or fig. 7. The receiver of fig. 4 includes a code sequence detection module 440 for detecting groups of sequentially received valid bits, each group representing the codes 0-7 described above. These sequences are shown in the state diagram of fig. 12. In some embodiments, code sequence detection module 440 may provide DFE functionality, for example, for use with sampler 430 in embodiments employing the sampler shown in fig. 6.

FIG. 8 is a block diagram of a code sequence detection module according to some embodiments. In some embodiments, the code sequence detection module may be implemented by D flip-flops 805 and 810, which are sampled by a delayed sampling clock 815 to create time for the buffering operation. The logic circuit 820 determines whether the detected code sequence is a valid sequence by analyzing the currently detected bits b 0-b 2 and the previously detected bits prev _ b 0-b 2. When the detected code sequence is a valid sequence, the bus line delay module 460 shown in fig. 4 will be provided with line delay adjustment enable signals w 0-w 3_ enable. As described above, in the H4 code implementation, any valid code sequence detected by the logic circuit 820 involves two lines. In such an embodiment, only two of the line delay adjust enable signals w 0-w 3_ enable are "1" and the remaining two are "0" (thus not causing a delay value update in the bus line delay module 460).

In the alternative, other sequences may be used on the basis of or in addition to the sequence involving only two lines. For example, the code sequence detection circuit 670 may identify a transition of each line that is only positive-negative inverted, but still maintains the original amplitude, such as a codeword transition from [ -1,1/3,1/3,1/3] to [1, -1/3, -1/3, -1/3], or a codeword transition from [ -1/3,1, -1/3, -1/3] to [1/3, -1,1/3,1/3], etc. The set of transitions comprises 8 sets of codeword sequences. In such transitions, the time offset value is updated accordingly by looking at the transition amplitude of the particular line. Specifically, for a codeword transition of [ -1,1/3,1/3,1/3] to [1, -1/3, -1/3, -1/3], the time offset monitor value or measurement of the MIC output may be weighted according to the following transition magnitude calculation: l (((line (code 1, i)) -line (code 2, i) × MIC (line (i)) | (in this case, i.e., [2,2/3,2/3,2/3 ]). it can be seen that the time offset of line W0 has three times the effect on the MIC output time offset monitor value as the other lines.

Fig. 9 is a block diagram of a logic circuit 820 according to some embodiments. FIG. 9 illustrates an example of a valid code sequence for transitioning from code "1" to code "7" of Table 1. This logic circuit may be implemented as an AND (AND) gate 905, wherein the output of the AND gate 905 is high when bits b0-b2 correspond to a code "1" to "001" AND the previous received bits prev _ b0-b2 correspond to a code "7" to "111". The control circuit 910 may analyze the outputs of all such detection logic gates and may output line delay adjustment enable signals w 0-w 3_ enable to the bus line delay module 460. The enable signal indicates which counter should be adjusted (either incremented or decremented depending on the signal time offset signature). In addition, the count decrements can be weighted in the manner described herein based on the relative amplitude of the line signal level transitions. In some embodiments, the control circuit 910 may employ control logic that implements table 2 below:

TABLE 2

The receiver of fig. 4 further comprises a matrix error combiner 450 for receiving early-late indicator signals E/L0-E/L2 from the plurality of sub-channels and providing them to the bus delay module 460 after generating the final early-late decision result for incrementing or decrementing the pre-stored delay values accordingly. As shown above and in Table 1, in some embodiments, there are only two subchannels R for any given valid code sequence₀～R₂The E/L signal generated by the changed, and therefore unchanged, sub-channel is a useless indication, so corresponding logic can be introduced to ignore the effect of such useless indication. Nevertheless, since both of the changed sub-channels provide early-late indication information indicating early or late, the combination of the two early-late indication information will override the early-late indication information of the sub-channel where no transition occurs, and therefore the final early-late indication information provided by the matrix error combiner 450 is valid even without the introduction of the logic.

FIG. 10 is an exemplary block diagram of a bus delay module 460 according to some embodiments. As shown, the bus delay module includes four modules 1005, 1010, 1015, 1020, one for each line of the multi-line bus. In some embodiments, each module corresponds to a counter that can be activated accordingly according to the received line delay adjustment enable signals w 0-w 3_ enable. Furthermore, each counter may be configured to receive an early-late indication signal from matrix error combiner 450, which may be used as a basis for controlling the corresponding counter to be turned up or down (U/D) according to the early-late indication signal. Each counter may be tapered according to the sampling clock after delay 470. In some embodiments, the stored value in each counter may be provided (e.g., as a binary bit) to a corresponding line delay adjustment circuit, as shown, for example, in fig. 5.

Fig. 13 is a flow diagram of a method 1300 according to some embodiments. As shown, method 1300 includes: successively received data values 1302 are obtained. By analyzing 1304 the received data values, it is determined whether the respective data corresponds to a set of single pair line transitions. If the judgment result is 'no', returning to the starting step of the method to obtain the next group of received data; if the determination is "yes," then the line corresponding to the code transition is identified 1306, for example, by the control logic 910 described above in connection with Table 2. Upon identifying the wire, a dynamic wire count value representing a total delay value is updated 1308 based on the received early-late information. When the dynamic error count value for a given line reaches an action threshold 1310, the line specific delay is adjusted according to the stored error count value 1312. In some embodiments, the lines may be initially made non-delayed by initializing the line-specific delay values, and then the amount of delay per line is algorithmically increased so that all lines have a delay relative to the "slowest" line that holds a delay value corresponding to zero delay. In an alternative, each line may be initialized to have a certain preset initial delay value, and then the time offset correction algorithm increases/decreases the amount of delay according to the composite time offset measurement signal. Furthermore, after the multi-wire bus is time offset corrected, each wire-specific delay value may be subtracted by the smallest wire-specific delay value, so that the "latest" wire does not experience any delay, while all other wires have wire-specific delay values relative to the "latest" wire.

The above embodiments describe a method of correcting a time offset with a vector signaling code having a codeword that represents a combination of a plurality of subchannels and is received via a multi-line bus. It should also be noted that each line serves as an input of at least two MICs, and therefore the time offset value of each line can be updated through the outputs of at least two different MICs, so as to realize a unified time offset relationship among the lines of the multi-line bus. At least one purpose of the time offset correction algorithm is to enable a greater eye opening for all MICs by adjusting the line specific delay values of all lines of the multi-line bus.

Fig. 14 is a flow diagram of a method 1400 according to some embodiments. As shown, the method 1400 includes: a plurality of codewords for a plurality of consecutive signaling time intervals are received 1402, each codeword being received as a plurality of symbols over a respective line of a multi-line bus, the plurality of symbols being received by a plurality of multiple-input comparators (MICs), wherein each symbol is received by at least two MICs. At 1404, for each codeword, a respective linear combination of the received symbols is generated. Further, a plurality of composite time offset measurement signals for the successive signaling time intervals are generated 1406, each composite time offset measurement signal being based on samples of one or more linear combinations, and line-specific time offset values for lines of the multi-line bus are updated 1408, wherein the one or more line-specific time offset values are updated in accordance with the composite time offset measurement signal associated with the linear combination formed by the at least two different MICs.

In some embodiments, at least one of the plurality of composite time offset measurement signals corresponds to a measurement of a single MIC, such time offset measurement signal containing time offset components for all lines connected to the MIC. An embodiment for updating line-specific delay elements with a composite time-offset measurement signal formed from the outputs of a single MIC is described in Hormati II. In such embodiments, the composite time offset measurement signal corresponds to an eye measurement obtained as follows: sampling the linear combination of the MICs relative to a variable vertical threshold; it is determined whether the effective eye opening of the MIC increases or decreases when the line has a forward or reverse timing offset (i.e., a timing offset that causes the line signal to advance or retard relatively). In some embodiments, at least one of the plurality of composite time offset measurement signals is generated from a linear combination generated by at least two MICs, the linear combination containing time offset components of all lines associated with the at least two MICs. Fig. 4 shows one such embodiment in which the outputs of two or more MICs are combined with each other.

In some embodiments, updating the line-specific timing offset value for the given line comprises: the capacitance associated with the given line is adjusted. In some embodiments, the adjusting of the capacitance comprises: controlling a switched capacitor network connected to the given line. Fig. 5 illustrates an exemplary line-specific delay element in which a capacitor is selectively coupled to a line by a bit to effect adjustment of the delay value. In some embodiments, C0, C1, and C2 are equal in capacitance, and these capacitors are controlled by a thermometer code. In the alternative, C0, C1, C2 may have different capacitances, and eight different combinations of capacitors C0, C1, C2 may be selected from B0-B2. Although only three capacitive elements are described above, such circuitry is not so limited and may contain more or fewer capacitive elements. In some embodiments, the one or more linearly combined samples are compared to a preset offset voltage by a dual input comparator, and the composite time offset measurement signal represents an early-late indication signal.

In some embodiments, the line-specific timing offset value is updated in response to a determination of a valid codeword sequence. In such embodiments, the updating of the line-specific timing offset value for each line of the multi-line bus may include: updating a line associated with the valid codeword sequence. In some embodiments, the line specific time offset value for a given line is updated in response to a subset of the generated composite time offset measurement signals for the consecutive plurality of signaling time intervals exceeding an action threshold.

In some embodiments, each linear combination operation is performed by a respective MIC among the multiple MICs, and the linear combination operation performed by the respective MIC is determined by a respective subchannel vector of multiple mutually orthogonal subchannel vectors.

Appendix I