阅读说明：本技术 具有粘合剂管芯附接的扇出式层叠封装 (Fan-out package-on-package with adhesive die attach ) 是由 D·奥沙利文 B·魏达斯 T·休伯 于 2019-04-16 设计创作，主要内容包括：扇出式层叠封装(PoP)组件,其中第二芯片粘附到第一芯片的非有源侧。第一芯片的嵌入在第一封装材料中的有源侧可以通过一个或多个再分布层电耦合,所述一个或多个再分布层扇出到PoP的第一侧上的封装互连。可以用第二封装材料将第二芯片粘附到第一芯片的非有源侧。第二芯片的有源侧可以通过延伸穿过第一封装材料的过孔结构电耦合到封装互连。第二芯片或其封装之间的第二互连可以接触过孔结构。将第二封装材料用作粘合剂可以改善第二芯片的位置稳定性,以促进晶圆级组装技术。(A fan-out package-on-package (PoP) assembly in which a second chip is adhered to a non-active side of a first chip. The active side of the first chip embedded in the first encapsulation material may be electrically coupled through one or more redistribution layers that fan out to the package interconnects on the first side of the PoP. A second encapsulant may be used to adhere the second chip to the non-active side of the first chip. The active side of the second chip may be electrically coupled to the package interconnect through a via structure extending through the first package material. A second interconnect between the second chip or its package may contact the via structure. The use of the second encapsulation material as an adhesive may improve the positional stability of the second chip to facilitate wafer-level assembly techniques.)

1. A microelectronic device package assembly, comprising:

a first chip including a first Integrated Circuit (IC);

a via structure adjacent to the first chip;

a first encapsulant material between sidewalls of the first chip and sidewalls of the via structure;

One or more redistribution layers electrically coupled to a first side of the first chip and electrically coupled to a first side of the via structure;

a second chip comprising a second IC, wherein the second chip is over a second side of the first chip opposite the first side, and wherein the second chip is electrically coupled to a second side of the via structure; and

a second encapsulant between at least a portion of the first chip and at least a portion of the second chip.

2. The device package assembly of claim 1, wherein the first encapsulant material is between the second side of the first chip and the second encapsulant material.

3. The device package assembly of any of claims 1-2, wherein:

the second encapsulant material is between at least a portion of the via structure and at least a portion of the second chip; and is

The first encapsulant material is between the second side of the via structure and the second encapsulant material.

4. The device package assembly of any of claims 1-2, further comprising a plurality of interconnects electrically coupling the second chip to the via structure.

5. The device package assembly of claim 3, wherein the interconnects comprise solder features and the second packaging material is absent between the solder features.

6. The device package assembly of claim 5, further comprising a third encapsulation material between the solder features.

7. The device package assembly of claim 6, wherein the third encapsulation material is between the second chip and the first encapsulation material, and wherein sidewalls of the third encapsulation material are adjacent to sidewalls of the second encapsulation material.

8. The device package assembly of claim 4, wherein:

the interconnects are aligned in a row adjacent to a first edge of the second chip;

a first portion of a footprint of the second chip occupied by the row of interconnects overhangs an edge of the second encapsulation material; and is

A second portion of the footprint of the second chip unoccupied by the row of interconnects is in contact with the second encapsulation material.

9. The device package assembly of claim 8, wherein the second encapsulation material extends at least beyond a second edge of the second chip opposite the first edge of the second chip.

10. The device package assembly of any of claims 1-9, wherein:

the first encapsulating material comprises a first epoxy resin;

the second encapsulating material includes a second epoxy resin; and wherein the one or more of the one,

the assembly also includes a third epoxy over the second chip.

11. A packaged microelectronic device, comprising:

a microprocessor chip, wherein a first side of the microprocessor chip is electrically coupled to one or more redistribution layers of a package;

a via structure adjacent to the microprocessor chip, wherein a first side of the via structure is electrically coupled to the one or more redistribution layers;

a first encapsulant between sidewalls of the microprocessor chip and sidewalls of the via structure;

a memory chip over a second side of the microprocessor chip, over a second side of the via structure, and electrically coupled to the second side of the via structure; and

a second encapsulant between the microprocessor chip and the memory chip.

12. The microelectronic device of claim 11, wherein the microprocessor comprises a baseband radio processor, and wherein the memory chip comprises DRAM.

13. The microelectronic device of any of claims 11-12, wherein:

the first encapsulation material is over the second side of the processor chip and the memory chip;

the second encapsulant material is over the first encapsulant material;

the memory chip is electrically coupled to the second side of the via structure by a plurality of interconnects that each extend through a thickness of the first encapsulation material over the second side of the processor chip; and is

An edge of the second encapsulant proximate the conductive feature is laterally spaced from a sidewall of at least one of the interconnects.

14. The microelectronic device of any of claims 11-12, further comprising a third encapsulation material between the interconnects and between an edge of the second encapsulation material and the sidewalls of at least one of the interconnects.

15. A method of fabricating a microelectronic package assembly, the method comprising:

receiving a workpiece comprising a first chip and a via structure embedded within a first encapsulation material, wherein a first side of the first chip and a first side of the via structure are electrically coupled to one or more redistribution layers of a package;

Applying a second encapsulation material over a second side of at least a portion of the first chip;

adhering one or more components to the second encapsulation material, the components including a second chip and a plurality of interconnects electrically coupled to the second chip; and

reflowing the plurality of interconnects to electrically couple the second chip to the second side of the via structure.

16. The method of claim 15, wherein applying the second encapsulation material comprises at least one of: screen printing the adhesive material, patterning the layer of adhesive material, needle dispensing the adhesive material, or picking and placing pre-fabricated pads of adhesive material.

17. The method of any of claims 15-16, further comprising assembling the workpiece prior to applying the second encapsulation material, the assembling comprising:

molding the first chip and the via structure within the first encapsulation material;

forming the one or more redistribution layers coupled to the first side of the first chip and the first side of the via structure; and

a plurality of second interconnects is formed on the first side of the first encapsulation material, and the plurality of second interconnects is coupled to the one or more redistribution layers.

18. The method of any of claims 15-16, further comprising forming a through mold via through a thickness of the first encapsulant material over the second side of the via structure.

19. The method of any of claims 15-16, further comprising pre-curing the second encapsulation material prior to attaching the one or more components.

20. The method of any of claims 15-16, further comprising underfilling a third encapsulation material between the plurality of interconnects electrically coupled to the second chip.

21. The method according to any one of claims 15-16, further comprising:

coating, molding, or spraying a final encapsulation material over the second chip.

Background

In electronic product fabrication, Integrated Circuit (IC) packaging is a stage in semiconductor device fabrication in which ICs that have been fabricated on a die or chip comprising semiconductor material are encapsulated in a supporting box or "package" that can protect the ICs from physical damage and support electrical contacts that connect the device to a main circuit board. In the IC industry, the process of manufacturing a package is often referred to as packaging or assembly.

Package on package (PoP) technology is a 3D package architecture that vertically integrates multiple components (e.g., IC chips), with two or more packages mounted (i.e., stacked) on top of each other. IC chips may be assembled in various ways within a PoP architecture. For example, a first IC chip may have a Ball Grid Array (BGA) package, and a second IC chip stacked on the first IC chip may be connected to the first IC chip through an additional BGA connection portion. As another example, a first IC chip may have a flip-chip BGA package (e.g., FCBGA), while a second IC chip stacked on the back side of the first chip is connected to the first IC chip by wire bonds (e.g., hybrid stacked FBGA).

The current trend of PoP and flip chip wire-bond packages presents new challenges in terms of high volume manufacturability and physical size of the package. Even with the increased complexity of device design, devices are under greater pressure to achieve new milestones in form factor. In PoP package architectures, z-height (thickness) is a very important characteristic. For example, in some device applications, a package z-height of 0.3-0.4mm or less is highly desirable.

Wafer Level Packaging (WLP) techniques, in which many chips are packaged in parallel on a carrier wafer or panel, are advantageous for high volume manufacturability. For example, in a fan-out package, the die is embedded in a molding compound during the reconfiguration process. The I/O of the die may then be redistributed with conductive routing between the die and the solder features, which may extend any distance from the edge of the die while supported by the molding compound. However, many WLP technologies are challenging to scale to PoP architectures. For example, one challenge is to add sufficient stability to the top die attach process.

Drawings

The subject matter described herein is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. For simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the drawings:

fig. 1A is a flow diagram illustrating a method of fabricating a fan-out PoP with adhesive die attach in accordance with some embodiments;

fig. 1B is a flow diagram illustrating a method of fabricating a fan-out PoP with adhesive die attach in accordance with some embodiments;

fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G illustrate cross-sectional views of a fan-out PoP with adhesive die attach developed as selected operations in a method of fabricating a fan-out PoP are performed, in accordance with some embodiments;

fig. 3A illustrates a top plan view of a fan-out PoP with adhesive die attach in accordance with some embodiments;

fig. 3B illustrates a cross-sectional view of a fan-out PoP with adhesive die attach, in accordance with some embodiments;

Fig. 3C illustrates a cross-sectional view of two contiguous fan-out pops with adhesive die attach, in accordance with some embodiments;

fig. 4 illustrates a mobile computing platform and data server machine employing a fan-out PoP with adhesive die attach, in accordance with an embodiment; and

FIG. 5 is a functional block diagram of an electronic computing device according to some embodiments.

Detailed Description

One or more embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that the techniques and/or arrangements described herein may be used in a variety of other systems and applications in addition to those described in detail herein.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and which illustrate exemplary embodiments. Moreover, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of the features in the figures. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment in any event that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) or in physical or electrical contact with each other, and/or that two or more elements cooperate or interact with each other (e.g., as a cause and effect relationship).

The terms "above," "below," "between," and "upper" as used herein refer to the relative position of one component or material with respect to another component or material where such a physical relationship is significant. For example, in the context of materials, one material or a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, the material or one disposed between two materials may be in direct contact with the two layers, or may have one or more intervening layers. Rather, a material or first material "on" a material or second material is in direct contact with the second material/material. Similar distinctions are made in the context of component assemblies.

As used throughout this specification and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "A, B or at least one of C" may represent a; b; c; a and B; a and C; b and C; or A, B and C.

Described herein are exemplary fan-out package-on-package (PoP) assemblies in which a die is adhered to another die. In some examples, the active side of the first die embedded in the first encapsulation material may be electrically coupled through one or more redistribution layers that fan out to the package interconnects on the first side of the PoP assembly. The second chip may be adhered to the non-active side of the first chip, for example, using a second encapsulant material. The second encapsulant material may be any suitable material suitable for maintaining the position of the second chip relative to the first chip and/or relative to a via structure extending through the first encapsulant material and electrically coupling the active side of the second chip to the redistribution layer and/or package interconnects on the first side of the PoP assembly. Accordingly, a redistribution layer and/or package interconnect on the first side of the PoP assembly may electrically couple the first chip to the second chip, wherein the via structure occupies a portion of the PoP assembly area adjacent to the first chip supporting fan-out. A second interconnect between the second chip (or a package of the second chip that also includes other redistribution layers) may contact the via structure. These second interconnects may be reflowed while the adhesion provided by the second encapsulant maintains proper positioning of the second chip.

Further described herein are exemplary methods for manufacturing a fan-out PoP assembly, wherein an adhesive is applied between a first component (e.g., an IC chip) and a second component (e.g., an IC chip). For example, the adhesive may be applied after subjecting the first chip to a wafer-level fanout process. In some embodiments, adhesive is selectively applied to the non-active side of the first die to position the adhesive material in a manner that makes an adjacent (off-die) via structure available to receive an interconnect structure present on the second component. The second component may be pressed into the adhesive, for example with a pick and place machine, such that the interconnect structure coupled to the second component is placed over the via structure. As described further below, once the second component is adhered in place, additional operations may then be performed. For example, another encapsulation material may be underfilled between the interconnect structures of the second component. In another example, one or more additional encapsulation materials may be applied over the second component. During the assembly process, a final reflow may be performed to form intimate contact between the second component and the via structure. As described further below, adhesive materials employed within PoP assembly architectures according to embodiments herein may facilitate wafer-level processing of PoP assemblies, which may enable reduced z-heights (e.g., PoP thicknesses).

Fig. 1A is a flow diagram illustrating a method 101 for fabricating a fan-out PoP with adhesive die attach, in accordance with some embodiments. The method 101 begins at block 110 with receiving a workpiece including a first IC chip. In an exemplary embodiment, a workpiece is panelized and includes a plurality of first IC chips arrayed over a panel for parallel package assembly. For example, the workpiece may have been fabricated upstream of block 100 according to any IC chip reconfiguration process. The workpiece received at block 110 also includes a first encapsulation material. The first IC chip may be at least partially embedded within the first encapsulant material. The precursor of the via structure or "through package" or "through mold" via together with the first IC chip occupies a region within the first packaging material adjacent to an edge of the first IC chip. Thus, the via structure or precursor is located outside the first chip within a portion of the first encapsulation material, which may also support fan-out of input/output (I/O) routing of the first IC chip that is present within one or more conductive redistribution layers on the first side of the first encapsulation material. For example, one or more of the I/os of the first IC chip may be electrically coupled to one or more vias of the via structure and/or may extend into a portion of the first encapsulant material that will receive the through mold vias.

The method 101 continues at block 120 with applying a second encapsulation material to the workpiece at block 120. The second encapsulating material will be at least temporarily operable as an adhesive. The second encapsulation material may have any composition and may be applied in any manner such that the second encapsulation material is operable to adhere the second IC chip (e.g., within the second package) to the first IC chip and/or to the first encapsulation material. Advantageously, the second encapsulation material is selectively applied and/or patterned at block 120 to some predetermined dimension(s) of adhesive features in order to facilitate electrical connection between one or more I/os of the second IC chip (or package thereof) and the via structure. For example, the second encapsulant material may be confined to a region adjacent the via structure/precursor over the first IC chip and/or over the first encapsulant material such that electrical connections may be made between the second IC chip I/O and the via structure without interference from the second encapsulant material. As described further below, the block 120 may include one or more of the following: screen printing the second encapsulant material, mask-based patterning the second encapsulant material, selectively dispensing the second encapsulant material, or picking and placing pre-fabricated pads of the second encapsulant material. For example, block 120 may be performed for each package assembly within a panelized workpiece.

In some embodiments, for example, where the fan-out region of the first encapsulant material lacks a pre-fabricated via structure, one or more via structures may be formed at block 120 (either before or after application of the second encapsulant material). For example, one or more through-mold vias may be milled (e.g., with any suitable laser ablation process or etching process) into a portion of the first encapsulant material adjacent to the first IC chip and/or adjacent to the second encapsulant material feature. Such through-mold vias may expose one or more conductive features coupled to the first IC chip through the redistribution layer(s) within the fan-out area adjacent to an edge of the first IC chip. In other embodiments where the fan-out region of the first package material includes a pre-fabricated via structure, the block 120 may include one or more operations to prepare (e.g., expose) a conductive surface of the via structure in preparation for a subsequent block in the method 101. Such an operation may be performed again before or after the application of the second encapsulating material.

The method 101 continues at block 130 with mounting, securing or adhering a second IC chip or package containing a second IC chip (i.e., a second component) to a second packaging material at block 130. At block 130, any technique known to be suitable for placing an IC chip onto a package substrate, board, PoP assembly, or the like, may be employed. As one example, a pick and place machine may pick and place a second IC chip onto a second packaging material. Thus, the size of each "pad" or feature of the second encapsulation material should be sufficient to accommodate the positional accuracy of the pick and place machine. In some exemplary embodiments in which the second IC chip is coupled to external electrical interconnects, such as solder or solder paste features (e.g., ball grid arrays, microspheres, bumps, solder bars or posts), block 130 may entail aligning the second IC chip to a reference so that the electrical interconnects coupled to the second IC chip may make contact with the conductive features of the via structures. For example, the block 130 may again be performed for each package assembly within the panelized work piece. Such a parallel PoP assembly may utilize an adhesive provided by the second encapsulant material such that there is sufficient stability in the common location of the second IC chip and the corresponding via structure.

The method 101 continues at block 150 where a thermal process is performed to heat the package assembly to an elevated temperature sufficient to reflow the one or more electrical interconnects at block 150. For example, where the component comprising the second chip includes external electrical interconnects (e.g., solder and/or solder paste features), these electrical interconnects are heated at block 150 to any temperature suitable for reflow to sufficiently electrically couple the I/O ports of the second IC chip to at least the conductive features of the via structure.

The method 101 completes at operation 160 and at operation 160 the package assembly is completed by any further packaging operations known to be suitable for PoP assemblies. For example, block 160 may include applying additional packaging material, and/or laser marking each PoP assembly within a panel, and/or singulating a panel of PoP assemblies, and/or electrically testing the PoP assemblies, and/or packaging the PoP assemblies for shipment to an end user (e.g., a platform or board level assembly plant). Notably, one or more of the blocks in method 101 may be iterated to increase the number of IC chips integrated within a PoP assembly to more than two chips. For example, blocks 120 and 130 may be repeated any number of times with additional chips adhered to additional adhesive encapsulation material, limited only by the footprint of the additional component(s), and the size of the through-mold vias and/or via structures electrically coupled to any additional adhesive attachment component(s).

Several exemplary embodiments of fabricating a fan-out PoP with adhesive die attach are summarized with method 101, and method 102 of fabricating a fan-out PoP with adhesive die attach is further described in the context of fig. 1B, in accordance with some specific embodiments. For example, method 102 may be performed in the practice of method 101. Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G illustrate cross-sectional views of a fan-out PoP with adhesive die attach as selected blocks in method 102 are performed, according to some example embodiments.

Referring first to fig. 1B, method 102 begins at block 103 by embedding a first IC chip within a first package matrix material, which in some exemplary embodiments is any material known to be suitable for IC chip package mold casting, at block 103. The first encapsulant material may be any suitable dielectric material and may be introduced into the casting wet/uncured and then dried/cured. Alternatively, the first encapsulant material may be any suitable dielectric material that may be introduced as a semi-cured dry film, for example as a laminate that is deformed around the first IC chip during package build-up and then fully cured. The first IC chip is advantageously at least partially embedded within the first encapsulation material. For example, in some embodiments, the sidewalls of the first IC chip are at least partially covered by the first encapsulation material, such as by a molding process performed with the active side of the first IC chip facing down on the panel or carrier. The first encapsulant material may also be molded or otherwise applied simultaneously around the pre-fabricated via structures that are placed adjacent to the edge of the first IC. The via structure may comprise any number of materials and may be fabricated according to any suitable technique, such as, but not limited to, microelectronic fabrication and/or micromachining techniques. At block 103, a via structure may also be placed on the carrier or panel and then embedded in the first encapsulation material simultaneously with the first IC chip.

Fig. 2A also shows a cross-sectional via that includes an exemplary component of IC chip 205 partially embedded within encapsulant 215. The cross-sectional view shown in fig. 2A is along line a-a' further shown in the plan view of the completed PoP assembly shown in fig. 3A, and as further described below. For example, the components shown in fig. 2A may be fabricated during block 103 of method 102. In some embodiments, IC chip 205 includes a microprocessor circuit. In some such embodiments, the microprocessor circuit is operable to execute a real-time operating system (RTOS). In some other embodiments, IC chip 205 executes one or more layers of a software stack that controls radio (wireless) functions. In one exemplary embodiment, IC chip 205 includes a digital baseband processor or baseband radio processor (BBP) suitable for use within a mobile phone or other wireless/mobile device.

As further shown in fig. 2A, IC chip 205 has sidewalls 206 substantially embedded within encapsulation material 215. The encapsulating material 215 may be any suitable matrix or carrier material and may be sized to have any size or shape. Many such materials exist, such as, but not limited to, epoxy resins (e.g., acrylates of novolacs, such as Epoxy Phenol Novolac (EPN) or Epoxy Cresol Novolac (ECN)). In some embodiments, the encapsulant 215 is a bisphenol-a epoxy resin, for example, including epichlorohydrin. In some embodiments, the encapsulant 215 includes a bisphenol-F epoxy resin (with epichlorohydrin). In some embodiments, encapsulant 215 includes an aliphatic epoxy resin, which may be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butanediol diglycidyl ether), or have higher functionality (e.g., trimethylolpropane triglycidyl ether). In some embodiments, encapsulant 215 includes glycidyl amine epoxy resins, such as triglycidyl-p-aminophenol (functionality 3) and N, N' -tetraglycidyl-bis- (4-aminophenyl) -methane (functionality 4).

As further shown in fig. 2A, the via structure 210 is also at least partially embedded within the encapsulation material 215. The via structure 210 will be operable as a through-carrier or through-package interconnect, or as a placeholder for such an interconnect. As shown, via structure 210 has sidewalls 211 adjacent to IC chip sidewalls 206. The via structure sidewalls 211 are separated from the IC chip sidewalls 206 by a middle portion of the encapsulation material 215. Thus, via structure 210 is external to IC chip 205 and integrated with IC chip 205 at a package level. The via structure 210 may include one or more semiconductor (e.g., crystalline silicon) and/or dielectric (e.g., silicon dioxide) materials 212, and one or more conductive vias 213 extending through a z-height or z-thickness (in the z-axis of fig. 2A) of the via structure 210. The conductive vias 213 may include any suitable metal(s), such as, but not limited to, tin, aluminum, copper, silver, nickel, gold, tungsten, platinum, and alloys or compounds thereof. It is noted that, for example, as described further below, adjacent packages may share a via structure and the via structures are separated when the packages are singulated. The via structure 210 also includes one or more redistribution layers and/or other conductive feature(s) 214 suitable for subsequent coupling to an interconnect of a second IC chip. The conductive features 214 may have a layout with one or more rows or columns of fixed pitch (e.g., having an orthogonal format), or have a staggered adjacent (dense) arrangement. In some alternative embodiments, the via structure 210 is simply a placeholder that includes one or more sacrificial materials to be removed during fabrication of the one or more through-mold vias. In other embodiments, the via structure 210 is not present at all, and the encapsulation material 215 occupies the entire region of the via structure 210 shown in fig. 2A.

As further shown in fig. 2A, an encapsulation material 215 is over the back side or non-active side of IC chip 205. The thickness T (z-dimension) of the encapsulation material 215 over the backside of the IC chip 205 may vary, but since overall package assembly thickness is important for high value components, the encapsulation material 215 may be thinned or completely removed from the non-active side of the IC chip 205 after the embedding/reconfiguration process. It may be advantageous to thin the encapsulation material 215 in a controlled plurality of chips to achieve a sufficiently uniform thickness to facilitate subsequent formation of through mold vias within the fan-out area of the encapsulation material 215. The encapsulation material 215 may be thinned using any suitable uniform process (e.g., chemical and/or mechanical polishing, grinding, or planarizing). It may be advantageous to have the via structure 210 fully embedded within the encapsulation material 215 so as to protect the via structure 210 from subsequent processing steps.

Returning to fig. 1B, the method 102 continues at block 104 with fabricating one or more redistribution layers (RDLs) coupled to one or more I/O ports of the first IC chip over an active side of the first IC chip and/or over a first package material side at block 104. In an exemplary embodiment, the RDL features extend beyond sidewalls of the first IC chip within a fan-out region of the first component supported by the first encapsulation material adjacent the first IC chip. For example, predefined conductive routes of the RDL may be formed over the active side of the wafer using any suitable subtractive and/or additive fabrication techniques. In some embodiments, RDL fabrication includes one or more of photolithography, thin film sputter deposition, thin film etching, thin film plating, and the like. One or more dry film build techniques may also be employed, such as, but not limited to, lamination of resin films (e.g., GX series films available from Ajinomoto Fine-Techno co., inc. Various subtractive and/or additive fabrication processes may be performed in sequence until electrical traces and/or interconnects have been distributed over the chip and over the fan-out region of the packaging material (i.e., carrier matrix). Fig. 2B illustrates an exemplary structure including the component illustrated in fig. 2A with the redistribution layer 220 added. As shown, RDL 220 includes conductive routing 222 electrically isolated by one or more dielectric materials 223 that have been built over the active side of IC chip 205. Conductive routes 222 may be coupled to one or more chip-level I/O features 224 of IC chip 205. As shown, RDL 220 extends over an area larger than IC chip 205 (which may be referred to as a fan-out structure). The conductive routing 222 may also be coupled to one or more conductive vias 213 of the via structure 210.

Returning to FIG. 1B, the method 102 continues at block 106, where at block 106, an external interconnect is formed that is coupled to the RDL feature formed at block 104. The external interconnects formed at block 106 will make electrical contact with the various previously constructed redistribution layers and, thus, with the various I/O ports of the packaged IC chip. The external interconnects formed at block 106 are also used to subsequently attach the package component(s) to any suitable Printed Circuit Board (PCB). Due to the fan-out of the signal paths in the RDL formed at block 104, the external interconnects may extend beyond the edges of the first IC chip and outside of the package to an external system. In the example further illustrated in fig. 2C, solder feature 230 has been formed or solder feature 230 is attached to conductive RDL feature 222. For example, the solder features 220 may be solder balls that have been attached according to any known process (e.g., with solder flux and a controlled thermal process that may partially reflow one or more of the flux and solder features 220). Alternatively, the solder features 220 may be studs or bumps comprising a conductive material (e.g., solder paste). Returning now to fig. 1B, processing of the active side of the panelized package components is now substantially complete, and the method 102 may optionally continue with electrical testing of the basic package at block 108, if desired. For example, if block 108 is performed, the electrical test may check the overall functionality of the base package. Block 108 may also include tests for determining the yield and/or quality of any package structures external to the IC chip, such as verifying the function of one or more through-mold (through-carrier) vias, before proceeding to subsequent blocks of method 102.

Method 102 continues at block 112 with preparing any lands (lands) of the via structure external to the IC chip for subsequent attachment of another component at block 112. At block 112, any remaining encapsulation material on the non-active side of the via structure may be removed by any suitable technique, as the removal method may depend on the fabrication block previously performed. Alternatively, for embodiments in which through-carrier vias are to be formed, those vias may be formed at block 112. For example, any via precursor structures embedded within the encapsulation material at operation 103 may be exposed and replaced with conductive through-carrier vias. In other embodiments, the carrier encapsulation material itself may be etched, ablated, or otherwise milled and filled at block 112 to form conductive through mold vias or through carrier vias adjacent at least one edge of the IC chip. In the example shown in fig. 2D, the package component from fig. 2C is further processed to form an opening 260 through the thickness of the package material 215 over the via structure 210. The opening 260 exposes the lands on the conductive feature(s) 214. If the conductive feature(s) 214 have been previously exposed, the opening 260 may have been patterned or the result of a plasma clean. Alternatively, a physical removal process (e.g., grinding or lapping, etc.) may be employed to expose the conductive feature(s) 214.

Returning to fig. 1B, the method 102 continues at block 122 with forming adhesive features over a second side of the package component at block 122. At least one adhesive feature may be formed over a single package component (e.g., over a non-active side opposite an active side of the IC chip). Block 122 is advantageously performed, for example, with adhesive features applied to the backside of the panel, while still panelizing the package component and/or carrier material. Each adhesive feature applied at block 122 may then be used to attach another component. In a panelized form, the adhesive features may be formed in parallel according to several processes or techniques.

In the example further shown in fig. 2E, adhesive features 240 have been applied to the package component shown in fig. 2D. As shown in fig. 2E, adhesive feature 240 has a lateral dimension D that is smaller than the lateral dimension of IC chip 205 in this example. As such, adhesive feature 240 is located over a portion of IC chip 205. In this example, encapsulation material 215 is between adhesive feature 240 and IC chip 205 in thickness. However, for some embodiments, encapsulation material 215 may be substantially planar with the inactive side of IC chip 205. Adhesive feature 240 may extend beyond one or more edges of IC chip 205. In the example shown, adhesive feature sidewalls 241 overlap IC chip sidewalls 206. The adhesive feature 240 may also overlap portions of the via structure 210. In the example shown, the adhesive feature sidewalls 241 overlap the via structure edges 211. The adhesive feature 240 may be advantageously applied in a manner that avoids clogging through the strip-shaped opening 261. Alternatively, the order of blocks 112 and 122 in method 102 (fig. 1B) may be reversed and opening 261 passes through the thickness of adhesive feature 240. Adhesive feature 240 may comprise any known encapsulating material(s). In some embodiments, adhesive feature 240 comprises an epoxy. For example, the adhesive feature 240 may be any of the materials described above for the encapsulating material 215. In some embodiments, the adhesive feature 240 is an encapsulating material having a composition different from the composition of the encapsulating material 215. For example, both the encapsulant 215 and the adhesive feature 240 include epoxies, both epoxies having different compositions. In a particular embodiment, the encapsulation material 215 is a first of the materials described above for the encapsulation material 215, and the adhesive feature 240 includes a second of the materials described above for the encapsulation material 215. In some other embodiments, both the encapsulation material 215 and the adhesive feature 240 comprise epoxy, the composition of the two encapsulation materials being not different, however the encapsulation material 215 may be cured prior to applying the adhesive feature 240, such that the material interface between the encapsulation material 215 and the adhesive feature 240 shown in fig. 2E indicates practice of the method 102 (fig. 1B).

In some embodiments, adhesive features 240 (fig. 2E) are applied non-selectively and patterned selectively. In other embodiments, the adhesive features 240 are selectively applied. In some embodiments, the adhesive feature 240 is applied in an undried or substantially uncured state, and then partially cured. In other embodiments, the adhesive feature 240 is applied in a semi-cured state, for example, as a dry film (e.g., a pressure sensitive adhesive, a die attach film, etc.). As one example, adhesive feature 240 may be applied by screen printing, where any suitable pre-fabricated screen or mesh is placed over the workpiece (panel or wafer), aligned with the reference mark, and the adhesive is forced through openings in the mesh over one or more of the underlying IC chip 205 and/or the encapsulation material 215. A mask-based patterning process may also be employed to apply the adhesive features 240. For example, a light-sensitive adhesive material may be dispensed or spin-coated onto the workpiece, with the adhesive exposed to the optical energy defining the boundaries of the adhesive features over one or more of the underlying IC chip 205 and/or the encapsulation material 215. One of the unexposed or exposed adhesive materials may then be removed with any suitable solvent. In other embodiments, adhesive features 240 may be selectively dispensed, for example, from a needle matrix in which each needle position applies a predetermined dose of adhesive material onto one or more of the underlying IC chip 205 and/or packaging material 215 to which adhesive is to be applied. In another example, pre-formed adhesive pads having adhesive features 240 of a desired size may be placed onto one or more of the underlying IC chip 205 or the encapsulation material 215. The pads of adhesive material may be placed by any suitable technique, such as, but not limited to, a pick and place machine.

After the adhesive feature 240 is applied, the physical shape and/or composition of the feature may be defined and/or affected, for example, by exposing the wafer to a controlled heat or energy source (e.g., IR lamp, laser, etc.). Such a treatment may pre-cure the adhesive feature 240, for example, to modify the epoxy from an uncured state to a semi-cured state. By process optimization at the application and processing stage, subsequent use of underfill for components to be secured to the adhesive feature 240 may be minimized or even avoided altogether.

Returning to FIG. 1B, the method 101 continues at block 132, where at block 132 one or more additional components are secured to the adhesive features formed at block 122. Any process that provides sufficient placement and pressure control may be used to push the components into the adhesive material on the underlying substrate. The controlled die attach process along with the engineered shape and/or amount of adhesive material may provide a stable foundation under the applied component. The component(s) attached at block 132 may be any component suitable for a PoP package assembly. In some examples, at block 132, an unpackaged IC chip is attached to the adhesive feature. In some other examples, a packaged IC chip is attached to the adhesive feature at block 132. In some such examples, the packaged IC chip attached at block 132 includes one or more RDL layers within the package. In some other examples, the packaged IC chip attached at block 132 includes an encapsulant over one or more sides of the packaged IC chip (e.g., the IC chip has been overmolded). In some other examples, the packaged IC chip attached at block 132 includes external interconnect features to be interfaced with the via structure prepared at block 112.

In the example further illustrated in fig. 2F, IC chip 250 has been secured to adhesive feature 240. IC chip 250 may include any integrated circuit. In some embodiments, IC chip 250 includes memory circuitry. In some such embodiments, the memory circuitry includes Random Access Memory (RAM), and more particularly Dynamic RAM (DRAM), such as, but not limited to, low power DRAM (e.g., LPDDR4, or any other suitable mobile DDR). In one exemplary embodiment, where IC chip 250 is a mobile DDR memory chip, IC chip 205 includes a BBP with pops, then package level interconnects are provided between the chips and are well suited for mobile phones or other wireless/mobile devices. As further shown in fig. 2F, a plurality of interconnects 260 each extend through an opening 261. The interconnects 260 may be any suitable interconnects, such as, but not limited to, solder features (e.g., bumps, microspheres, posts, or rod connections). The interconnect 260 may be further coupled to the IC chip 250 by one or more redistribution layers 255. RDL(s) 255 may, for example, focus I/O ports near one or more edges of the active side of IC chip 250. In the embodiment shown in fig. 2F, interconnect 260 includes a row or column of solder features proximate to chip edge 251. In this example, interconnect 260 is limited to a portion of IC chip 250 that overhangs the footprint of adhesive feature sidewall 241, such interconnect 260 being separated from adhesive feature sidewall 241 by region 270.

Returning to fig. 1B, method 102 may optionally continue at block 134 with the interconnects of the component secured to the adhesive material being underfilled at block 134, and/or method 102 may continue at block 136 with one or more additional encapsulation materials being applied over the component secured at block 132 at block 136. As noted above, underfill block 134 may be avoided in some embodiments, such as where the adhesive material applied at block 122 provides sufficient protection from corrosion and/or other interconnect failure modes. If underfill block 134 is performed in method 102, the underfill material may at least partially fill region 270. Any suitable underfill material may be applied at block 134, such as, but not limited to, any epoxy known to be suitable for such underfill application. In some embodiments, the region 270 is at least partially filled with an underfill material having a different composition than the encapsulation material used as the adhesive feature 240. In other embodiments, the region 270 is at least partially filled with an underfill material having the same composition as the encapsulation material used as the adhesive feature 240. However, for such embodiments, the material interface between the underfill material and the adhesive feature sidewalls 241 may still be indicative of the practice of the method 102.

Fig. 2G further illustrates an embodiment in which an optional top encapsulation material 280 has been applied over IC chip 250. For example, encapsulation material 280 may have been applied at block 136 in FIG. 1B. Alternatively, the component attached at block 132 may already include a top cap as part of the pre-fabricated package. In the example shown in fig. 2G, encapsulation material 280 extends over the entire non-active side of IC chip 250, and also extends over the entire encapsulation material 215, which indicates a blanket deposition process. For example, a spin coating process, a molding process, or a spray coating process may have the encapsulation material 280 deposited. The encapsulation material 280 may have any composition known to be suitable for further protecting the packaged IC from its intended use environment. In some embodiments, for example, the encapsulation material 280 is an epoxy. In some such embodiments where adhesive feature 240 also comprises epoxy, encapsulant 280 has a different composition than adhesive feature 240. In some other embodiments where the encapsulation material 215 also includes an epoxy, the encapsulation material 280 has a different composition than at least one of the adhesive feature 240 and the encapsulation material 215. In some such embodiments, the encapsulation material 280 has a different composition than both the adhesive feature 240 and the encapsulation material 215. In some other embodiments where adhesive feature 240 also includes epoxy, encapsulation material 280 has the same composition as at least one of adhesive feature 240 and encapsulation material 215. In some such embodiments, the encapsulation material 280 has the same composition as both the adhesive feature 240 and the encapsulation material 215. Mechanical material interfaces between the encapsulation material 280 and the adhesive feature sidewalls 241 and/or between the encapsulation material 280 and the encapsulation material 215 may still indicate the practice of block 136 in method 102.

Returning to fig. 1B, the method 102 continues at block 152 where, at block 152, a reflow process is performed to reflow at least the interconnect between the second component and the land of the via structure. Reflow may make permanent electrical contact between the top component and the via structure and/or the through-mold via. Any reflow process known to be appropriate for the selected interconnect may be performed at block 152. During the reflow process, the elevated temperature may further cure one or more of the encapsulation materials that have been applied during the method 102. For example, the adhesive features formed at block 122 may be cured into the final encapsulation material. Likewise, any final encapsulating material(s) applied at block 136 may also be cured to a final state. The method 102 is then completed at block 162, for example, with tagging and singulation of pops.

While the above describes a microelectronic device assembly method for PoP with adhesive die attach, structural features of an exemplary microelectronic device package assembly are further described below in the context of fig. 3A and 3B to emphasize physical attributes indicative of the assembly method. Fig. 3A illustrates a top plan view of a fan-out PoP 201 including adhesive die attach, in accordance with some embodiments. Fig. 3B illustrates a cross-sectional view of the fanout PoP 201 along the line a-a' shown in fig. 3A, in accordance with some other embodiments. For example, the fan-out PoP 201 may be manufactured according to method 101, and more specifically according to method 102.

Referring first to fig. 3A, PoP 201 occupies a footprint in the x-y plane. Within this footprint, encapsulation material 215 occupies a fan-out region including at least one integrated circuit beyond the sidewalls of IC chip 205. Interconnects 230 are arranged within the footprint of IC chip 205 as shown by the dotted lines. One or more rows or columns of interconnects 230 are within the area of the fan-out region. Via structure 210 is adjacent to one edge of IC chip 205 within a footprint of encapsulation material 215. Adhesive feature 240 is placed over a portion of IC chip 205 and also occupies an area extending beyond the edge sidewalls of IC chip 205 proximate via structure 210. Another component including at least IC chip 250 is placed over adhesive material 240. The IC chip sidewalls 252 overlap the adhesive feature sidewalls 241 proximate the via structures 210 by one or more rows or columns of the plurality of interconnects 260 (e.g., solder features) that are aligned with the one or more IC chip sidewalls 252. For example, interconnect 260 may be confined within an overlap or overhang region between IC chip 250 and via structure 210. IC chip 250 is electrically coupled to via structure 210 at least through interconnect 260. In the example shown, the interconnects 260 are positioned beyond the adhesive material sidewalls 241, and thus there is no adhesive material between the interconnects 260. Although two staggered columns (rows) of interconnects 260 are shown in fig. 3A, embodiments may have interconnects of only one or more than two columns. The opposite adhesive material edge extends beyond IC chip sidewall 251 opposite chip sidewall 252 (and opposite via structure 210). Interconnect 260 may also be present along at least some portion of the other edge (e.g., orthogonal to chip sidewall 252), for example, where IC chip 250 has a larger area extending beyond adhesive sidewall 241 and via structure 210 has a larger width (e.g., in the x dimension).

As shown in the cross-sectional view of fig. 3B for PoP 201, encapsulation material 215 is between IC chip sidewalls 206 and via structure sidewalls 211. RDL 220 is electrically coupled to a first side of IC chip 205. RDL 220 is also electrically coupled to a first side of via structure 210. A chip 250 including at least one integrated circuit is over a second side of IC chip 205 opposite RDL 220. Circuitry of IC chip 250 is electrically coupled to a second side of via structure 210. Adhesive feature 240, which includes another encapsulation material, is located between at least a portion of IC chip 205 and at least a portion of IC chip 250. As further shown in fig. 3B, encapsulation material 215 is between adhesive feature 240 and the second inactive side of IC chip 205. With adhesive feature sidewalls 241 overlapping via structure sidewalls 211, a portion of adhesive feature 240 is between via structure 210 and IC chip 250. Encapsulation material 215 is also located between adhesive feature 240 and the second side of via structure 210. In the example shown, there is no adhesive material 240 between the interconnects 260. Thus, region 270 may be a void or underfill encapsulant may surround interconnect 260. Such underfill encapsulant is located between IC chip 250 and encapsulant 215, where the sidewalls of the underfill encapsulant are then adjacent to adhesive material sidewalls 241.

As described above, one or more of the encapsulation material 215, the adhesive feature 240, and the encapsulation material 280 may include an epoxy. Once the adhesive properties of the adhesive feature 240 are utilized, the composition of the adhesive feature 240 may remain distinguishable from the composition of the encapsulation material 215, or the composition of the adhesive feature 240 (e.g., after a curing process) may be substantially the same as the encapsulation material 215. Likewise, after curing of adhesive feature 240, the composition of adhesive feature 240 may remain distinguishable from the composition of encapsulation material 280, or the composition of adhesive feature 240 may be substantially the same as encapsulation material 280. However, the physical material interface may remain indicative of the method of performing the assembly PoP 201.

Fig. 3C illustrates a cross-sectional view of two contiguous fan-out pops 201 and 302 with adhesive die attach, in accordance with some embodiments. In this example, a single via structure 210 is shared between two adjacent pops 201, 302. The via structure 210 may be separated into two portions (e.g., along dashed line 350) during the package singulation process. For such embodiments, the edges of a portion of the via structure 210 remaining within each of the pops 201 and 302 (e.g., along dashed line 350) will not be embedded within the encapsulation material 215. Thus, the mold epoxy may be located between IC chip 205 and via structure 210, but the side of via structure 210 opposite IC chip 205 is free of mold epoxy.

For example, as described elsewhere herein, fig. 4 illustrates a mobile computing platform and data server machine employing a PoP package assembly including adhesive attachment. Server machine 406 may be any commercially available server, including for example any number of high performance computing platforms, including packaged monolithic socs in the exemplary embodiment, disposed within a rack and networked together for electronic data processing. The mobile computing platform 405 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, and the like. For example, the mobile computing platform 405 may be any of a tablet, a smartphone, a laptop, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 410, and a battery 415.

As a system component within server machine 406, packaging assembly 450 may include a memory block (e.g., RAM) and a processor block (e.g., microprocessor, multi-core microprocessor, baseband processor, etc.) interconnected by an RDL fan-out and one or more via structures. For example, as described elsewhere herein, as a packaged integrated system 410, the package assembly 450 includes a PoP assembly with adhesive attachment. The assembly 450 includes one or more of a Power Management Integrated Circuit (PMIC)430, an RF (wireless) integrated circuit (RFIC)425 including a wideband RF transmitter and/or receiver (TX/RX), and a memory 435 interconnected within the PoP assembly, which may be further interconnected to a board within the server 406 or the mobile device 405.

Functionally, PMIC 430 may perform battery power regulation, DC-DC conversion, etc., and thus has an input coupled to battery 415 and an output that provides a current source to other functional modules. As further shown, in the exemplary embodiment, RFIC 425 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher.

FIG. 5 is a functional block diagram of an electronic computing device according to some embodiments. For example, computing device 500 may be found inside platform 405 or server machine 406. Device 500 also includes a motherboard 502 that hosts several components, such as, but not limited to, a processor 504 (e.g., an application processor), for example, processor 504 may be in a package coupled to motherboard 502 by a PoP assembly with adhesive die attach as described elsewhere herein. Processor 504 may be physically and/or electrically coupled to motherboard 502. In some examples, for example, as described elsewhere herein, the processor 504 includes an integrated circuit die packaged within the processor 504, and the connection between the IC die and the processor 504 is within a PoP assembly with adhesive attachment. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 506 may also be physically and/or electrically coupled to the processor 504 within the PoP assembly. Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to motherboard 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Solid State Drive (SSD), Compact Disc (CD), Digital Versatile Disc (DVD), etc.), among others. For example, as described elsewhere herein, any of these other components may also be coupled to the motherboard 502, e.g., through BGA solder connections present on the PoP assembly.

The communication chip 506 may enable wireless communication for transferring data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, the computing device 500 may include a plurality of communication chips 506. For example, a first communication chip may be dedicated for short range wireless communications such as Wi-Fi and Bluetooth, while a second communication chip may be dedicated for long range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

While certain features set forth herein have been described with reference to various embodiments, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the embodiments described herein, as well as other embodiments, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the spirit and scope of the disclosure.

It will be recognized that the principles of the present disclosure are not limited to the embodiments so described, but may be practiced with modification and alteration without departing from the scope of the appended claims. The above embodiments may include undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.