阅读说明：本技术 集成电路、嵌入式系统和机动车 (Integrated circuit, embedded system and motor vehicle ) 是由 E·贝克尔 A·奥厄 M·施赖伯 于 2021-03-19 设计创作，主要内容包括：集成电路、嵌入式系统和机动车。一种集成电路(10),其特征在于如下特征：-所述电路(10)包括具有共同被使用的端口(12)的通信模块(11)；-所述电路(10)包括用于处理至少一个故障情况(14)的故障收集模块(13)；-所述电路(10)被设立为在多个内部通信信道(20、21、22、23、24)上经由所述端口(12)来进行通信；并且-所述故障收集模块(13)具有至少一个硬件路径(31、32、33、34),用于在所述故障情况(14)下选择性地切断各个通信信道(20、21、22、23、24)。(Integrated circuits, embedded systems, and automotive vehicles. An integrated circuit (10) characterized by the following features: -the circuit (10) comprises a communication module (11) with a commonly used port (12); -the circuit (10) comprises a fault collection module (13) for handling at least one fault condition (14); -the circuit (10) is set up to communicate via the port (12) on a plurality of internal communication channels (20, 21, 22, 23, 24); and-the fault collection module (13) has at least one hardware path (31, 32, 33, 34) for selectively cutting off individual communication channels (20, 21, 22, 23, 24) in case of the fault condition (14).)

1. An integrated circuit (10) is provided,

the method is characterized by comprising the following steps:

-the circuit (10) comprises a communication module (11) with a commonly used port (12);

-the circuit (10) comprises a fault collection module (13) for handling at least one fault condition (14);

-the circuit (10) is set up to communicate via the port (12) on a plurality of internal communication channels (20, 21, 22, 23, 24); and is

-the fault collection module (13) has at least one hardware path (31, 32, 33, 34) for selectively cutting off individual communication channels (20, 21, 22, 23, 24) in case of the fault condition (14).

2. The circuit (10) of claim 1,

the method is characterized by comprising the following steps:

-the communication module (11) is set up to manage a transmit queue (40, 41, 42, 43, 44) and a receive queue (50, 51, 52, 53) for the communication channel (20, 21, 22, 23, 24); and is

-the hardware path (31) is set up to selectively block or empty the respective transmit queues (40, 41, 42, 43, 44).

3. The circuit (10) of claim 1 or 2,

the method is characterized by comprising the following steps:

-the communication module (11) is set up for medium access control (15); and is

-the hardware path (32) is set up to strip the respective communication channel (20, 21, 22, 23, 24) from the medium access control (15).

4. The circuit (10) of any of claims 1 to 3,

the method is characterized by comprising the following steps:

-the circuit (10) comprises a random access memory (16);

-the communication module (11) is set up for direct memory access (60, 61, 62, 63, 64) to the random access memory (16); and is

-the hardware path (33) is set up to disable the direct memory access (60, 61, 62, 63, 64) on the respective communication channel (20, 21, 22, 23, 24).

5. The circuit (10) of any of claims 1 to 4,

the method is characterized by comprising the following steps:

-the circuit (10) comprises a plurality of processor cores (70, 71, 72, 73, 74);

-the processor cores (70, 71, 72, 73, 74) are combined into partitions (81, 82, 83, 84, 85) which are assigned respective communication channels (20, 21, 22, 23, 24); and is

-the hardware path (34) is directed from the fault collection module (13) to the processor core (70, 71, 72, 73, 74).

6. The circuit (10) of any of claims 1 to 5,

the method is characterized by comprising the following steps:

-said circuit (10) has at least one external fault contact (17) for controlling said fault collection module (13).

7. The circuit (10) of any of claims 1 to 6,

the method is characterized by comprising the following steps:

-the communication module (11) is an ethernet module (11) with a media independent interface (18); and is

-another hardware path leads directly from the fault collection module (13) to the interface (18).

8. A microcontroller (10) as claimed in any one of claims 1 to 7.

9. An embedded system having a circuit (10) according to any of claims 1 to 8.

10. A motor vehicle having a system according to claim 9.

Technical Field

The invention relates to an integrated circuit, in particular to a microcontroller. The invention also relates to an embedded system with such an integrated circuit and to a motor vehicle with such an integrated circuit.

Background

The circuit for embedded systems according to the prior art has a plurality of processor cores and complex peripheral functions like ethernet interfaces. Within the framework of the AUTOSAR standard, for example, individual software components on a commonly used multi-core (multicore) or multiprocessor system are typically organized in logical application partitions for purposes of system virtualization and providing protection boundaries.

DE102016211768a1 relates to an integrated ethernet communication module for Media Access Control (MAC) via Direct Memory Access (DMA).

Disclosure of Invention

The invention provides an integrated circuit, in particular in the form of a microcontroller (μ C), an embedded system having such an integrated circuit, and a motor vehicle having such an integrated circuit, according to the independent claims.

The proposed solution is based on the following recognition: integrated ethernet MAC communication modules are known that have multiple queues (queues) and integrated DMA channels for transmission and reception. These queues and DMAs may be assigned to different independent partitions or applications in multi-core-microcontroller and microprocessor architectures. A partition or application has its own memory area and may be implemented on a CPU or distributed across multiple CPUs. Here, a partition is considered a logical unit that can access the ethernet module. It is also possible to run multiple partitions on one CPU.

In this case, each partition communicates via a separate logical ethernet communication channel and is allowed to be unaffected by the other partitions in terms of guaranteed bandwidth and latency in order to ensure deterministic behavior. The communication channel is characterized by its own MAC and/or IP address and is typically composed of a queue in an ethernet communication controller (MAC), one or more DMA channels to which it belongs, and its own configuration. The transmission and reception of all defined communication channels takes place via the same ethernet communication controller. The transmission of messages is controlled in the MAC layer by priority provisioning or polling (round robin).

The device according to the invention also takes into account the fact that: hardware faults threatening the operational safety (safety) in μ C are typically handled in an Error Management Module (EMM). There is also an external fault contact (error pin), wherein the function defined in μ C can be switched off by the external monitoring module by an EMM or directly.

For each failure, a corresponding system response may be configured in the EMM. In the case of a communication module according to the prior art, the entire message content is generally regarded as untrusted in the event of a fault. Due to the failure, the ethernet packet that appears to be valid may contain a corrupted message. To prevent the sending of this corrupted message, the ethernet sending function at the media-independent interface (xMII) is normally immediately deactivated in case of a failure by a Failure Collection and Control Unit (FCCU) or a failed contact. In this way, the transmission of messages with errors can be stopped in time. In this way, in a system with multiple partitions, all communication channels are cut off at the same time, although the fault that develops may involve only one partition and thus only the communication of that partition has to be stopped and the other partitions may continue to transmit.

In this context, separate hardware paths from a central fault collection module and externally accessible fault contacts for cutting off the respective ethernet communication channels of the module are proposed.

The advantage of this solution is that it opens up the possibility of targeted removal of only the partition involved in the failure from the ethernet communication. Thus, other partitions may continue to communicate on the ethernet bus unaffected.

Advantageous embodiments and refinements of the basic idea specified in the independent claims are possible by the measures mentioned in the dependent claims.

Drawings

Embodiments of the invention are illustrated in the drawings and are further described in the following description.

The only figure shows a block diagram of μ C according to an embodiment.

Detailed Description

The figure illustrates the basic configuration of a circuit (10) according to the invention in the form of a microcontroller (10) having a plurality of processor cores (70, 71, 72, 73, 74) which partially form partitions (81, 82, 83, 84, 85) with a delimited random access memory (RAM 16). The microcontroller (10) also comprises an Ethernet communication module (11) with a common used port (12) which manages transmit queues (40, 41, 42, 43, 44) and receive queues (50, 51, 52, 53) for a plurality of internal communication channels (20, 21, 22, 23, 24). The microcontroller (10) also comprises a central fault collection module (13) having hardware paths (31, 32, 33, 34) which enable selective disconnection of the individual communication channels (20, 21, 22, 23, 24) in the event of a fault situation (14). To achieve this goal, the hardware paths (31, 32, 33, 34) may take different routes without departing from the scope of the invention.

The hardware path is set up to immediately block or empty one of the transmit queues (40, 41, 42, 43, 44), for example according to a first option (31). According to a second option (32), the hardware path leads directly to the MAC layer and is set up to strip one of the communication channels (20, 21, 22, 23, 24) from the medium access control (15). According to a third option (33), the hardware path is set up as: direct memory access (60, 61, 62, 63, 64) is disabled on the communication channel (20, 21, 22, 23, 24) concerned. Finally, according to a fourth option (34), the hardware path is routed from the fault collection module (13) not to the communication module (11) but to the individual processor cores (70, 71, 72, 73, 74), which in the event of a fault (14) prevent the data transmission on the communication channel (20, 21, 22, 23, 24) concerned in a software manner by means of an interrupt.

The circuit (10) generally also has: an external fault contact (17) for controlling the fault collection module (13); and a conventional hardware path from the fault collection module (13) directly to the xMII interface (18).

Such a microcontroller (10) can be embedded in a motor vehicle, for example, as a system-on-chip (SoC).