阅读说明：本技术 启动电路和振荡电路 (Starting circuit and oscillating circuit ) 是由 管璐璐 李曙光 浦小飞 于 2020-08-04 设计创作，主要内容包括：本申请提供一种启动电路和振荡电路,该启动电路包括：控制电路,用于生成第一控制信号；生成电路,连接所述控制电路,用于根据所述第一控制信号,生成变化的参考信号；比较电路,所述比较电路的反向输入端连接所述生成电路,正相输入端接入比较信号,所述比较电路用于将所述参考信号与所述比较信号比较后,输出按照预设频率变化的时钟信号。本申请实现了通过启动电路提供按照晶体谐振频率变化的时钟信号,以便于加速启动晶振电路。(The application provides a starting circuit and an oscillating circuit, the starting circuit includes: a control circuit for generating a first control signal; the generating circuit is connected with the control circuit and used for generating a changed reference signal according to the first control signal; and the comparison circuit is used for comparing the reference signal with the comparison signal and outputting a clock signal which changes according to a preset frequency. The application realizes that the clock signal which changes according to the resonance frequency of the crystal is provided by the starting circuit so as to accelerate the starting of the crystal oscillator circuit.)

1. A start-up circuit, comprising:

a control circuit for generating a first control signal;

the generating circuit is connected with the control circuit and used for generating a changed reference signal according to the first control signal;

and the comparison circuit is used for comparing the reference signal with the comparison signal and outputting a clock signal which changes according to a preset frequency.

2. The circuit of claim 1, wherein the generation circuit comprises:

the first resistor is connected with a first switch in series, and the first switch is used for controlling the electrifying state of the first resistor;

a tuning capacitor connected to the first resistor, the tuning capacitor being connected in parallel with a second switch for controlling the energization state of the tuning capacitor;

the control circuit is connected with the first switch, and the first control signal is used for controlling the opening or closing of the first switch.

3. The circuit of claim 2, further comprising:

the input end of the second inverter is connected with the control circuit, the output end of the second inverter is connected with the second switch, and a second control signal output by the second inverter is used for controlling the opening or closing of the second switch;

when the first switch is closed and the second switch is open, the generating circuit of the first resistance and the tuning capacitor generates the varying reference signal.

4. The circuit of claim 1, further comprising:

and the input end of the third phase inverter is connected with the generating circuit, and the output end of the third phase inverter is connected with the control circuit.

5. The circuit of claim 1, wherein the comparison circuit comprises:

the output end of the generating circuit is connected with the reverse input end of the first comparator, and the forward input end of the first comparator is connected with a first comparison signal;

the output end of the generating circuit is connected with the reverse input end of the second comparator, and the forward input end of the second comparator is connected with a second comparison signal;

and when the first comparator and the second comparator work alternately, a clock signal which changes according to the preset frequency is generated.

6. The circuit of claim 5, wherein the comparison circuit further comprises:

and the input end of the trigger is respectively connected with the output end of the first comparator and the output end of the second comparator.

7. The circuit of claim 6, wherein the comparison circuit further comprises:

the first signal source is connected with the positive input end of the first comparator and used for generating the first comparison signal; the output end of the trigger is connected with the first signal source, and a first clock signal output by the trigger is used for controlling the first signal source to be switched on or switched off;

the first signal source includes:

the first current source is connected with the output end of the trigger;

one end of the first capacitor is connected with the first current source, and the other end of the first capacitor is grounded;

the second signal source is connected with the positive input end of the second comparator and used for generating the second comparison signal;

the second signal source includes:

the second current source is connected with the output end of the trigger;

and one end of the second capacitor is connected with the second current source, and the other end of the second capacitor is grounded.

8. The circuit of claim 7, wherein the comparison circuit further comprises:

the input end of the first phase inverter is connected with the output end of the trigger, the output end of the first phase inverter is connected with the second signal source, and a second clock signal output by the first phase inverter is used for controlling the opening or closing of the second signal source.

9. An oscillating circuit, comprising: the startup circuit of any one of claims 1 to 8;

and the crystal oscillator circuit is connected with the output end of the comparison circuit of the starting circuit and is used for accessing a clock signal which changes according to the preset frequency, and the preset frequency is the resonance frequency of the crystal oscillator circuit.

10. The circuit of claim 9, further comprising:

and the third switch and the fourth switch are respectively connected with the control circuit and the crystal oscillator circuit, and the first control signal output by the control circuit is also used for controlling the third switch and the fourth switch to be switched on or switched off.

Technical Field

The application relates to the technical field of circuits, in particular to a starting circuit and an oscillating circuit.

Background

The crystal oscillator circuit has the characteristics of good stability and small change along with external influences such as temperature, voltage and the like, is widely applied to various circuit systems, is generally used as an accurate clock source, can provide a calibration source for an RC (resistor-capacitor) clock circuit in an integrated circuit system, can also be used as a reference source of a radio frequency system, and is an essential timing module in systems such as Bluetooth, 5G and the like.

The crystal oscillator circuit requires an off-chip crystal (crystal) device, the oscillation frequency of which is determined by the resonant frequency of the crystal. In a traditional crystal oscillator circuit, a crystal is driven by a large inverter, the voltage amplitude of two ends of the crystal is slowly changed and gradually increased when the circuit works, and the crystal oscillator circuit starts oscillation and sometimes outputs clock when the amplitude exceeds a certain range. When the voltage amplitude of the two ends of the crystal is further increased, the frequency of the crystal oscillator circuit is gradually stabilized, and the larger the amplitude of the crystal is, the more the phase noise of the output clock is reduced.

A common problem of crystal oscillator circuits is that the circuit starts oscillating too slowly, and for example, 32M crystal oscillator circuits, conventional crystal oscillator circuits usually take hundreds of us or even ms from turn-on to clock output, which undoubtedly increases the overall power consumption of the integrated circuit system. There are some crystal oscillator circuits with fast start-up, which usually achieve the start-up acceleration by increasing the driving of the output MOS transistor of the crystal oscillator circuit, but this will greatly increase the overall power consumption.

Disclosure of Invention

An object of the embodiments of the present application is to provide a start-up circuit and an oscillating circuit, so as to provide a clock signal varying according to a preset frequency through the start-up circuit, so as to accelerate start-up of the oscillating circuit.

A first aspect of an embodiment of the present application provides a starting circuit, including: a control circuit for generating a first control signal; the generating circuit is connected with the control circuit and used for generating a changed reference signal according to the first control signal; and the comparison circuit is used for comparing the reference signal with the comparison signal and outputting a clock signal which changes according to a preset frequency.

In one embodiment, the generating circuit includes: the first resistor is connected with a first switch in series, and the first switch is used for controlling the electrifying state of the first resistor; and the tuning capacitor is connected with the first resistor, and is connected with a second switch in parallel, and the second switch is used for controlling the power-on state of the tuning capacitor.

In an embodiment, the control circuit is connected to the first switch, and the first control signal is used to control the first switch to be opened or closed.

In one embodiment, the method further comprises: and the input end of the second inverter is connected with the control circuit, the output end of the second inverter is connected with the second switch, and a second control signal output by the second inverter is used for controlling the opening or closing of the second switch.

In one embodiment, when the first switch is closed and the second switch is open, the generating circuit formed by the first resistor and the tuning capacitor generates the varying reference signal.

In one embodiment, the first resistor is an adjustable first resistor; the tuning capacitor is an adjustable capacitor.

In one embodiment, the method further comprises: and the input end of the third phase inverter is connected with the generating circuit, and the output end of the third phase inverter is connected with the control circuit.

In one embodiment, the comparison circuit includes: the output end of the generating circuit is connected with the reverse input end of the first comparator, and the forward input end of the first comparator is connected with a first comparison signal; the output end of the generating circuit is connected with the reverse input end of the second comparator, and the forward input end of the second comparator is connected with a second comparison signal; and when the first comparator and the second comparator work alternately, a clock signal which changes according to the preset frequency is generated.

In one embodiment, the comparison circuit further includes: and the first signal source is connected with the positive input end of the first comparator and used for generating the first comparison signal.

In one embodiment, the comparison circuit further includes: and the second signal source is connected with the positive input end of the second comparator and is used for generating the second comparison signal.

In one embodiment, the comparison circuit further includes: the input end of the trigger is respectively connected with the output end of the first comparator and the output end of the second comparator; the output end of the trigger is connected with the first signal source, and the first clock signal output by the trigger is used for controlling the opening or closing of the first signal source.

In one embodiment, the first signal source includes: the first current source is connected with the output end of the trigger; and one end of the first capacitor is connected with the first current source, and the other end of the first capacitor is grounded.

In one embodiment, the comparison circuit further includes: the input end of the first phase inverter is connected with the output end of the trigger, the output end of the first phase inverter is connected with the second signal source, and a second clock signal output by the first phase inverter is used for controlling the opening or closing of the second signal source.

In one embodiment, the second signal source includes: the second current source is connected with the output end of the trigger; and one end of the second capacitor is connected with the second current source, and the other end of the second capacitor is grounded.

A second aspect of the embodiments of the present application provides an oscillation circuit, including: the start-up circuit according to the first aspect of the embodiments of the present application and any embodiments thereof; and the crystal oscillator circuit is connected with the output end of the comparison circuit of the starting circuit and is used for accessing a clock signal which changes according to the preset frequency, and the preset frequency is the resonance frequency of the crystal oscillator circuit.

In one embodiment, the method further comprises: and the third switch and the fourth switch are respectively connected with the control circuit and the crystal oscillator circuit, and the first control signal output by the control circuit is also used for controlling the third switch and the fourth switch to be switched on or switched off. The method is used for executing the first aspect and any embodiment of the first aspect to identify the flow information of the document information.

The application provides a starting circuit and oscillating circuit, generate first control signal through control circuit, the generating circuit generates the reference signal of change according to first control signal, comparison circuit carries out the output result after comparing reference signal and the comparative signal of access afterwards, comparison circuit's output result is according to predetermineeing frequency variation, forms clock signal, this clock signal input oscillating circuit can make oscillating circuit start fast, reduces oscillating circuit's start-up consumption.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of an oscillation circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a start-up circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a start-up circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram illustrating timing variations of a reference signal and a first clock signal according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a variation of a frequency of an output clock signal of a start-up circuit according to an embodiment of the present disclosure;

fig. 6 is a signal waveform diagram of a key node according to an embodiment of the present application.

Reference numerals:

1-oscillating circuit, 10-starting circuit, 11-starting module, 111-generating circuit, 112-comparing circuit, 12-controlling circuit, 20-crystal oscillator circuit, T0-inverter, R0-resistor, J0 crystal, S1-third switch, S2-fourth switch, R1-first resistor, K1-first switch, C-tuning capacitor, K2-second switch, Q1-first comparator, Q2-second comparator, 31-first signal source, a 1-first current source, C1-first capacitor, 32-second signal source, a 2-second current source, C2-second capacitor, Q3-flip-flop, T1-first inverter, T2-second inverter, T3-third inverter, first control signal standing _ up _ en, the second control signal startup _ enb, the first clock signal clk0, the second clock signal clk0_ b, the reference signal Vref, the feedback signal flag, f 0-the resonant frequency of the crystal.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, the terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, the present embodiment provides an oscillation circuit 1 including: the start-up circuit 10, the crystal oscillator circuit 20, the third switch S1 and the fourth switch S2, wherein:

the start-up circuit 10 comprises a start-up module 11 and a control circuit 12, the control circuit 12 controls the start-up module 11 to generate a first clock signal clk0 and a second clock signal clk0_ b by a first control signal startup _ en and a second control signal startup _ enb. The start module 11 generates a feedback signal flag to be input to the digital control circuit 12, and the feedback signal flag can be used for turning on and off the digital control circuit 12.

The crystal oscillation circuit 20 includes: and the crystal J0, the resistor R0 and the inverter T0 are connected in parallel, wherein the crystal J0, the resistor R0 and the input end of the inverter T0 are connected with a node XI, and the crystal J0, the resistor R0 and the output end of the inverter T0 are connected with a node XO. The crystal oscillator circuit 20 is connected to the start-up circuit 10 through the third switch S1 and the fourth switch S2, and in the fast start-up phase of the crystal oscillator circuit 20, the third switch S1 and the fourth switch are turned on, and the first clock signal clk0 and the second clock signal clk0_ b of the start-up module 11 are applied to two ends of the crystal J0, so that the current amplitude in the crystal J0 is increased fast, and the start-up process of the crystal oscillator circuit 20 is accelerated.

In an embodiment, the crystal oscillator circuit 20 is connected to the output terminal of the comparison circuit 112 of the start circuit 10, and is configured to receive a clock signal varying according to a predetermined frequency, where the predetermined frequency is a resonant frequency f0 of a crystal J0 in the crystal oscillator circuit 20.

In an embodiment, the third switch S1 and the fourth switch S2 are respectively connected to the control circuit 12, and the first control signal startup _ en output by the control circuit 12 can also be used to control the third switch S1 and the fourth switch S2 to open or close.

As shown in fig. 2, the present embodiment provides a starting circuit 10, which can be used in the oscillation circuit 1 shown in fig. 1, so as to accelerate the starting of the crystal oscillator circuit 20 in the oscillation circuit 1. The start-up circuit 10 includes: a control circuit 12 and a start-up module 11, wherein the start-up module 11 may comprise a generation circuit 111 and a comparison circuit 112.

The control circuit 12, which may be implemented by a digital controller, is used to generate the first control signal startup en. The generating circuit 111 is connected to the control circuit 12 for generating a varying reference signal vref in dependence on the first control signal startup en. The inverting input terminal of the comparing circuit 112 is connected to the generating circuit 111, the non-inverting input terminal is connected to the comparison signal, and the comparing circuit 112 is configured to compare the reference signal vref with the comparison signal and output a clock signal varying according to a preset frequency.

In an embodiment, the starting module 11 may be a common clock circuit, a ring oscillator clock circuit formed by an inverter chain, or a commonly used RC (resistor-capacitor) charging and discharging clock circuit, and these clock circuits may operate fast to output a clock signal.

In an embodiment, as shown in fig. 3, the present embodiment provides a starting circuit 10, which can be used in the oscillating circuit 1 shown in fig. 1, so as to accelerate the starting of the crystal oscillator circuit 20 in the oscillating circuit 1. The RC clock circuit is taken as an example of the start module 11 for detailed description. The generation circuit 111 includes: the circuit comprises a first resistor R1, a first switch K1, a tuning capacitor C and a second switch K2, wherein the first resistor R1 is connected with the first switch K1 in series, and the first switch K1 is used for controlling the electrifying state of the first resistor R1. The tuning capacitor C is connected with the first resistor R1, one end of the second switch K2 is connected with the connection point of the first resistor R1 and the tuning capacitor C, the other end of the second switch K2 is grounded, and the second switch K2 is used for controlling the electrifying state of the tuning capacitor C.

In an embodiment, the control circuit 12 is connected to the first switch K1, and the first control signal startup _ en generated by the control circuit 12 may be used to control the opening or closing of the first switch K1, for example, when the first control signal startup _ en is at a high level, the first switch K1 is controlled to be closed.

In one embodiment, the method further comprises: an input end of the second inverter T2, an input end of the second inverter T2 is connected to the control circuit 12, an output end of the second inverter T2 is connected to the second switch K2, and after the first control signal startup _ en is input to the second inverter T2, the second inverter T2 may output a second control signal startup _ enb, and the second control signal startup _ enb may be used to control the second switch K2 to be turned on or off.

In one embodiment, when the first control signal startup _ en is high, the first switch K1 is controlled to be closed, and when the second control signal startup _ enb is low, the second switch K2 may be controlled to be opened, so that the generating circuit 111 starts to operate, and the reference signal vref is generated at the connection point of the first resistor R1 and the tuning capacitor C. It can be seen that the reference signal vref is a varying reference level.

In one embodiment, the comparison circuit 112 includes: and in the two-way comparator, the output end of the generating circuit 111 is connected with the inverting input end of the first comparator Q1, and the inverting input end of the first comparator Q1 is connected with the first comparison signal. The output end of the generating circuit 111 is connected with the inverting input end of the second comparator Q2, and the inverting input end of the second comparator Q2 is connected with the second comparison signal. When the first comparator Q1 and the second comparator Q2 alternately operate, a clock signal varying at a preset frequency is generated.

In one embodiment, the comparison circuit 112 further includes: the first signal source 31 is connected to the positive input terminal of the first comparator Q1, and is configured to generate a first comparison signal.

In one embodiment, the first signal source 31 may be composed of a first current source a1 and a first capacitor C1, the first current source a1 is connected to the positive input terminal of the first comparator Q1, one end of the first capacitor C1 is connected to the connection point of the first current source a1 to the first comparator Q1, and the other end is grounded. The first current source a1 may generate a first comparison signal.

In one embodiment, the comparison circuit 112 further includes: the second signal source 32 is connected to the positive input terminal of the second comparator Q2 for generating a second comparison signal.

In an embodiment, the second signal source 32 is composed of a second current source a2 and a second capacitor C2, the second current source a2 is connected to the positive input terminal of the second comparator Q2, one end of the second capacitor C2 is connected to the second current source a2, and the other end is grounded. The second current source a2 may generate a second comparison signal.

In one embodiment, the comparison circuit 112 further includes: and the input ends of the flip-flop Q3 and the flip-flop Q3 are respectively connected with the output end of the first comparator Q1 and the output end of the second comparator Q2. Wherein the flip-flop Q3 may be an SRQ flip-flop Q3, the output of the first comparator Q1 may be connected to the input S of the flip-flop Q3, and the output of the second comparator Q2 may be connected to the input R of the flip-flop Q3.

In one embodiment, the output terminal Q of the flip-flop Q3 is connected to the first signal source 31, and the first clock signal clk0 output by the flip-flop Q3 can be used to control the opening or closing of the first signal source 31. For example, when the first clock signal clk0 is high, the first current source a1 is controlled to be turned on, so that the first signal source 31 generates the first comparison signal.

In one embodiment, the comparison circuit 112 further includes: an input end of the first inverter T1 and an input end of the first inverter T1 are connected to an output end Q of the flip-flop Q3, after a first clock signal clk0 output by the flip-flop Q3 passes through the first inverter T1, the first inverter T1 outputs a second clock signal clk0_ b, an output end of the first inverter T1 is connected to the second signal source 32, and the second clock signal clk0_ b is used for controlling the second signal source 32 to be opened or closed. For example, when the second clock signal clk0_ b is at a high level, the second signal source 32 is controlled to be turned on, so that the second signal source 32 generates the second reference signal vref. This also enables the first comparator Q1 and the second comparator Q2 to operate alternately.

In one embodiment, as shown in fig. 4, a timing diagram of the reference signal vref and the first clock signal clk0 shows, when the first switch K1 is closed and the second switch K2 is opened, the generating circuit 111 generates the reference signal vref, when the level of the reference signal vref is low, the frequency of the output first clock signal clk0 is high, and when the reference signal vref gradually rises, the frequency of the output first clock signal clk0 gradually decreases.

In an embodiment, during the fast start-up phase of the crystal oscillator circuit 20, the first clock signal clk0 is connected to the XI terminal of the crystal J0, and the second clock signal clk0_ b is connected to the XO terminal of the crystal J0, that is, there is a clock frequency with a frequency change at both ends of the crystal J0, when the clock frequency of the change becomes the resonant frequency f0 of the crystal J0, the amplitude of the current ixo on the crystal J0 changes abruptly, which will greatly increase the oscillation start-up time of the crystal oscillator. In order to ensure that the clock frequency of the chip of the start-up circuit 10 can sweep the resonant frequency f0 of the crystal J0 under all conditions, it is necessary to reasonably take the maximum value fmax and the minimum value fmin of the clock frequency output by the start-up circuit 10, wherein the maximum value fmax can be 2 times of the resonant frequency f0 of the crystal J0, and the minimum value fmin can be 0.1 f 0.

In one embodiment, the first resistor R1 is an adjustable first resistor R1. The tuning capacitor C is a tunable capacitor. As shown in fig. 5, by adjusting the values of the first resistor R1 and the tuning capacitor C, the slope of the frequency change of the first clock signal clk0 during the fast start phase can be changed, and the smaller the slope, the larger the amplitude of the jump of the current ixo at the resonant frequency f 0. Under the condition of the fixed maximum value fmax and the minimum value fmin, the smaller the frequency change slope of the first clock signal clk0, the slower the whole scanning process, and in practical application, the frequency change slope can be selected according to the actual condition of the circuit.

In one embodiment, the method further comprises: in the third inverter T3, the input terminal of the third inverter T3 is connected to the connection point of the first resistor R1 and the tuning capacitor C in the generating circuit 111, and the output terminal of the third inverter T3 is connected to the control circuit 12. After the reference signal vref generated by the generating circuit 111 passes through the third inverter T3, the third inverter T3 outputs a feedback signal flag, which can make the first control signal startup _ en output by the control circuit 12 become low level. The third inverter T3 is a hysteretic inverter.

In one embodiment, as shown in fig. 6, a timing diagram of the change of the first control signal startup _ en, the reference signal vref, the feedback signal flag, the first clock signal clk0 at the frequency of the node XO and the signal waveform at the node XI in fig. 3 is provided. After the first control signal startup _ en goes high, the reference signal vref node of the generating circuit 111 starts to charge, the level thereof gradually rises, and the frequency of the output first clock signal clk0 changes from high to low with the change of the reference signal vref. In a stage where the first control signal startup _ en is high, the first clock signal clk0 and the second clock signal clk0_ b are directly connected to two ends of the crystal J0, so that the level of the crystal J0 at the XI end is the first clock signal clk0 when the first control signal startup _ en is equal to 1.

In an embodiment, during the operation of the start-up circuit 10, the reference signal vref may be provided to the third inverter T3 to obtain the feedback signal flag, and the up-down threshold of the third inverter T3 is lower than the down-down threshold. In the initial stage of the fast start, the reference signal is at a high level, and the feedback signal flag becomes a low level when the reference signal vref gradually rises and exceeds the down-turn threshold of the third inverter T3. The feedback signal flag is then fed to the control circuit 12, and the control circuit 12 delays the time period after which the first control signal startup _ en is turned low after the reference signal vref is turned low, indicating that the fast start-up procedure is completed. Crystal J0 is then driven into operation by crystal oscillator circuit 20, and the signal at node XI oscillates around the dc operating point and gradually increases in amplitude. Since the current ixo of the crystal J0 has abrupt change in the fast start phase, the voltage amplitude of the crystal J0 is larger than that of the normal crystal oscillator circuit 20 during start-up after the fast start phase. Taking a 32M circuit as an example, the start-up time of the crystal oscillator circuit 20 can be shortened from 1ms to 200us after the start-up circuit 10 of the present embodiment is adopted.

In one embodiment, after the start-up is completed, the start-up circuit 10 may be turned off, and the power consumption of the start-up circuit 10 will not be generated. The power consumption of the start-up circuit 10 is typically in the tens of uA, which is negligible compared to the hundreds of uA for the crystal oscillator circuit 20 to operate. However, the start-up circuit 10 of the present embodiment can shorten the crystal oscillation stabilizing time, reduce the overall power consumption, and increase the corresponding speed of the circuit.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.