阅读说明：本技术 时钟分数分频器模块、图像和/或视频处理模块及设备 (Clock fractional divider module, image and/or video processing module and apparatus ) 是由 C·艾谢纳 D·皮埃尔恩蒂利 D·库佩 G·蒙塔尔巴诺 于 2020-04-03 设计创作，主要内容包括：本发明涉及一种时钟分数分频器模块(100),其形成为、在其中包括或集成有双核心锁步单元(10；20；30),其中,所述双核心锁步单元(10；20；30)被配置为能够实现附有误差检测、识别和/或校正装置、机制或处理的时钟分数分频装置、机制或处理。(The invention relates to a clock fractional divider module (100) formed as, including or integrated in a dual core lockstep unit (10; 20; 30), wherein the dual core lockstep unit (10; 20; 30) is configured to enable a clock fractional divider means, mechanism or process with an error detection, identification and/or correction means, mechanism or process attached thereto.)

1. A clock fractional divider module (100) in which,

-a dual core lockstep unit (10; 20; 30) is integrated in the clock fractional divider module (100),

-wherein the dual core lockstep unit (10; 20; 30) is configured to enable a clock fractional division process accompanied by an error detection, identification and/or correction process.

2. The clock fractional divider module (100) of claim 1,

-a master clock fractional divider module core unit (10) as a first component is integrated in the clock fractional divider module (100),

-wherein the master clock fractional divider module core unit (10) is particularly configured to enable a corresponding clock fractional division process.

3. The clock fractional divider module (100) of claim 2, wherein the master clock fractional divider module core unit (10) is configured to be able to generate a respective clock enable signal to gate and/or enable an input reference clock and/or generate an output clock accordingly.

4. The clock fractional divider module (100) of any one of the preceding claims,

-a checker clock fractional divider module core unit (20) as a second component is integrated in the clock fractional divider module (100),

-wherein the checker clock fractional divider module core unit (20) is particularly configured to enable a respective error detection, identification and/or correction.

5. The clock fractional divider module (100) of claim 4, wherein the checker clock fractional divider module core unit (20) is configured to be able to generate a respective clock enable signal, in particular for comparison with a respective master core clock enable signal.

6. The clock fractional divider module (100) of any one of the preceding claims,

-the clock fractional divider module (100) comprises or is integrated with a lockstep comparison unit (30) as a third component,

-wherein the respective checker clock fractional divider module core unit (20) is particularly configured to enable a respective error identification, detection and/or detection in cooperation with the lockstep comparison unit (30).

7. The clock fractional divider module (100) of claim 4, wherein the lockstep comparison unit (30) is configured to enable at least one of:

-comparing core clock enable signals of or assigned to said master clock fractional divider module core unit (10) and checker clock fractional divider module core unit (20), in particular if these enable signals are different, generating an error signal, and

-comparing enable signals as a master enable signal and a checker enable signal of the master clock fractional divider module core unit (10) and the checker clock fractional divider module core unit (20) or of the master clock fractional divider module core unit (10) and the checker clock fractional divider module core unit (20), in particular if these enable signals are different, generating an error signal,

in particular, they are all operated by means of XOR logic.

8. The clock fractional divider module (100) of any one of the preceding claims, which is realized in whole or in part, in particular one or more of its components or parts of its components, as or by at least one of software and hardware components, in particular based on one or more semiconductor modules and/or ASICs.

9. An image and/or video processing module (1), the image and/or video processing module (1) comprising: the clock fractional divider module (100) according to any of the preceding claims, functionally and/or physically connected to the image and/or video processing module (1).

10. A device comprising an image and/or video processing module (1) according to claim 9, wherein the device is particularly formed as a vehicle.