阅读说明：本技术 一种磁性隧道结存储阵列单元及其***电路的制备方法 (Preparation method of magnetic tunnel junction storage array unit and peripheral circuit thereof ) 是由 张云森 郭一民 陈峻 肖荣福 于 2019-04-11 设计创作，主要内容包括：本发明一种磁性隧道结存储阵列单元及其外围电路的制备方法,在存储阵列单元区域,采用在金属连线M<Sub>x</Sub>之上,依次制作磁性隧道结底电极、磁性隧道结和磁性隧道结顶电极,磁性隧道结底电极、磁性隧道结和磁性隧道结顶电极依次对齐；在外围电路单元区域,采用在金属连线M<Sub>x</Sub>之上,依次制作可电学导通的赝磁性隧道结底电极、可低电阻导通的赝磁性隧道结和赝磁性隧道结顶电极,并且赝磁性隧道结底电极、赝磁性隧道结、赝磁性隧道结顶电极依次对齐；在存储阵列单元区域的磁性隧道结顶电极和外围电路单元区域的赝磁性隧道结顶电极之上制作一层金属连线M<Sub>x+1</Sub>以在外围电路单元区域和存储阵列单元区域分别实现从金属连线M<Sub>x</Sub>到M<Sub>x+1</Sub>之间的有效连接。(The invention relates to a magnetic tunnel junction storage array unit and a preparation method of a peripheral circuit thereof x Sequentially manufacturing a magnetic tunnel junction bottom electrode, a magnetic tunnel junction and a magnetic tunnel junction top electrode, wherein the magnetic tunnel junction bottom electrode, the magnetic tunnel junction and the magnetic tunnel junction top electrode are sequentially aligned; in the peripheral circuit unit region, the metal connection line M is adopted x Sequentially manufacturing a pseudo-magnetic tunnel junction bottom electrode capable of being electrically conducted, a pseudo-magnetic tunnel junction capable of being conducted at low resistance and a pseudo-magnetic tunnel junction top electrode, and sequentially aligning the pseudo-magnetic tunnel junction bottom electrode, the pseudo-magnetic tunnel junction and the pseudo-magnetic tunnel junction top electrode; a layer of metal connecting wire M is made on the top electrode of the magnetic tunnel junction in the memory array unit region and the pseudo-magnetic tunnel junction in the peripheral circuit unit region x+1 To form a peripheral circuit unit region and a memory array unit regionDomain-by-domain slave metal link M x To M x+1 To be operatively connected therebetween.)

1. A method for preparing a magnetic tunnel junction storage array unit and a peripheral circuit thereof is characterized by comprising the following steps:

in the memory array unit area, the metal connecting line M is adopted_xSequentially manufacturing a magnetic tunnel junction bottom electrode, a magnetic tunnel junction and a magnetic tunnel junction top electrode, wherein the magnetic tunnel junction bottom electrode, the magnetic tunnel junction and the magnetic tunnel junction top electrode are sequentially aligned, and x is more than or equal to 1;

in the peripheral circuit unit region, the metal connection line M is adopted_xSequentially manufacturing a pseudo-magnetic tunnel junction bottom electrode capable of being electrically conducted, a pseudo-magnetic tunnel junction capable of being conducted at low resistance and a pseudo-magnetic tunnel junction top electrode, and sequentially aligning the pseudo-magnetic tunnel junction bottom electrode, the pseudo-magnetic tunnel junction and the pseudo-magnetic tunnel junction top electrode;

finally, a layer of metal connecting wire M is manufactured on the top electrode of the magnetic tunnel junction in the memory array unit region and the pseudo magnetic tunnel junction in the peripheral circuit unit region_x+1To realize the slave metal connection M in the peripheral circuit unit region and the memory array unit region respectively_xTo the metal line M_x+1To be operatively connected therebetween.

2. The method of claim 1, further comprising the steps of:

the method comprises the following steps: metal-carrying wire M providing surface finish_xThe left part area of the CMOS substrate is a storage array unit area, and the right part area of the CMOS substrate is a peripheral circuit unit area;

step two: depositing a layer of metal layer on the metal connecting line M before the deposition of the magnetic tunnel junction bottom electrode_xOn the above, the pseudo magnetic tunnel with rough surface is defined by imaging the metal area before deposition of bottom electrode of pseudo magnetic tunnel junction with rough surface, and the pseudo magnetic tunnel with rough surface is made on the metal layer before deposition of bottom electrode of magnetic tunnel junction with peripheral circuit unit area by etchingMetal before bottom electrode deposition is removed, a mask is removed, and a planarization process is adopted to grind the metal layer before bottom electrode deposition of the magnetic tunnel in the memory array unit area so as to meet the requirement of manufacturing a magnetic tunnel junction and ensure that the metal layer has lower flatness under the pseudo magnetic tunnel bottom electrode in the peripheral circuit unit area;

step three: sequentially depositing a magnetic tunnel junction bottom electrode film layer, a magnetic tunnel junction multilayer film and a magnetic tunnel junction top electrode film layer on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the memory array unit region, and simultaneously sequentially depositing a pseudo magnetic tunnel junction bottom electrode film layer, a pseudo magnetic tunnel junction multilayer film and a pseudo magnetic tunnel junction top electrode film layer on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the peripheral circuit unit region;

or, a magnetic tunnel junction bottom electrode film layer, a magnetic tunnel junction multilayer film, a magnetic tunnel junction top electrode film layer and a sacrificial mask layer are sequentially deposited on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the memory array unit region, and a pseudo-magnetic tunnel junction bottom electrode film layer, a pseudo-magnetic tunnel junction multilayer film, a pseudo-magnetic tunnel junction top electrode film layer and a sacrificial mask layer are sequentially deposited on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the peripheral circuit unit region;

step four: defining a magnetic tunnel junction and a pseudo-magnetic tunnel junction in a graphical mode, simultaneously etching the top electrode of the magnetic tunnel junction, the top electrode of the pseudo-magnetic tunnel junction and the pseudo-magnetic tunnel junction, and stopping etching on the corresponding bottom electrode;

step five: manufacturing an etched magnetic tunnel junction bottom electrode and metal before deposition thereof, a pseudo magnetic tunnel junction bottom electrode and a metal side wall self-alignment mask before deposition thereof;

step six: etching the magnetic tunnel junction bottom electrode and the metal before deposition thereof, and the pseudo-magnetic tunnel junction bottom electrode and the metal before deposition thereof by taking the side wall self-alignment mask as a hard mask;

step seven: depositing a magnetic tunnel junction/pseudo-magnetic tunnel junction filling medium, and flattening by adopting chemical machinery until a magnetic tunnel junction top electrode/pseudo-magnetic tunnel junction top electrode is formed;

step eight: depositing metal connecting line M_x+1Interlayer dielectric and metal interconnection M_x+1。

3. The method of claim 2, wherein the total thickness of the metal layer before the deposition of the bottom electrode of the magnetic tunnel junction is 5nm to 50nm, and the material of the metal layer is Ti, TiN, W, WN, Ta, TaN, Ru or any combination thereof.

4. The method of claim 2, wherein the magnetic tunnel junction bottom electrode film or the pseudo-magnetic tunnel junction bottom electrode film is Ta, TaN, Ti, TiN, W, WN, Ru or any combination thereof, has a thickness of 5 nm-80 nm, and can be implemented by CVD, PVD, ALD or ion beam deposition;

the total thickness of the magnetic tunnel junction multilayer film or the pseudo-magnetic tunnel junction multilayer film is 8 nm-40 nm, and the bottom pinning structure is formed by sequentially and upwardly superposing a reference layer, a barrier layer and a memory layer or the top pinning structure is formed by sequentially and upwardly superposing a memory layer, a barrier layer and a reference layer;

the thickness of the magnetic tunnel junction top electrode film layer or the pseudo-magnetic tunnel junction top electrode film layer is 20 nm-100 nm, and Ta, TaN, Ti, TiN, W, WN or any combination of the Ta, the TaN, the Ti, the TiN, the W and the WN are selected.

5. The method of claim 2, wherein Cl is used to prepare the magnetic tunnel junction memory array cell and its peripheral circuit₂Or CF₄Etching the magnetic tunnel junction top electrode/pseudo-magnetic tunnel junction top electrode by a reactive ion etching process which is mainly used for etching gas, and removing residual polymer by adopting a dry process and/or a wet process so as to transfer the pattern to the top of the magnetic tunnel junction/pseudo-magnetic tunnel junction;

etching the magnetic tunnel junction and the pseudo-magnetic tunnel junction simultaneously by adopting a reactive ion etching and/or ion beam etching method;

wherein, the ion beam etching mainly adopts Ar, Kr or Xe and the like as an ion source; the reactive ion etching mainly adopts CH₃OH、CH₄/Ar、C₂H₅OH、CH₃OH/Ar or CO/NH₃Etc. as the main etching gas.

6. The method as claimed in claim 2, wherein the sidewall self-aligned mask is formed by n deposition>Etching of]The process is realized, wherein n is more than or equal to 1, and the size of n is selected to ensure that the critical dimension of the self-aligned mask containing the side wall is more than M_xThe critical dimension of (2).

7. The method of claim 2, wherein the self-aligned mask deposition process is selected from CVD, PVD, ALD or IBD, and process parameters are strictly controlled such that the sidewall film conformally covers the periphery of the magnetic tunnel junction and its top electrode and the pseudo-magnetic tunnel junction and its top electrode, the top of the magnetic tunnel junction top electrode and the pseudo-magnetic tunnel junction top electrode, and the etch front of the magnetic tunnel junction bottom electrode and the pseudo-magnetic tunnel junction bottom electrode;

the first deposited material is typically selected from SiN, SiC or SiCN, and the 2 nd through nth deposited materials are typically selected from SiO2, SiON, SiN, SiC, SiCN or low dielectric constant dielectrics, and the like.

8. The method of claim 2, wherein the etching process generally uses RIE process with etching gas generally C₄F₈、C₃F₆、C₄F₆、C₂F₆、SF₆、NF₃、CF₄、CHF₃、CH₂F₂、CH₃F、O₂、N₂、NH₃、He、Ar、CO、CO₂Or CH₄；

Controlling technological parameters, particularly controlling the power and bias voltage of a radio frequency power supply for ion bombardment, so that the deposition on the side wall is hardly etched, and the deposition at the etching front end of the bottom electrode is completely etched;

after the last etch, the residue may optionally be removed using dry and/or wet processes.

9. The method of claim 2 wherein the common material of the MTJ/pseudoMTJ fill dielectric is SiO₂SiON or low dielectric constant dielectrics, typically by CVD.

10. The method of claim 2, wherein the metal line M is a metal line_x+1The interlayer dielectric is typically SiO₂SiON or a low dielectric constant dielectric and depositing an etch stop layer prior to depositing the bit line interlayer dielectric;

metal connecting wire M_x+1The composition material is metal Cu, and Ti/TiN or TaN/Ta is added to serve as a diffusion barrier layer.

Technical Field

The present invention relates to the field of Magnetic Random Access Memory (MRAM) manufacturing technology, and in particular, to a Magnetic Random Access Memory (MRAM) Magnetic Tunnel Junction (MTJ) Memory Array Unit and a method for manufacturing a peripheral circuit thereof.

Background

In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer in between; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.

In order to be able to record information in such a magnetoresistive element, a writing method based on Spin momentum Transfer (STT) switching technology has been proposed, and such an MRAM is called STT-MRAM. STT-MRAM is further classified into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM), which have better performance depending on the direction of magnetic polarization. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying a spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current to be injected for writing or switching operation. Therefore, this writing method can achieve both device miniaturization and current reduction.

Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, because the required switching current is reduced when the size of the MTJ element is reduced. It is therefore desirable to make the pSTT-MRAM device extremely small in size, with very good uniformity, and with minimal impact on the MTJ magnetic properties, by a fabrication method that also achieves high yield, high accuracy, high reliability, low power consumption, and maintains a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ device may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may fluctuate greatly, which may impair the performance of MRAM.

In the current MRAM manufacturing process, a Magnetic Tunnel Junction (MTJ) array cell is generally formed, specifically including: the Bottom Electrode through hole (BEV), the Bottom Electrode (BE), the Magnetic Tunnel Junction (MTJ), the Top Electrode (Top Electrode, TE) and the Top Electrode through hole (Top Electrode Via, TEV) are arranged between Mx (x is more than or equal to 1) and Mx +2(x is more than or equal to 1). With this connection method, since three photolithography processes are required, a series of problems due to inaccurate alignment of the photomask must be generated, which is very disadvantageous for reducing the production cost and miniaturizing the device.

Disclosure of Invention

The invention provides a magnetic tunnel junction storage array unit and a preparation method of a peripheral circuit thereof, aiming at the problems and the defects in the prior art.

The invention solves the technical problems through the following technical scheme:

the invention provides a preparation method of a magnetic tunnel junction storage array unit and a peripheral circuit thereof, which is characterized by comprising the following steps:

in the memory array unit area, the metal connecting line M is adopted_xSequentially manufacturing a magnetic tunnel junction bottom electrode, a magnetic tunnel junction and a magnetic tunnel junction top electrode, wherein the magnetic tunnel junction bottom electrode, the magnetic tunnel junction and the magnetic tunnel junction top electrode are sequentially aligned, and x is more than or equal to 1;

in the peripheral circuit unit region, the metal connection line M is adopted_xSequentially manufacturing a pseudo-magnetic tunnel junction bottom electrode capable of being electrically conducted, a pseudo-magnetic tunnel junction capable of being conducted at low resistance and a pseudo-magnetic tunnel junction top electrode, and sequentially aligning the pseudo-magnetic tunnel junction bottom electrode, the pseudo-magnetic tunnel junction and the pseudo-magnetic tunnel junction top electrode;

finally, a layer of metal connecting wire M is manufactured on the top electrode of the magnetic tunnel junction in the memory array unit region and the pseudo magnetic tunnel junction in the peripheral circuit unit region_x+1To realize the secondary metal wiring in the peripheral circuit unit region and the memory array unit region respectivelyM_xTo the metal line M_x+1To be operatively connected therebetween.

On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.

The positive progress effects of the invention are as follows:

because the invention does not need to manufacture BEV and TEV, two photomasks are reduced, thereby avoiding a plurality of problems caused by photoetching alignment, reducing the complexity of the process and being beneficial to reducing the production cost.

Furthermore, in the peripheral circuit Unit (peripheral Unit) region, a pseudo magnetic tunnel junction (Dummy-MTJ) capable of being directly conducted is manufactured, so that a through hole (VIA) for realizing Mx to Mx +1 is prevented from being manufactured after the Magnetic Tunnel Junction (MTJ) array Unit is manufactured, and the production cost can be further reduced.

Meanwhile, after the Magnetic Tunnel Junction (MTJ) unit and the pseudo-magnetic tunnel (Dummy-MTJ) unit are etched, a side wall process is adopted to increase the Critical Dimension (CD) of a bottom electrode etching self-alignment mask so as to prevent some problems caused by Cu exposure when the magnetic tunnel junction bottom electrode (MTJ BE) and the pseudo-magnetic tunnel junction bottom electrode (Dummy-MTJ BE) are etched, and the improvement of the electricity, magnetism and yield of a Magnetic Random Access Memory (MRAM) is facilitated.

Drawings

FIG. 1 is a method of fabricating a magnetic tunnel junction memory array cell and its peripheral circuitry providing surface polished metal interconnects M with CMOS in accordance with the present invention_x(x ≧ 1) schematic diagram of a CMOS substrate.

Fig. 2 is a schematic diagram of a magnetic tunnel junction memory array Unit and a method for manufacturing a peripheral circuit thereof according to the present invention, before depositing pseudo magnetic tunnel junction (Dummy-MTJ) multilayer film and Bottom Electrode (BE) and Top Electrode (TE) thereof, and before surface roughening processing of Metal Layer (BE Pre-Dep Metal Layer) before bottom electrode deposition, in a peripheral circuit Unit (peripheral Unit) region.

Fig. 3 is a schematic diagram after depositing a bottom electrode (pseudo magnetic tunnel junction bottom electrode) film layer, a magnetic tunnel junction (pseudo magnetic tunnel junction) multilayer film, a top electrode (pseudo magnetic tunnel junction top electrode) film layer or a sacrificial mask on a bottom electrode Pre-deposition Metal layer (BE Pre-dep Metal) according to a method for manufacturing a magnetic tunnel junction memory array unit and a peripheral circuit thereof of the present invention.

Fig. 4 is a schematic diagram of a magnetic tunnel junction memory array unit and a method for manufacturing a peripheral circuit thereof according to the present invention, after a Magnetic Tunnel Junction (MTJ) and a pseudo-magnetic tunnel junction (Dummy-MTJ) are defined graphically, and a Top Electrode (TE), the Magnetic Tunnel Junction (MTJ)/the pseudo-magnetic tunnel junction (Dummy-MTJ) thereof are etched respectively, and the etching is stopped on a Bottom Electrode (BE).

Fig. 5-10 are schematic diagrams illustrating a method for manufacturing a magnetic tunnel junction memory array unit and its peripheral circuits according to a preferred embodiment of the present invention, after a self-aligned mask of a Magnetic Tunnel Junction Bottom Electrode (MTJBE) and a pseudo-magnetic tunnel junction bottom electrode (Dummy-MTJ BE) is prepared by a three-deposition- > etching sidewall process.

FIG. 11 is a schematic diagram of a magnetic tunnel junction memory array cell and its peripheral circuit fabrication method after etching Bottom Electrode (BE) and bottom electrode Pre-deposition Metal (BE Pre-dep Metal) according to the present invention.

Fig. 12 is a schematic diagram of a method for fabricating a magnetic tunnel junction memory array cell and its peripheral circuits according to the present invention, filled with a dielectric and planarized down to behind the top electrode.

FIG. 13 is a method for fabricating a MTJ memory array cell and its peripheral circuits according to the present invention, M_x+1Schematic after etching and metallic Cu filling.

Description of reference numerals: 200-surface polished metal connecting line M_x(x is more than or equal to 1) CMOS substrate, 201-metal connecting line M_x(x is not less than 1) interlayer dielectric, 2021-metal line M_x(x is more than or equal to 1) (memory array unit area), 2022-metal connecting line M_x(x.gtoreq.1) (peripheral circuit region), 310-bottom electrode Pre-deposition Metal Layer (BE Pre-dep Metal Layer), 311-magnetic Tunnel junction bottom electrode Pre-deposition Metal (MTJ BE Pre-dep Metal), 320-pseudo-magnetic Tunnel junction (Dummy-MT)J) Cell region, surface roughness region mask, 330-pseudomagnetic tunnel junction (Dummy-MTJ) cell region, surface roughness region opening, 340-surface roughness pseudomagnetic tunnel junction bottom electrode pre-deposition metal, 410-Bottom Electrode (BE) (pseudomagnetic tunnel junction bottom electrode Dummy-MTJBE) film layer, 411-magnetic tunnel junction bottom electrode (MTJ BE) (memory array cell region), 412-pseudomagnetic tunnel junction bottom electrode (Dummy-MTJ) (peripheral circuit cell region), 420-Magnetic Tunnel Junction (MTJ) (pseudomagnetic tunnel junction Dummy-MTJ) multilayer film, 4201-smooth magnetic tunnel junction barrier layer, 4202-surface roughness magnetic tunnel junction barrier layer in pseudomagnetic tunnel junction (Dummy-MTJ) cell region, 421-magnetic tunnel junction cell (MTJ) (memory array cell region), 422-pseudo magnetic tunnel junction (Dummy-MTJ) (peripheral circuit unit region), 430-Top Electrode (TE) (pseudo magnetic tunnel junction top electrode Dummy-MTJ TE) film layer, 431-magnetic tunnel junction top electrode (MTJ TE), 432-pseudo magnetic tunnel junction top electrode (Dummy-MTJTE), 440-sacrificial mask, 441-residual sacrificial mask (memory array unit region), 442-residual sacrificial mask (peripheral circuit unit region), 451-first layer sidewall spacer (memory array unit region), 452-second layer sidewall spacer (peripheral circuit unit region), 461-second layer sidewall spacer (memory array unit region), 462-second layer sidewall spacer (peripheral circuit unit region), 471-third layer sidewall spacer (memory array unit region), 472-third layer sidewall spacer (peripheral circuit unit region), 480-Magnetic Tunnel Junction (MTJ)/pseudo-magnetic tunnel junction (Dummy-MTJ) filled dielectric, 510-metal line M_x+1Interlevel dielectric, 511-metal interconnect M_x+1(memory array cell area) and 512-metal line M_x+1(peripheral circuit unit region).

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

The invention provides a method for preparing a magnetic tunnel junction storage array unit of a magnetic random access memory and a peripheral circuit thereof, which is provided between two layers of Cu metal, namely: m_x(x.gtoreq.1) and M_x+1(x is more than or equal to 1), the manufacturing process and the alignment mode of the magnetic random access Memory Array Unit (Memory Array Unit) and the peripheral circuit (peripheral Unit) thereof are carried out.

In the Memory Array Unit (Memory Array Unit) region, the metal connection line M is adopted_xAnd (x is more than or equal to 1), sequentially manufacturing a magnetic tunnel junction bottom electrode (MTJ BE), a Magnetic Tunnel Junction (MTJ) and a magnetic tunnel junction top electrode (MTJ TE), and sequentially aligning the MTJBE, the MTJ and the MTJ TE.

In the peripheral circuit Unit (peripheral Unit) region, the metal connection line M is adopted_xAnd sequentially manufacturing a pseudomagnetic tunnel junction bottom electrode (Dummy-MTJ BE) capable of being electrically conducted, a pseudomagnetic tunnel junction (Dummy-MTJ) capable of being conducted with low resistance and a pseudomagnetic tunnel junction top electrode, and sequentially aligning the Dummy-MTJ BE, the Dummy-MTJ and the Dummy-MTJ TE.

Finally, a layer of metal connecting line M is manufactured on the Top Electrode (TE) of the Memory Array Unit (Memory Array Unit) area and the pseudo-magnetic tunnel junction top electrode (Dummy-MTJ TE) of the peripheral circuit Unit (peripheral Unit) area_x+1(x is more than or equal to 1), and the slave metal connecting wire M is respectively realized in the peripheral circuit unit area and the memory array unit area of the magnetic random access memory_xTo the metal line M_x+1To be operatively connected therebetween.

Because the invention does not need to manufacture BEV and TEV, two photomasks are reduced, thereby avoiding a plurality of problems caused by photoetching alignment, reducing the complexity of the process and being beneficial to reducing the production cost.

Furthermore, in the peripheral circuit Unit (peripheral Unit) region, a pseudo magnetic tunnel junction (Dummy-MTJ) capable of being directly conducted is manufactured, so that a through hole (VIA) for realizing Mx to Mx +1 is prevented from being manufactured after the Magnetic Tunnel Junction (MTJ) array Unit is manufactured, and the production cost can be further reduced.

Meanwhile, after the Magnetic Tunnel Junction (MTJ) unit and the pseudo-magnetic tunnel (Dummy-MTJ) unit are etched, a side wall process is adopted to increase the Critical Dimension (CD) of a bottom electrode etching self-alignment mask so as to prevent some problems caused by Cu exposure when the magnetic tunnel junction bottom electrode (MTJ BE) and the pseudo-magnetic tunnel junction bottom electrode (Dummy-MTJ BE) are etched, and the improvement of the electricity, magnetism and yield of a Magnetic Random Access Memory (MRAM) is facilitated.

The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memories (MRAMs), and is not limited to any process sequence or flow, as long as the resulting product or device is prepared by the same or similar method as that prepared by the following preferred process sequence or flow, with the following specific steps:

the method comprises the following steps: cu-bearing metal connecting wire M with polished surface_x(x ≧ 1) in the CMOS substrate 200, as shown in FIG. 1, the left area of the CMOS substrate is a memory array cell area, and the right area of the CMOS substrate is a peripheral circuit cell area.

Step two: under the pseudo magnetic tunnel junction bottom electrode (Dummy-MTJ BE)412 in the peripheral circuit Unit region (peripheral Unit), a rough surface of pseudo magnetic tunnel junction bottom electrode Pre-dep Metal (Dummy-MTJ BE Pre-dep Metal)340 is fabricated, as shown in FIG. 2.

The method comprises the following steps:

2.1: a magnetic tunnel junction bottom electrode Pre-deposition Metal layer (MTJ BE Pre-dep Metal layer)310 is deposited over Bottom Electrode Vias (BEV)2201, 2202.

Wherein, the magnetic tunnel junction bottom electrode Pre-deposition Metal Layer (MTJ BE Pre-dep Metal Layer)310 can also BE called pseudo-magnetic tunnel junction bottom electrode Pre-deposition Metal Layer (Dummy-MTJ BE Pre-dep Metal Layer), the total thickness is 5 nm-50 nm, and the forming material is Ti, TiN, W, WN, Ta, TaN, Ru or any combination thereof.

2.2: the area of the pseudo-magnetic tunnel junction bottom electrode pre-deposition Metal (Dummy-MTJ BEPre-dep Metal)340 with rough surface is defined graphically as shown in FIG. 2 (a).

Wherein, the area occupied by the Metal (Dummy-MTJ BE Pre-dep Metal)340 before deposition of the bottom electrode of the rough surface of the pseudo magnetic tunnel junction is generally larger than that occupied by the subsequent pseudo magnetic tunnel junction Unit 422(Dummy-MTJ Unit).

2.3: etching to manufacture pseudo-magnetic tunnel junction bottom electrode Pre-deposition Metal (Dummy-MTJ BE Pre-dep Metal)340 with rough surface, removing mask 320, and selectively grinding magnetic tunnel junction bottom electrode Pre-deposition Metal Layer (MTJ BE Pre-dep Metal Layer)310 in memory array Unit (ArrayUnit) region by planarization process to meet the requirement of manufacturing Magnetic Tunnel Junction (MTJ), and simultaneously ensuring lower flatness in peripheral circuit Unit (peripheral Unit) region, especially under pseudo-magnetic tunnel junction bottom electrode (Dummy-BE). As shown in fig. 2 (b).

The Etching process is implemented by Reactive Ion Etching (RIE) or Ion Beam Etching (Ion Beam Etching).

Step three: a magnetic tunnel junction bottom electrode (MTJ BE) (pseudo-magnetic tunnel junction bottom electrode Dummy-MTJBE) film layer 410, a Magnetic Tunnel Junction (MTJ) (pseudo-magnetic tunnel junction Dummy-MTJ) multilayer film 420, a magnetic tunnel junction top electrode (MTJ TE) (pseudo-magnetic tunnel junction bottom electrode Dummy-MTJ TE) film layer 430, and/or a sacrificial mask layer 440 are sequentially deposited. As shown in fig. 3.

Specifically, the method comprises the following steps: a magnetic tunnel junction bottom electrode film layer, a magnetic tunnel junction multilayer film and a magnetic tunnel junction top electrode film layer are sequentially deposited on a magnetic tunnel junction bottom electrode pre-deposition metal layer in a storage array unit area, and a pseudo magnetic tunnel junction bottom electrode film layer, a pseudo magnetic tunnel junction multilayer film and a pseudo magnetic tunnel junction top electrode film layer are sequentially deposited on a magnetic tunnel junction bottom electrode pre-deposition metal layer in a peripheral circuit unit area.

Or, a magnetic tunnel junction bottom electrode film layer, a magnetic tunnel junction multilayer film, a magnetic tunnel junction top electrode film layer and a sacrificial mask layer are sequentially deposited on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the memory array unit region, and a pseudo-magnetic tunnel junction bottom electrode film layer, a pseudo-magnetic tunnel junction multilayer film, a pseudo-magnetic tunnel junction top electrode film layer and a sacrificial mask layer are sequentially deposited on the magnetic tunnel junction bottom electrode pre-deposition metal layer in the peripheral circuit unit region.

The magnetic tunnel junction bottom electrode (MTJ BE) (pseudo-magnetic tunnel junction bottom electrode Dummy-MTJ BE) film 410 is generally Ta, TaN, Ti, TiN, W, WN, Ru, or any combination thereof, has a thickness ranging from 5nm to 80nm, and can BE implemented by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).

The total thickness of the multilayer film 420 of the Magnetic Tunnel Junction (MTJ) (pseudo magnetic tunnel junction (Dummy-MTJ)) is 8nm to 40nm, and the multilayer film can be a Bottom Pinned structure in which a reference layer, a barrier layer and a memory layer are sequentially stacked upwards or a Top Pinned structure in which the memory layer, the barrier layer and the reference layer are sequentially stacked upwards.

Further, the reference layer of the vertical type (pSTT-MRAM) generally has a superlattice multilayer film structure of [ Co/(Ni, Pd, Pt) ] n/Co/Ru/Co/[ (Ni, Pd, Pt)/Co ] m/(Ta, W, Mo, Hf, CoTa, FeTa, TaCoFeB)/CoFeB (where: n > m, m ≧ 0), and a seed layer is usually required below, for example: Ta/Pt, Ta/Ru, Pt/Ru and the like, and the total thickness of the reference layer is preferably 4-20 nm.

The barrier layer is a nonmagnetic metal oxide, preferably MgO, and has a thickness of 0.5 to 3 nm.

In the peripheral circuit Unit (peripheral Unit) region, the barrier layer, especially on the rough surface, is deformed, thereby destroying the structure of the barrier layer.

Further, the vertical pSTT-MRAM memory layer is typically CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W, Mo, Hf)/CoFeB, and preferably has a thickness of 0.8nm to 2 nm.

The thickness of the top electrode (MTJ) 430 (pseudo-magnetic tunnel junction bottom electrode Dummy-MTJ TE) is 20nm to 100nm, and Ta, TaN, Ti, TiN, W, WN or any combination thereof is selected to obtain a better profile in the halogen plasma.

Further, a sacrificial mask 440, typically of SiO, may be deposited after the top electrode film 430 is deposited₂SiON, SiC, SiCN, SiN, or any combination thereof.

Step four: the Magnetic Tunnel Junction (MTJ)421 and the pseudo-magnetic tunnel junction (Dummy-MTJ)422 are defined graphically and their Top Electrodes (TE)431,432, Magnetic Tunnel Junction (MTJ)421 and pseudo-magnetic tunnel junction (Dummy-MTJ)422 are etched with the etch stopping on the Bottom Electrode (BE)411,412 as shown in FIG. 4.

Generally with Cl₂Or CF₄The top electrodes 431,432 are etched by a Reactive Ion (RIE) etching process, which is the main etching gas, and simultaneously the remaining polymer is removed by a dry and/or wet process to transfer the pattern to the top of the Magnetic Tunnel Junction (MTJ) and the pseudo-magnetic tunnel junction (Dummy-MTJ).

The Etching of the Magnetic Tunnel Junction (MTJ)421 and the pseudo-magnetic tunnel junction (Dummy-MTJ)422 is simultaneously completed by Reactive Ion Etching (RIE) and/or Ion Beam Etching (IBE), and the Etching is stopped on the Bottom Electrodes (BE)411, 412.

Wherein, IBE mainly adopts Ar, Kr or Xe and the like as an ion source; RIE mainly uses CH₃OH,CH₄/Ar、C₂H₅OH、CH₃OH/Ar or CO/NH₃Etc. as the main etching gas.

Further, after the etching is completed, the sidewall damage/capping layer remaining around the Magnetic Tunnel Junction (MTJ)421 and the pseudo magnetic tunnel junction (Dummy-MTJ)422 is removed using the IBE process.

Step five: and manufacturing a self-aligned mask for etching the magnetic tunnel junction bottom electrode (MTJ BE)411 and the Pre-deposition Metal (MTJ BE Pre-dep Metal)311 thereof, the pseudo magnetic tunnel junction bottom electrode (MTJ BE)412 and the Pre-deposition Metal (MTJ BE Pre-dep Metal)340 side wall thereof, as shown in FIGS. 5-10.

Wherein the sidewall self-aligned mask can be formed by n-times deposition>Etching of]The process is realized, wherein n is more than or equal to 1. Further, the magnitude of n is preferably selected such that the Critical Dimension (Critical Dimension) of the self-aligned mask including the sidewall is larger than M_x(x.gtoreq.1) Critical Dimension (CD).

Further, the deposition process is generally selected from CVD, PVD, ALD or IBD, and the process parameters are strictly controlled so that the sidewall film is conformal to cover the periphery of the Magnetic Tunnel Junction (MTJ) and its Top Electrode (TE) and the pseudo-magnetic tunnel junction (Dummy-MTJ) and its Top Electrode (TE), the top of the magnetic tunnel junction top electrode (MTJ TE) and the pseudo-magnetic tunnel junction (Dummy-MTJ TE), and the Etch Front end (Etch Front) of the magnetic tunnel junction bottom electrode (MTJ BE) and the pseudo-magnetic tunnel junction bottom electrode (Dummy-MTJ BE).

Further, the first deposited material is generally selected from SiN, SiC or SiCN, etc.

Further, the materials deposited from the 2 nd to the n nd deposition are generally selected from SiO₂SiON, SiN, SiC, SiCN, or low dielectric constant (low-k) dielectrics, and the like.

The Low dielectric constant (Low-k) dielectric is a material having a dielectric constant (k) lower than that of silicon dioxide (k ═ 3.9), and in the specific implementation, the Low-k material may be Hydrogen Silicate (HSQ, k ═ 2.8 to 3.0), methylsilicate-containing (MSQ, k ═ 2.5 to 2.7) containing Si-CH3 functional groups, hybrid organosiloxane Polymer (HOSP) film (k ═ 2.5) synthesized by synthesizing HSQ and MSQ, Porous SiOCH film (k ═ 2.3 to 2.7), or even Porous high molecular compound such as Porous Silicate (k ≦ 2.0) and Porous high molecular weight (CH) film (k ≦ 1.9).

Etching process, generally adopting RIE process, etching gas is generally C₄F₈、C₃F₆、C₄F₆、C₂F₆、SF₆、NF₃、CF₄、CHF₃、CH₂F₂、CH₃F、O₂、N₂、NH₃、He、Ar、Co、CO₂Or CH₄And the like.

The process parameters, particularly the power of the ion bombarded RF power supply, are controlled so that the deposition on the sidewall is hardly etched, while the deposition on the front end of the bottom electrode etching is etched clean.

After the last etch, the residue may optionally be removed using dry and/or wet processes.

Referring to fig. 5-10, a detailed flow diagram of a sidewall self-aligned mask for preparing an etched Magnetic Tunnel Junction Bottom Electrode (MTJBE)411 and a Pre-deposition Metal (MTJ BE Pre-dep Metal)311 thereof, a pseudo magnetic tunnel junction bottom electrode (MTJ BE)412 and a Pre-deposition Metal (MTJ BE Pre-dep Metal)340 thereof by using a [ deposition- > etching ] process flow for 3 times is shown.

Step six: the magnetic tunnel junction bottom electrode (MTJ BE)411 and its Pre-deposition Metal (MTJ BE Pre-dep Metal)310, the pseudo magnetic tunnel junction bottom electrode (MTJ BE)412 and its Pre-deposition Metal (MTJ BE Pre-dep Metal)340 are etched using the sidewall self-aligned mask as a hard mask, as shown in fig. 11.

The etching process may be implemented by using an RIE process or an IBE process.

Step seven: a magnetic tunnel junction/pseudomagnetic tunnel junction fill dielectric 480 is deposited and chemical mechanical planarization is employed up to the magnetic tunnel junction top electrode (MTJ-TE)/pseudomagnetic tunnel junction top electrode (Dummy-MTJ TE) as shown in fig. 12.

The magnetic tunnel junction/pseudomagnetic tunnel junction fill dielectric 480 is typically made of SiO₂SiON or low dielectric constant (low-k) dielectrics, typically implemented using CVD.

Step eight: depositing metal connecting line M_x+1Interlayer dielectric 510 and metal line M_x+1(521,522) is shown in FIG. 13.

Metal connecting wire M_x+1Interlayer dielectric 510 is typically SiO₂SiON or Low dielectric constant (Low-K) dielectric, and selectively depositing a metal line M_x+1An etch stop layer (SiN, SiC, SiCN, or the like) is deposited before the interlayer dielectric.

Wherein, the metal connecting line M_x+1521,522 is metallic Cu, and Ti/TiN or TaN/Ta is added as a diffusion barrier layer.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.