阅读说明：本技术 包括层叠存储单元的阻变存储器件 (Resistive memory device including stacked memory cells ) 是由 金东槿 于 2019-10-17 设计创作，主要内容包括：本申请公开一种包括层叠的存储单元的阻变存储器件,包括其中布置有存储单元的多个存储片。第一级字线至第三级字线沿存储片区域的行利用解码电路顺序地层叠在多个存储片区域上。第一级位线被插置在第一级字线和第二级字线之间。第一级位线可以沿存储片区域的列延伸。第二级位线可以被插置在第二级字线和第三级字线之间。第二级位线可以沿存储片区域的列延伸。通过所选存储片区域的解码电路来控制存储片区域之中的所选存储片区域的所选行处的第一级字线和第三级字线以及所选存储片区域的所选列处的第二级位线。通过另一存储片区域的另一解码电路来控制在所选存储片区域的所选行处的第二级字线和在所选存储片区域的所选列处的第一级位线。(A resistive memory device including stacked memory cells includes a plurality of memory slices in which the memory cells are arranged. First-level to third-level word lines are sequentially stacked on the plurality of chip regions along rows of the chip regions using a decoding circuit. The first level bit line is interposed between the first level word line and the second level word line. The first level bit lines may extend along columns of the memory slice regions. The second level bit line may be interposed between the second level word line and the third level word line. The second level bit lines may extend along columns of the memory slice regions. The first-level word line and the third-level word line at a selected row of a selected chip region among the chip regions and the second-level bit line at a selected column of the selected chip region are controlled by a decoding circuit of the selected chip region. The second level word line at a selected row of the selected chip area and the first level bit line at a selected column of the selected chip area are controlled by another decoding circuit of another chip area.)

1. A resistive memory device, comprising:

a plurality of memory slices in which memory cells are arranged;

first-level to third-level word lines sequentially stacked on each of the plurality of memory chips along a row of each memory chip;

first-level bit lines interposed between the first-level word lines and the second-level word lines and extending along columns of each memory chip; and

second level bit lines interposed between the second level word lines and the third level word lines and extending along columns of each memory chip,

wherein the first level word line and the third level word line of the selected row of the selected memory chip and the second level bit line of the selected column of the selected memory chip are controlled by a decoding circuit of the selected memory chip, an

Wherein the second level word line of the selected row and the first level bit line of the selected column in the selected memory slice are controlled by another decoding circuit of another memory slice.

2. The resistive-switching memory device according to claim 1, wherein the memory cell is provided at: an intersection between the first level word line and the first level bit line, an intersection between the first level bit line and the second level word line, an intersection between the second level word line and the second level bit line, and an intersection between the second level bit line and the third level word line.

3. The resistive-switching memory device according to claim 1, wherein the decoding circuit comprises:

a row switch unit including a plurality of row switch transistors connected to each row, wherein each of the plurality of row switch units is configured to be connected to a different word line group in such a manner that all word lines are connected to one of the plurality of row switch units; and

a column switch unit including a column switch transistor connected to each column, wherein each of the plurality of column switch units is configured to be connected to a different bit line group in such a manner that all bit lines are connected to one of the plurality of column switch units.

4. The resistive-switching memory device according to claim 1, wherein the decoding circuit comprises:

a first row switch unit for controlling an upper row among the rows; and

a second row switch unit for controlling a lower row among the rows,

wherein the first row of switch units is disposed at one end of each of the upper rows, and the second row of switch units is disposed at the other end of each of the lower rows.

5. The resistive-switching memory device according to claim 4, wherein the first row switch unit includes a row switch transistor disposed at one end of each of the upper rows, and the second row switch unit includes a row switch transistor disposed at the other end of each of the lower rows.

6. The resistive-switching memory device according to claim 4, wherein the first-level word line and the third-level word line located at the selected row of the selected memory chip are commonly connected with the second-level word line located at the selected row of the memory chip adjacent to the selected memory chip, and the first row switch unit or the second row switch unit of the selected memory chip,

a second level word line located at a selected row of the selected memory chip is commonly connected with a first level word line and a third level word line located at a selected row of a memory chip adjacent to the selected memory chip, and a first row switching cell or a second row switching cell of an adjacent memory chip, an

The memory chip adjacent to the selected memory chip is positioned adjacent to the selected memory chip along the extending direction of the word line.

7. The resistive-switching memory device according to claim 1, wherein the decoding circuit comprises:

a first column switch unit for controlling a left column among the columns; and

a second column switch unit for controlling a right-side column among the columns,

wherein the first column switch unit is disposed at one end of each of the left side columns, and the second column switch unit is disposed at the other end of each of the right side columns.

8. The resistive-switching memory device according to claim 7, wherein the first column switch unit includes a column switch transistor disposed at one end of each of the left side columns, and the second column switch unit includes a column switch transistor disposed at the other end of each of the right side columns.

9. The resistive-switching memory device according to claim 8, wherein the second-level bit line located at the selected column of the selected memory slice is electrically connected to the first-level bit line located at the selected column of the memory slice adjacent to the selected memory slice and the first column switch or the second column switch of the selected memory slice,

a first level bit line at a selected column of the selected memory slice is electrically connected to a second level bit line at a selected column of a memory slice adjacent to the selected memory slice and either the first column switch or the second column switch of the adjacent memory slice, an

The memory slice adjacent to the selected memory slice is positioned adjacent to the selected memory slice along the extending direction of the bit line.

10. The resistive memory device according to claim 9, wherein the first-level bit lines and the second-level bit lines are arranged in units of the memory chip.

11. The resistive-switching memory device according to claim 9, wherein the first-level bit line and the second-level bit line extend in units of two memory slices that are not disconnected, and the first-level bit line and the second-level bit line are arranged in a staggered shape to overlap each other on the selected memory slice.

12. The resistive-switching memory device according to claim 11, wherein the first-level bit line and the second-level bit line are located at the same column overlapped on the corresponding memory chip,

central portions of first-level bit lines and second-level bit lines located at the same column are arranged at both sides of the corresponding memory chip, an

Center portions of the first-level bit line and the second-level bit line are electrically connected to different column switching transistors located at different memory chips.

13. The resistive-switching memory device according to claim 8, further comprising an auxiliary bit line pad partially overlapping the column switch transistors through the column and extending through a gap between the memory slices, wherein the first-stage bit line and the second-stage bit line are electrically connected to the column switch transistors through the auxiliary bit line pad.

14. The resistive-switching memory device according to claim 13, wherein the auxiliary bit line pad is located between a plane in which the column switch transistors are formed and a plane in which the first-level word lines are formed.

15. A resistive memory device, comprising:

a plurality of memory slices;

a control block;

a first memory layer stacked on each of the memory chips having the control blocks, the first memory layer including first-level word lines, first-level memory cells, and first-level bit lines sequentially stacked;

a second memory layer stacked on the first-level bit lines of the first memory layer, the second memory layer including second-level memory cells and second-level word lines sequentially stacked;

a third memory layer stacked on the second-level word lines of the second memory layer, the third memory layer including third-level memory cells and second-level bit lines sequentially stacked; and

a fourth memory layer stacked on the second-level bit lines of the third memory layer, the fourth memory layer including fourth-level memory cells and third-level word lines sequentially stacked,

wherein the first level word line and the third level word line of the selected row of the selected memory chip and the second level word line of the selected row of the first memory chip adjacent to the selected memory chip are controlled by the row switching unit of the selected memory chip, an

Wherein a second-level bit line located at a selected column of a selected memory slice and a first-level bit line of a second memory slice adjacent to the selected memory slice are controlled by a column switching unit of the selected memory slice.

16. The resistive-switching memory device according to claim 15, wherein the control block comprises:

a first row switch unit including a row switch provided to each of the upper rows among the rows and disposed at one end of the row;

a second row switch unit including a row switch provided at the other end of the row provided to each of the lower rows;

a first column switch unit including a column switch provided to each left column among the columns, the column switch being provided at one end of the column; and

a second column switch unit including a column switch provided at the other end of each of the columns to the right side column.

17. The resistive-switching memory device according to claim 15, further comprising an insulating layer which is located between the control block and the first memory layer and includes a plurality of auxiliary bit line pads,

wherein the auxiliary bit line pad partially overlaps the column switch and extends through a gap between the memory slices.

18. The resistive-switching memory device according to claim 17, wherein the second-level bit line of the selected memory slice and the first-level bit line of the second memory slice are electrically connected to one of the column switches located at the selected column through an auxiliary bit line pad located at the selected column of the selected memory slice.

19. The resistive-switching memory device according to claim 15, wherein the first memory slice is any one of memory slices adjacent to the selected memory slice along a direction in which the word line extends, and the first memory slice is positioned adjacent to a row switch for controlling a selected row of the selected memory slice.

20. The resistive-switching memory device according to claim 15, wherein the second memory slice is any one of memory slices adjacent to the selected memory slice along a direction in which the bit line extends, and the second memory slice is positioned adjacent to a column switch for controlling a selected column of the selected memory slice.

21. The resistive memory device according to claim 15, wherein the first-level to third-level word lines are separately arranged in units of the memory chip, and the first-level and second-level bit lines are separately arranged in units of the memory chip.

22. A resistive memory device, comprising:

a first memory layer including first-level word lines, first-level memory cells, and first-level bit lines sequentially stacked;

a second storage layer disposed on the first-level bit lines of the first storage layer, the second storage layer including second-level memory cells and second-level word lines sequentially stacked;

a third memory layer disposed on the second-level word lines of the second memory layer, the third memory layer including third-level memory cells and second-level bit lines sequentially stacked; and

a fourth storage layer disposed on the second-level bit lines of the third storage layer, the fourth storage layer including fourth-level memory cells and third-level word lines sequentially stacked,

wherein the first-level bit lines and the second-level bit lines extend in units of two memory slices that are not disconnected, and the first-level bit lines and the second-level bit lines are arranged in a staggered shape to overlap each other on the selected memory slice,

wherein a central portion of a first-level bit line in the selected memory slice is electrically connected to a column switch cell of the selected memory slice, an

Wherein a central portion of the second-level bit line in the selected memory slice is electrically connected to the column switch unit of the memory slice adjacent to the selected memory slice.

23. The resistive memory device according to claim 22, wherein a column switch unit provided for each of the memory slices includes a column switch transistor provided to an edge portion of each of the columns in the memory slice, and an auxiliary bit line pad is arranged on the column switch transistor and connected to the first-stage bit line or the second-stage bit line.

Technical Field

Various embodiments may relate generally to a nonvolatile memory device, and more particularly, to a resistive memory device including a plurality of stacked memory layers (deck).

Background

In order to provide a memory device having a high capacity and low power consumption, a next-generation memory device of a nonvolatile type without periodic refresh has been studied. Next generation memory devices may require high integration of Dynamic Random Access Memory (DRAM), non-volatility for refreshing memory, speed of SRAM, and the like.

The resistive memory device as a next-generation memory device may include a phase-change ram (pcram), a Nano Floating Gate Memory (NFGM), a polymer ram (poram), a magnetic ram (mram), a ferroelectric ram (feram), a resistive ram (reram), and the like.

The PCRAM may include a switching element and a storage element arranged at an overlapping portion of a word line and a bit line. Therefore, the memory cell array structure of the PCRAM may be referred to as a cross-point array.

Next generation memory devices may also require a high degree of integration. Therefore, a stacked memory cell structure including alternately stacked word lines and bit lines can be proposed.

Disclosure of Invention

In example embodiments of the present disclosure, a resistive memory device may include a plurality of memory slices (tiles) in which memory cells are arranged. The first-level to third-level word lines may be sequentially stacked on the plurality of chip regions along rows of the chip regions using a decoding circuit. The first level bit line may be interposed between the first level word line and the second level word line. The first level bit lines may extend along columns of the memory slice regions. The second level bit line may be interposed between the second level word line and the third level word line. The second level bit lines may extend along columns of the memory slice regions. The first-level word line and the third-level word line at a selected row of a selected chip region among the chip regions and the second-level bit line at a selected column of the selected chip region may be controlled by a decoding circuit of the selected chip region. The second level word line at a selected row of the selected chip region and the first level bit line at a selected column of the selected chip region may be controlled by another decoding circuit of another chip region.

In example embodiments of the present disclosure, a resistive memory device may include a plurality of memory slices and a control block. The first memory layer stacked on each memory chip having the control block may include first-level word lines, first-level memory cells, and first-level bit lines sequentially stacked on each memory chip area having the control block. The second memory layer may include second-level memory cells and second-level word lines sequentially stacked on the first-level bit lines of the first memory layer. The third memory layer may include third-level memory cells and second-level bit lines sequentially stacked on the second-level word lines of the second memory layer. The fourth memory layer may include fourth-level memory cells and third-level word lines sequentially stacked on the second-level bit lines of the third memory layer. The first-level and third-level word lines at a selected row of a selected chip area among the chip areas and the second-level word lines at a selected row of a first chip area adjacent to the selected chip area may be controlled by a row switch of the selected chip area. The second-level bit line at the selected column of the selected chip area and the first-level bit line at the second chip area adjacent to the selected chip area may be controlled by the column switch of the selected chip area.

In example embodiments of the present disclosure, a resistive memory device may include a first memory layer, a second memory layer, a third memory layer, and a fourth memory layer. The first memory layer may include first-level word lines, first-level memory cells, and first-level bit lines sequentially stacked on the control block. The second memory layer may include second-level memory cells and second-level word lines sequentially stacked on the first-level bit lines of the first memory layer. The third memory layer may include third-level memory cells and second-level bit lines sequentially stacked on the second-level word lines of the second memory layer. The fourth memory layer may include fourth-level memory cells and third-level word lines sequentially stacked on the second-level bit lines of the third memory layer. The first-level to third-level word lines may intersect the first-level bit lines and the second-level bit lines. The first-level bit line and the second-level bit line may extend in units of two memory slices that are not disconnected. The first-level bit lines and the second-level bit lines may be arranged to overlap each other on the selected chip area in a staggered shape. The first-level bit lines in the selected memory chip area may have a central portion electrically connected to the column switches of the selected memory chip area. The second-level bit lines in the selected memory chip area may have a central portion electrically connected to the column switches of the memory chip areas adjacent to the selected memory chip area.

In an example embodiment of the present disclosure, a resistive switching memory system may include a processor, a controller, and a memory device. The memory device may include a plurality of memory slices in which memory cells are arranged. The first-level word lines to the third-level word lines may be sequentially stacked on the plurality of chip regions along the rows of the chip regions using the decoding circuit. The first level bit line may be interposed between the first level word line and the second level word line. The first level bit lines may extend along columns of the memory slice regions. The second level bit line may be interposed between the second level word line and the third level word line. The second level bit lines may extend along columns of the memory slice regions. The first-level word line and the third-level word line at a selected row of a selected chip region among the chip regions and the second-level bit line at a selected column of the selected chip region may be controlled by a decoding circuit of the selected chip region. The second level word line at the selected row of the selected chip region and the first level bit line at the selected column of the selected chip region may be controlled by another decoding circuit of another chip region.

Drawings

The above and other aspects, features and advantages of the presently disclosed subject matter will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a semiconductor system according to an example embodiment;

fig. 2 is a perspective view illustrating a memory cell array of a resistive memory device according to an example embodiment;

FIG. 3 is a perspective view illustrating a memory chip according to an example embodiment;

fig. 4 is a circuit diagram illustrating a storage layer according to an example embodiment;

FIG. 5 is a perspective view illustrating a storage unit according to an example embodiment;

FIG. 6 is a plan view illustrating a control block according to an example embodiment;

fig. 7 is a plan view illustrating a memory array memory slice (MAT) including a plurality of memory slices according to an example embodiment;

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7;

FIG. 9 is a sectional view taken along line IX-IX' in FIG. 7; and

fig. 10 is a sectional view illustrating an arrangement of bit lines according to an example embodiment.

Detailed Description

Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The figures are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein but are to include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as defined by the appended claims.

The present invention is described herein with reference to cross-sectional and/or plan views of preferred embodiments of the invention. However, the embodiments of the present invention should not be construed as limiting the inventive concept. Although a few embodiments of the present invention will be shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention.

Although terms such as "first" and "second" may be used to describe various components, these components must not be understood as being limited to the above terms. The above terms are only used to distinguish one component from another component. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present disclosure.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms in this disclosure are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that terms such as "including" or "having," or the like, are intended to indicate the presence of the features, numbers, operations, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, operations, actions, components, parts, or combinations thereof may be present or may be added.

FIG. 1 is a block diagram illustrating a semiconductor system according to an example embodiment.

Referring to fig. 1, a semiconductor system 100 may include a processor 110, a controller 120, and a memory device 200.

The processor 110 may be connected to the controller 105 through a bus 105. The processor 110 may provide memory access requests (read requests, write requests, etc.) including memory addresses and data to the controller 120. The processor 110 may receive read data from the controller 120.

The controller 120 may provide commands CMD, such as a read command, a write command, and the like, addresses ADD, DATA, and control signals CTRL to the semiconductor memory device 200 in order to operate the semiconductor memory device 200.

The memory device 200 may include a nonvolatile resistive memory device including a variable resistance element. The variable resistance element may change a variable resistance characteristic according to a current and/or a voltage to perform a memory operation. For example, the variable resistance element may include a material used in RRAM, PRAM, MRAM, FRAM, or the like, such as a chalcogenide compound, a transition metal compound, a ferroelectric, a ferromagnetic substance, or the like. However, the variable resistance element is not limited to the above-described materials. In particular, the variable resistance element may include a metal oxide. The metal oxide may include: transition metal oxides (e.g., nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, tungsten oxide, cobalt oxide, etc.), perovskite materials (e.g., sto (srtio), pcmo (prcamno), etc.).

The variable resistance element may comprise a phase-changeable material. The phase-changeable material may include a chalcogenide material, such as GST (Ge-Sb-Te). The variable resistive element can be stabilized into any one of a crystalline state and an amorphous state by applying heat to represent switching characteristics between different resistance states.

The variable resistance element may include a tunnel barrier layer between two magnetic layers. The magnetic layer may include NiFeCo, CoFe, or the like. The tunnel barrier layer may include Al₂O₃And the like. The variable resistance element may exhibit switching characteristics between different resistance states according to the magnetization direction of the magnetic layer. For example, when the magnetization directions of the magnetic layers are parallel to each other, the variable resistance element may have a low resistance state. In contrast, when the magnetization directions of the magnetic layers are not parallel to each other, the variable resistive element may have a high resistance state. Hereinafter, the memory device 200 of this example embodiment may correspond to a nonvolatile resistance change memory device. The nonvolatile resistive random access memory device 200 may include a memory cell array 210 and a control block 250.

Fig. 2 is a perspective view illustrating a memory cell array of a resistive memory device according to an example embodiment.

Referring to fig. 2, the memory cell array 210 of the resistive memory device 200 may include a plurality of MATs.

Each MAT may be divided into a plurality of memory slices T1-T4. In an example embodiment, one MAT may be divided into four memory slices T1 through T4. Each of the memory slices T1-T4 may include a plurality of memory cells.

The control block 250 may be provided to each of the memory chips T1-T4. For example, the control block 250 may be interposed between each of the memory chips T1 through T4 and the semiconductor substrate 300.

Fig. 3 is a perspective view illustrating a memory sheet according to an example embodiment. The memory chips T1-T4 may have substantially the same configuration. FIG. 3 illustrates a first memory chip T1 among the memory chips T1-T4.

Referring to fig. 3, a memory chip T1 may be disposed on a semiconductor substrate 300, and a control block 250 is disposed between the memory chip T1 and the semiconductor substrate 300. The memory sheet T1 may include a plurality of stacked memory layers D1-D4. Each of the storage layers D1 through D4 may have a two-dimensional arrangement with a plurality of storage cells. In an example embodiment, the memory sheet T1 may include four stacked memory layers D1-D4.

Fig. 4 is a circuit diagram illustrating a storage layer according to an example embodiment.

Referring to fig. 4, the memory layer D1 may include a plurality of word lines WL0 to WL3, a plurality of bit lines BL0 to BL3, and memory cells MC. Each of the storage layers D1 to D4 may have substantially the same configuration.

The bit lines BL 0-BL 3 may intersect the word lines WL 0-WL 3. The memory cells MC may be located at intersections of word lines WL 0-WL 3 and bit lines BL 0-BL 3, respectively.

Fig. 5 is a perspective view illustrating a memory cell according to an example embodiment.

Referring to fig. 5, a memory cell MC may include a selector 32, an intermediate electrode 35, and a storage layer 38 at the intersection of a word line WL and a bit line BL. The selector 32, the intermediate electrode 35, and the storage layer 38 may be sequentially stacked at an intersection between the word line WL and the bit line BL.

At least one of the selector 32 and the storage layer 38 may include a chalcogenide material as the phase-changeable material. When the storage layer 38 includes a chalcogenide material, the chalcogenide material of the storage layer 38 may have a non-volatile phase change at room temperature. In contrast, the chalcogenide material of selector 32 may have different phase change characteristics than the chalcogenide material in storage layer 38. According to an embodiment, the positions of the selector 32 and the storage layer 38 may be reversed.

The selector 32 may be an OTS (ovonic threshold switch) element comprising an OTS material. The OST material may include a chalcogenide material that makes up the storage layer 38. However, the selector 32 may further include an element for suppressing crystallization, such As arsenic (As). This element can prevent the formation of non-temporary nuclei and prevent the growth of chalcogenide material, thereby inhibiting crystallization. Therefore, when a potential higher than the critical voltage is applied, the selector 32 can be switched to the on state. Sufficient current may be provided to the selector 32 during the on state. For example, the selector 32 may include Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, Ge-As-Bi-Se, and the like. The word line WL may be used as a heating electrode for heating the selector 32.

The storage layer 38 (i.e., the phase-changeable storage layer) may include elements In an In-Sb-te (ist) alloy system. For example, the phase-changeable storage layer may comprise an element In the Ge-Sb-Te (GST) alloy system, In₂Sb₂Te₅、In₁Sb₂Te₄And In₁Sb₄Te₇At least two of them. In another embodiment, the phase-changeable storage layer may include Ge₈Sb₅Te₈、Ge₂Sb₂Te₅、Ge₁Sb₂Te₄、Ge₁Sb₄Te₇And Ge₄Sb₄Te₇Etc. of the display. Herein, the use of hyphenated chemical composition notation may indicate the elements of a particular mixture or compound and all stoichiometries attendant to the elements. The chalcogenide alloy of storage layer 38 may include: Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, In-Ge-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ag-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, Ge-Te-Sn-Pt, etc.

The intermediate electrode 35 may be a node for electrically connecting the selector 32 with the storage layer 38. The intermediate electrode 35 may be used as a heating electrode for heating the storage layer 38.

For example, the word line WL, the selector 32, and the intermediate electrode 35 may form an access element S of the memory cell MC. The intermediate electrode 35, the storage layer 38, and the bit line BL may form a variable resistance R of the memory cell MC.

In example embodiments, the stacked memory layers D1 through D4 may share a word line WL or a bit line BL in common. For example, the first and second memory layers D1 and D2 may share the bit line BL in common. The second and third memory layers D2 and D3 may share a word line WL in common. The third and fourth memory layers D3 and D4 may share a bit line BL in common.

Fig. 6 is a plan view illustrating a control block according to an example embodiment.

Referring to fig. 6, as described above, the control block 250 may be disposed between the semiconductor substrate 300 and the memory chip T1. Control block 250 may include transistors for forming a plurality of control circuits.

For example, control block 250 may include control logic 252, voltage generation circuit 254, read/write circuit 256, and decode circuit 260.

The control logic 252 may generate control signals for writing DATA into the stacked memory layers D1 through D4 or for reading DATA based on a command CMD, an address ADD, and a control signal CTRL received from the memory controller 120. The control signals may be provided to the voltage generation circuit 254, the read/write circuit 256, and the decoding circuit 260. The control logic 252 may provide operation control signals to the read/write circuits 256 for operating the read/write circuits 256. For example, the operation control signal may include a write enable signal, a read enable signal, a sense enable signal, a discharge enable signal, a precharge enable signal, and the like. The control logic 252 may provide a voltage generation signal to the voltage generation circuit 254.

The voltage generation circuit 254 may generate voltages for performing a write operation, a read operation, and an erase operation on the memory cell array 210. In particular, the voltage generation circuit 254 may generate a word line driving voltage V to drive a word line_WLAnd a bit line driving voltage for driving the bit lineV_BL. Word line driving voltage V_WLAnd bit line driving voltage V_BLMay include a reset write voltage, a set write voltage, an inhibit voltage, a read voltage, a verify voltage, etc.

The decoding circuit 260 may include row switching units 260a and 260b and column switching units 270a and 270 b. The row switching units 260a and 260b may select a word line of a selected row in the memory chip T in response to a row address. The column switch units 270a and 270b may select a bit line of a selected column in the memory chip T in response to a column address.

The row switching cells 260a and 260b may be classified into a first row switching cell 260a and a second row switching cell 260b according to their positions. Accordingly, the word lines may be divided and controlled by the first and second row switching units 260a and 260 b. For example, the first and second row switching cells 260a and 260b may be arranged on a diagonal line intersecting the center point c of the memory chip T. For example, when the memory chip T is divided into first to fourth quadrants, the first row switching unit 260a may be positioned at an outer edge portion of the first quadrant, and the second row switching unit 260b may be positioned at an outer edge portion of the fourth quadrant, so that all word lines may be connected to the first or second row switching units 260a or 260 b.

The column switch units 270a and 270b may be classified into a first column switch unit 270a and a second column switch unit 270b according to positions. Accordingly, the bit lines may be divided and controlled by the first and second column switch units 270a and 270 b. For example, the first and second column switch units 270a and 270b may be arranged on a diagonal line intersecting the center point c of the memory chip T. For example, the first column switch unit 270a may be positioned at an outer edge portion of the second quadrant, and the second column switch unit 270b may be positioned at an outer edge portion of the third quadrant, so that all bit lines may be connected to the first column switch unit 270a or the second column switch unit 270 b.

For example, when one memory chip T includes n rows, word lines positioned in the first to n/2 th rows may be connected to the first row switching unit 260 a. Here, the first row switching unit 260a may include switching transistors (row switching transistors) arranged at one edge portion (e.g., an edge portion of the first quadrant) of each of the first to n/2 th rows (upper rows). For example, a portion of the word lines positioned at the first to n/2 th rows may be connected to row switching transistors positioned at edge portions of the respective rows. Another portion of the word lines located at, for example, the first to n/2 th rows of the memory chip T2 in fig. 7 may be connected to row switching transistors located at the corresponding row of another memory chip. Another embodiment may disclose a configuration that may be reversed in such a manner that the first row of switching cells 260a may be disposed at an edge portion of the second quadrant.

Word lines positioned at (n +1)/2 th to nth rows (lower rows) may be connected to the second row switching unit 260 b. Here, the second row switching unit 260b may include a row switching transistor s disposed at another edge portion (e.g., an edge portion of a fourth quadrant) of each of the (n +1)/2 th to nth rows. For example, a portion of the word lines located at (n +1)/2 th to nth rows may be connected to the row switching transistors located at edge portions of the corresponding rows. Another portion of the word lines located at, for example, the (n +1)/2 th to nth rows of the memory chip T2 in fig. 7 may be connected to the row switching transistors located at the corresponding row of the other memory chip. Another embodiment may disclose a configuration that is turned over in such a manner that the second row switching cells 260b may be arranged at an edge portion of the third quadrant.

In addition, when one memory chip T includes m columns, bit lines positioned at the first to m/2 th columns (left columns) may be connected to the first column switch unit 270 a. Here, the first column switching unit 270a may include a switching transistor (column switching transistor) disposed at one edge portion (e.g., an edge portion of the second quadrant) of each of the first to m/2 th columns. For example, a portion of the bit lines located at the first to m/2 th columns may be connected to the column switching transistors located at the corresponding columns. Another portion of the bit lines located at, for example, the first to m/2 th columns of the memory chip T3 in fig. 7 may be connected to the column switching transistors located at the corresponding column of the other memory chip. Another embodiment may disclose a configuration that is reversed in such a manner that the first column of switching cells 270a may be disposed at an edge portion of the first quadrant.

Bit lines positioned at (m +1)/2 th to m-th columns (right-side columns) may be connected to the second column switching unit 270 b. Here, the second column switching unit 270b may include a column switching transistor disposed at another edge portion (e.g., an edge portion of a third quadrant) of each of the (m +1)/2 th to m-th columns. For example, a portion of the bit line located at the (m +1)/2 th to m-th columns may be connected to the column switching transistor located at an edge portion of the corresponding column. Another portion of the bit lines located at, for example, (m +1)/2 th to m-th columns of the memory chip T3 in fig. 7 may be connected to the column switching transistors located at the corresponding column of the other memory chip. Another embodiment may disclose a configuration that is turned over in such a manner that the second column of switching units 270b may be disposed at an edge portion of the fourth quadrant.

U.S. patent application 2018/0358085, the disclosure of which is incorporated herein by reference in its entirety, may disclose the relationship between row switch transistors, column switch transistors, and memory cells.

In another embodiment, the row switch cells and the column switch cells of the common resistive memory device may be located in a region between the memory chips T. For example, the row switches 260a and 260b and the column switches 270a and 270b may be disposed at portions overlapping with the memory layers in the memory chip T. Therefore, when the gaps are provided between the memory chips T, it may not be necessary to consider the areas of the row switch cells 260a and 260b and the column switch cells 270a and 270 b. Therefore, the area of the memory chip T can be enlarged by reducing the gap between the memory chips T.

In addition, in an example embodiment, circuits 252, 254, and 256 in control block 250 may be provided for each memory slice. Alternatively, the control logic 252, the voltage generation circuit 254, and the read/write circuit 256 of the control block 250 may be disposed at any one of the memory chips T1 through T4 to supply signals/voltages to the remaining memory chips.

Fig. 7 is a plan view illustrating a MAT including a plurality of memory slices according to an example embodiment. Fig. 8 is a sectional view taken along line VIII-VIII' in fig. 7. In addition, fig. 9 is a sectional view taken along a line IX-IX' in fig. 7.

Referring to fig. 7 to 9, the semiconductor substrate 300 may include a region where at least one MAT is to be formed. The MAT may be divided into memory slices where memory cells may be formed. In an example embodiment, one MAT may be divided into four memory slices T1-T4.

As described above, the gap between the conventional memory chips can be set in consideration of the area of the row switching unit (e.g., row decoder) or the column switching unit (e.g., column decoder).

In example embodiments, the row switch cells 260a and 260b and the column switch cells 270a and 270b are disposed under the memory chips T1-T4, except for the contact portions connecting the row switch cells 260a, 260b to the word lines and the contact portions connecting the column switch cells 270a, 270b to the bit lines. Since the conventional contact portion may have a minimum feature size, the gap between the memory chips T1 through T4 may be reduced to a size slightly larger (e.g., 10% to 20%) than the minimum feature size.

The row switch transistors SWR of the first and second row switch cells 260a and 260b and the column switch transistors SWC of the first and second column switch cells 270a and 270b may be formed on the semiconductor substrate 300 having the memory chips T1 to T4. The row switch transistors SWR may be disposed on the memory chips T1 to T4 for each row. The row switch transistor SWR may be disposed at one end or the other end of the memory chip according to the position of the row.

The column switch transistors SWC may be disposed on the memory chips T1 to T4 for each column. The column switch transistors SWC may be disposed at upper or lower ends of the memory chip according to the position of the columns.

For example, the arrangement direction of the row switch transistors SWR may be substantially perpendicular to the arrangement direction of the column switch transistors SWC.

As is well known, since the row switch transistor SWR and the column switch transistor SWC may include junction regions, the junction regions may partially diffuse into the gaps between the memory chips.

In an example embodiment, an auxiliary bit line pad 310 may be disposed for each column of memory slices T1-T4 for connecting a column switch transistor and a bit line. For example, the auxiliary bit line pad 310 may be located above the column switch transistor SWC of each of the memory slices T1-T4. For example, the auxiliary bit line pad 310 may be electrically connected to the drain of each column switch transistor SWC. In order to make the auxiliary bit line pad 310 easily contact the bit line, the auxiliary bit line pad 310 may extend from the drain of the column switch transistor SWC to a gap of the adjacent memory chip in the extending direction of the bit line. For example, at least one insulating layer may be interposed between the semiconductor substrate 300 having the row and column switch transistors SWR and SWC and the auxiliary bit line pad 310.

First level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8) may be arranged on the auxiliary bit line pad 310. First-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8) may be arranged on each of the memory chips T1-T4 along the x-direction (row direction) in FIG. 7. The first-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL in FIG. 8) and the auxiliary bit line pad 310 are insulated by an insulating layer. The insulating layer may serve as a planarization layer. Therefore, the first-level word lines 1_ WL0 ~ 1_ WLn-1 (1 _ WL of FIG. 8) can be arranged on the flat upper surface of the insulating layer. The first-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8) may be electrically connected to drains of row switch transistors SWR located at the same row of the corresponding memory chip shown in FIG. 8.

The first-level bit lines 1_ BL 0-1 _ BLm-1 (1 _ BL of FIG. 9) may be arranged and stacked on the first-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8). The first-level bit lines 1_ BL 0-1 _ BLm-1 (1 _ BL of FIG. 9) may extend through each of the memory slices T1-T4 along the y-direction (column direction) in FIG. 7 to intersect the first-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8). The first-level memory cells 1_ MC may be arranged at intersections between the first-level word lines 1_ WL0 ~ 1_ WLn-1 (1 _ WL of FIG. 8) and the first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9). Each memory cell MC may have the configuration in fig. 5. Accordingly, the first memory layer DECK1 may be formed of first-level word lines 1_ WL0 ~ 1_ WLn-1 (1 _ WL of FIG. 8), first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9), and first-level memory cells 1_ MC. Although not shown in the drawings, an insulating layer may be interposed between the first-level word lines 1_ WL0 ~ 1_ WLn-1 (1 _ WL of FIG. 8) and the first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9), that is, between the first-level memory cells 1_ MC.

The second-level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL of FIG. 8) may be arranged and stacked on the first-level bit lines 1_ BL 0-1 _ BLn-1 (1 _ BL of FIG. 9). The second level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL of FIG. 8) can intersect the first level bit lines 1_ BL 0-1 _ BLm-1 (1 _ BL of FIG. 9). The second-level memory cells 2_ MC may be formed at intersections between the first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9) and the second-level word lines 2_ WL0 ~ 2_ WLn-1 (2 _ WL of FIG. 8). Accordingly, the second memory layer DECK2 may be formed of first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9), second-level word lines 2_ WL0 ~ 2_ WLn-1 (2 _ WL of FIG. 8), and second-level memory cells 2_ MC. The insulating layer may be interposed between the first-level bit lines 1_ BL0 ~ 1_ BLm-1 (1 _ BL of FIG. 9) and the second-level word lines 2_ WL0 ~ 2_ WLn-1 (2 _ WL of FIG. 8), that is, between the second-level memory cells 2_ MC.

For example, the second-level memory cells 2_ MC, the first-level bit lines 1_ BL 0-1 _ BLm-1 (1 _ BL of FIG. 9), and the first-level memory cells 1_ MC are located between the first-level word lines 1_ WL 0-1 _ WLn-1 (1 _ WL of FIG. 8) and the second-level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL of FIG. 8).

The second-level bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL of FIG. 9) may be arranged and stacked on the second-level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL of FIG. 8). The second-level bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL of FIG. 9) may intersect the second-level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL of FIG. 8). The third-level memory cells 3_ MC may be arranged at intersections between the second-level bit lines 2_ BL0 ~ 2_ BLm-1 (2 _ BL of FIG. 9) and the second-level word lines 2_ WL0 ~ 2_ WLn-1 (2 _ WL of FIG. 8) to define a third storage layer DECK 3. For example, the third storage layer DECK3 may include: second-level bit lines 2_ BL0 to 2_ BLm-1 (2 _ BL of FIG. 9), second-level word lines 2_ WL0 to 2_ WLn-1 (2 _ WL of FIG. 8), and third-level memory cells 3_ MC. The insulating layer may be interposed between the second-level bit lines 2_ BL0 ~ 2_ BLm-1 (2 _ BL of FIG. 9) and the second-level word lines 2_ WL0 ~ 2_ WLn-1 (2 _ WL of FIG. 8), that is, between the 3_ MCs of the third-level memory cells. The third-stage memory cells 3_ MC, the second-stage word lines 2_ WL 0-2 _ WLn-1 (2 _ WL in FIG. 8), and the second-stage memory cells 2_ MC are located between the first-stage bit lines 1_ BL 0-1 _ BLm-1 (1 _ BL in FIG. 9) and the second-stage bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL in FIG. 9).

The third-level word lines 3_ WL0 ~ 3_ WLn-1 (3 _ WL of FIG. 8) may be arranged and stacked on the second-level bit lines 2_ BL0 ~ 2_ BLm-1 (2 _ BL of FIG. 9). The third level word lines 3_ WL 0-3 _ WLn-1 (3 _ WL of FIG. 8) can intersect the second level bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL of FIG. 9). The fourth-stage memory cells 4_ MC may be arranged at intersections between the second-stage bit lines 2_ BL0 ~ 2_ BLm-1 (2 _ BL of FIG. 9) and the third-stage word lines 3_ WL0 ~ 3_ WLn-1 (3 _ WL of FIG. 8) to define a fourth storage layer DECK 4. The fourth storage layer DECK4 may include: third-level word lines 3_ WL 0-3 _ WLn-1 (3 _ WL in FIG. 8), second-level bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL in FIG. 9), and fourth-level memory cells 4_ MC. The insulating layer may be interposed between the second-level bit lines 2_ BL0 ~ 2_ BLm-1 (2 _ BL of FIG. 9) and the third-level word lines 3_ WL0 ~ 3_ WLn-1 (3 _ WL of FIG. 8), that is, between the fourth-level memory cells 4_ MC. The fourth-level memory cells 4_ MC, the second-level bit lines 2_ BL 0-2 _ BLm-1 (2 _ BL in FIG. 9), and the third-level memory cells 3_ MC are located between the third-level word lines 3_ WL 0-3 _ WLn-1 (3 _ WL in FIG. 8) and the second-level word lines 2_ WL 0-2 _ WLn-1 (2 _ WL in FIG. 8).

According to example embodiments, a memory chip may include four memory layers, i.e., four layers of memory cell arrays. Memory layers may generally share word lines and bit lines of memory layers above or below the corresponding memory layer.

For example, referring to FIG. 8, one end of the first-level word line 1_ WL (and 1_ WL0 ~ 1_ WLn-1 of FIG. 9) and one end of the third-level word line 3_ WL (and 3_ WL0 ~ 3_ WLn-1 of FIG. 9) at a selected row of the selected memory chip T1 may be connected to the row switch transistor SWR at the selected row through a contact CT. One end of the first-level word lines 1_ WL (and 1_ WL0 ~ 1_ WLn-1 of FIG. 9) and one end of the third-level word lines 3_ WL (and 3_ WL0 ~ 3_ WLn-1 of FIG. 9) may be positioned adjacent to the row switch transistors SWR.

At a selected row of the selected memory chip T1, the second-level word line 2_ WL may be connected to the row switch transistors SWR of a corresponding row in another memory chip T2 adjacent in the extending direction of the word line. For example, the other end of the second level word line 2_ WL at the selected row of the selected memory chip T1 may be electrically connected to a row switching transistor SWR for controlling the selected row of the adjacent memory chip T2. The other end of the second level word line 2_ WL of the selected memory chip T1 may not be electrically connected to the row switch transistor SWR of the selected memory chip T1. Accordingly, the first-level word line 1_ WL and the third-level word line 3_ WL at the selected memory chip T1 may be driven by the row switch transistor SWR of the selected memory chip T1. In contrast, the second-level word line 2_ WL of the selected memory chip T1 may be driven by the row switch transistor SWR of another memory chip T2 adjacent to the selected memory chip T1.

The row switch transistor SWR and the first-level word line 1_ WL of the selected memory chip T1 may be electrically connected through at least one contact CT. The first-level word line 1_ WL of the selected memory chip T1 and the second-level word line 2_ WL of an adjacent memory chip (not shown in fig. 8) may be electrically connected through at least one contact CT. The second-level word line 2_ WL of the adjacent memory chip and the third-level word line 3_ WL of the selected memory chip T1 may be electrically connected through at least one contact CT. Fig. 8 shows contacts CT located at the ends of the first-to third-level word lines 1_ WL, 2_ WL, and 3_ WL. However, the contact CT may be located at other positions of 1_ WL, 2_ WL, and 3_ WL from the first-level word line to the third-level word line.

For example, 1_ WL, 2_ WL, and 3_ WL of the first-level to third-level word lines may have substantially the same length for crossing the corresponding memory chip. However, in another embodiment, in order to easily connect the first to third level word lines 1_ WL, 2_ WL, and 3_ WL with the row switching transistor SWR, the first to third level word lines 1_ WL, 2_ WL, and 3_ WL may have different lengths. For example, since the second level word line 2_ WL of the selected memory chip T1 may be connected to the row switching transistor SWR and the first level word line 1_ WL and the third level word line 3_ WL of the second memory chip T2, the second level word line 2_ WL of the first memory chip T1 may be drawn toward the second memory chip T2 (or adjacent memory chips) so as to penetrate a gap between the first memory chip T1 and the second memory chip T2.

Referring to fig. 9, the second-level bit line 2_ BL or the uppermost bit line of the selected column located at the selected memory chip T4 may be electrically connected to the column switch transistor SWC at the selected column through the auxiliary bit line pad 310 and the contact CT. The auxiliary bit line pad 310 may easily connect one end of the second-stage bit line 2_ BL with the column switch transistor SWC in the memory chip T4 through a gap between the memory chip T2 and the memory chip T4.

The second-level bit line 2_ BL at the selected column of the selected memory chip T4 may be electrically connected to the first-level bit line 1_ BL of the corresponding column of the memory chip T2 adjacent to the selected memory chip T4. The memory chip T2 adjacent to the selected memory chip T4 may correspond to a memory chip located adjacent to the column switch transistor SWC of the selected memory chip T4 among the memory chips adjacent in the extending direction of the bit line. Accordingly, the first-level bit line 1_ BL of the selected memory chip T4 may be controlled by the column switch transistor SWC of the adjacent memory chip (not shown), and the second-level bit line 2_ BL of the selected memory chip T4 may be controlled by the column switch transistor SWC of the selected memory chip T4.

The column switch transistor SWC of the selected memory chip T4 and the first-level bit line 1_ BL of the adjacent memory chip may be connected through at least one contact CT. The first-level bit line 1_ BL of the adjacent memory chip and the second-level bit line 2_ BL of the selected memory chip T4 may be electrically connected through at least one contact CT.

The first-level bit line 1_ BL and the second-level bit line 2_ BL may have substantially the same length for crossing the corresponding memory chip. However, in another embodiment, the first-stage bit line 1_ BL and the second-stage bit line 2_ BL may have different lengths in order to easily connect the bit lines with the column switch transistors SWC. For example, since the first-level bit line 1_ BL of the second memory slice T2 may be connected to the column switch transistor SWC of the fourth memory slice T4 and the second-level bit line 2_ BL of the fourth memory slice T4, the first-level bit line 1-BL of the second memory slice T2 may be drawn toward the fourth memory slice T4, thereby penetrating a gap between the second memory slice T2 and the fourth memory slice T4.

Hereinafter, the operation of the resistive memory device may be illustrated in detail.

When the first row of the second chip T2 is selected, the row switching transistor SWR corresponding to the first row may be driven according to a corresponding row address. Accordingly, the first-level word line 1_ WL at the first row of the second chip T2, the third-level word line 3_ WL at the first row of the second chip T2, and the second-level word line 2_ WL at the first row of the first chip T1, which are connected to the row switching transistor SWR at the first row, may be simultaneously enabled.

When a write voltage or a read voltage is applied to select a bit line of a first column of the second chip T2, a column switch transistor SWC at the first column may be driven. Accordingly, a write voltage or a read voltage may be transmitted to the second-stage bit line 2_ BL of the second memory chip T2 connected to the column switch transistor SWC at the first column of the fourth memory chip T4 and the first-stage bit line 1_ BL of the second memory chip T2 connected to the column switch transistor SWC at the first column of the fourth memory chip T4.

Although two word lines of one memory slice are simultaneously selected, one memory slice may select one memory cell because only one bit line of one memory slice may be enabled.

Fig. 10 is a sectional view illustrating an arrangement of bit lines according to an example embodiment. The formation of the word lines and bit lines of this example embodiment may be substantially the same as those previously shown. Thus, any further illustration regarding the formation of word lines and bit lines may be omitted herein for the sake of brevity. Here, the shape of the bit line may be shown.

Referring to fig. 10, the first-level bit line 1_ BLa and the second-level bit lines 2_ BLa and 2_ BLb may be configured to cross two memory slices that are not disconnected. The first-level bit line 1_ BLa and the second-level bit lines 2_ BLa and 2_ BLb crossing both memory slices may overlap each other in only one memory slice. The first-level bit line 1_ Bla and the second-level bit lines 2_ Bla and 2_ BLb extend in units of two memory slices that are not disconnected. Accordingly, the first-level bit lines 1_ Bla and the second-level bit lines 2_ Bla and 2_ BLb are arranged to overlap each other on the selected memory chip in a staggered shape.

For example, the first-level bit lines 1-BLa of the selected column may be arranged on the fourth memory chip T4 and may be positioned at the first side of the second and fourth memory chips T2 and T4 without being separated. The fourth memory chip T4 may be positioned adjacent to the second memory chip T2 in the extending direction of the bit lines. The first-level bit lines 1-BLa may be electrically connected with the column switch transistors SWC (e.g., the column switch transistors SWC of the fourth memory chip T4) located at the center portions of the second and fourth memory chips T2 and T4 via the auxiliary bit line pads 310.

The second-level bit line 2_ BLa may be disposed on the second chip T2 not disconnected and a chip outside the second chip T2 (hereinafter, referred to as a first-side chip). The first side memory chip may be positioned adjacent to the second memory chip T2 in the extending direction of the bit line. The second-level bit line 2-BLa may be electrically connected to the column switch transistor SWC of the second memory chip T2 at the center portion of the second memory chip T2 and the first side memory chip via the auxiliary bit line pad 310.

The second-level bit line 2_ BLb may be disposed on the fourth memory chip T4 not disconnected and a memory chip outside the fourth memory chip T4 (hereinafter, referred to as a second-side memory chip). The second side memory chip may be positioned adjacent to the fourth memory chip T4 in the extending direction of the bit line. The second-level bit line 2_ BLb may be electrically connected to the column switch transistor SWC of the fourth memory chip T4 located at the center portion of the fourth memory chip T4 and the second-side memory chip via the auxiliary bit line pad 310.

According to example embodiments, although the first-level bit lines and the second-level bit lines on one memory slice may be arranged in units of two memory slices, one memory cell may be selected by one memory slice because the first-level bit lines and the second-level bit lines may be controlled by different column switching transistors.

Further, the row switches and the column switches may be arranged in the memory chips so that the gap between the memory chips may be reduced. An auxiliary bit line pad may be formed between the column switch and the first-level word line to ensure a contact margin between the column switch and the bit line.

In addition, the word lines and bit lines in each memory layer may be independently controlled by the control block of the corresponding memory chip and the control block of the adjacent memory chip. Therefore, when a row address and a column address are input into each MAT, one memory cell can be selected by each memory chip.

The above-described embodiments of the present invention are intended to be illustrative, not limiting. Various alternatives and equivalents are possible. The present invention is not limited by the embodiments described herein. Nor is the invention limited to any particular type of semiconductor device. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.