阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 王楠 于 2019-04-12 设计创作，主要内容包括：本发明一种半导体器件及其形成方法,包括步骤：提供衬底,所述衬底包括器件密集区和器件稀疏区,且所述衬底上形成有鳍部；在所述衬底上形成伪栅结构,所述伪栅结构横跨所述鳍部；在所述器件密集区的所述伪栅结构两侧的所述鳍部内形成第一沟槽,同时在所述器件稀疏区的所述伪栅结构两侧的所述鳍部内形成第二沟槽；在所述第一沟槽和所述第二沟槽内形成第一应力层；在所述伪栅结构的侧壁上形成牺牲侧墙；在所述第二沟槽的所述第一应力层上形成第二应力层；去除所述牺牲侧墙；利用在器件稀疏区进行二次外延生长应力层,平衡器件稀疏区和器件密集区的接触电阻,提高半导体器件性能的稳定性。(The invention relates to a semiconductor device and a forming method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a device dense area and a device sparse area, and a fin part is formed on the substrate; forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part; forming first grooves in the fin parts on two sides of the pseudo gate structure in the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure in the device sparse region; forming a first stress layer in the first groove and the second groove; forming a sacrificial side wall on the side wall of the pseudo gate structure; forming a second stress layer on the first stress layer of the second trench; removing the sacrificial side wall; and a stress layer is epitaxially grown in the sparse region of the device for the second time, so that the contact resistance of the sparse region and the dense region of the device is balanced, and the performance stability of the semiconductor device is improved.)

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a device dense area and a device sparse area, and a fin part is formed on the substrate;

forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part;

forming first grooves in the fin parts on two sides of the pseudo gate structure in the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure in the device sparse region;

forming a first stress layer in the first groove and the second groove;

forming a sacrificial side wall on the side wall of the pseudo gate structure;

forming a second stress layer on the first stress layer of the second trench;

and removing the sacrificial side wall.

2. The method of claim 1, wherein the sacrificial sidewall covers the first stress layer in the first trench in the device dense region.

3. The method for forming the semiconductor device according to claim 2, wherein the material of the sacrificial side wall comprises one or more of silicon nitride, silicon oxide, silicon carbide and silicon carbonitride.

4. The method for forming the semiconductor device according to claim 1, wherein the second stress layer is formed by an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, a process temperature is 500 to 800 ℃, a reaction chamber pressure is 1 to 100 torr, and a reaction gas is silane.

5. A semiconductor device formed by the method of any of claims 1 to 4, comprising:

a substrate comprising a device dense region and a device sparse region;

a fin portion on the substrate;

the dummy gate structure is positioned on the substrate and spans the fin part;

the first groove is positioned in the fin parts at two sides of the pseudo gate structure of the device dense region;

the second groove is positioned in the fin parts on two sides of the pseudo gate structure in the device sparse area;

a first stress layer located in the first trench and the second trench;

and the second stress layer is positioned on the first stress layer in the second groove.

6. A method of forming a semiconductor device, comprising,

providing a substrate, wherein the substrate comprises a device dense area and a device sparse area, and a fin part is formed on the substrate;

forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part;

forming first grooves in the fin parts on two sides of the pseudo gate structure in the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure in the device sparse region;

forming a sacrificial side wall on the side wall of the pseudo gate structure of the device dense region;

forming a second stress layer in the second groove;

removing the sacrificial side wall;

and forming a first stress layer in the first groove and on the second stress layer.

7. The method for forming the semiconductor device according to claim 6, wherein the sacrificial sidewall covers the first trench in the device dense region.

8. The method for forming a semiconductor device according to claim 6, wherein when the semiconductor device is a POMS device, the second stress layer is formed by an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500 to 800 ℃, the pressure in the reaction chamber is 1 to 100 torr, and the reaction gas includes silane and a germanosilicide gas.

9. The method for forming a semiconductor device according to claim 6, wherein when the semiconductor device is an NOMS device, the second stress layer is formed by an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500 to 800 ℃, the pressure in the reaction chamber is 1 to 100 torr, and the reaction gas includes silane and phosphine gas.

10. A semiconductor device formed by the method of any of claims 6 to 9, comprising:

a substrate comprising a device dense region and a device sparse region;

a fin portion on the substrate;

the dummy gate structure is positioned on the substrate and spans the fin part;

the first groove is positioned in the fin parts at two sides of the pseudo gate structure of the device dense region;

the second groove is positioned in the fin parts on two sides of the pseudo gate structure in the device sparse area;

the second stress layer is positioned in the second groove;

and the first stress layer is positioned in the first groove and on the second stress layer.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.

In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation structure which are positioned on the surface of a semiconductor substrate, wherein the isolation structure covers part of the side wall of the fin part and is positioned on the substrate and crossed with a grid structure; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.

However, as the size of semiconductor devices is reduced and the device density is increased, the performance of the formed fin field effect transistor is unstable.

Disclosure of Invention

The invention provides a semiconductor device and a forming method thereof, which can stabilize the performance of the formed semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, wherein the substrate comprises a device dense area and a device sparse area, and a fin part is formed on the substrate; forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part; forming first grooves in the fin parts on two sides of the pseudo gate structure in the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure in the device sparse region; forming a first stress layer in the first groove and the second groove; forming a sacrificial side wall on the side wall of the pseudo gate structure; forming a second stress layer on the first stress layer of the second trench; and removing the sacrificial side wall.

Optionally, in the device dense region, the sacrificial sidewall covers the first stress layer in the first trench.

Optionally, the material of the sacrificial side wall includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, an organic substance, or a metal.

Optionally, a method for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas is silane.

A semiconductor device formed using the above method, comprising: a substrate comprising a device dense region and a device sparse region; a fin portion on the substrate; the dummy gate structure is positioned on the substrate and spans the fin part; the first groove is positioned in the fin parts at two sides of the pseudo gate structure of the device dense region; the second groove is positioned in the fin parts on two sides of the pseudo gate structure in the device sparse area; a first stress layer located in the first trench and the second trench; and the second stress layer is positioned on the first stress layer in the second groove.

The invention also provides another method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a device dense area and a device sparse area, and a fin part is formed on the substrate; forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part; forming first grooves in the fin parts on two sides of the pseudo gate structure in the device dense region, and forming second grooves in the fin parts on two sides of the pseudo gate structure in the device sparse region; forming a sacrificial side wall on the side wall of the pseudo gate structure of the device dense region; forming a second stress layer in the second groove; removing the sacrificial side wall; and forming a first stress layer in the first groove and on the second stress layer.

Optionally, in the device dense region, the sacrificial side wall covers the first trench.

Optionally, the semiconductor device is a POMS device, the method for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas includes silane and germanide gas.

Optionally, the semiconductor device is an NOMS device, the method for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 500-800 ℃, the pressure of the reaction chamber is 1-100 torr, and the reaction gas includes silane and phosphine gas.

A semiconductor device formed using the above method, comprising: a substrate comprising a device dense region and a device sparse region; a fin portion on the substrate; the dummy gate structure is positioned on the substrate and spans the fin part; the first groove is positioned in the fin parts at two sides of the pseudo gate structure of the device dense region; the second groove is positioned in the fin parts on two sides of the pseudo gate structure in the device sparse area; the second stress layer is positioned in the second groove; and the first stress layer is positioned in the first groove and on the second stress layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

stress layers are formed in the grooves of the device sparse area twice, the volume of the stress layers formed in the grooves of the device sparse area is increased, and when contact holes are formed subsequently, the contact area between the contact holes and the source and drain is increased conveniently, so that the contact resistance is reduced; meanwhile, after the stress layers are formed in the grooves of the device sparse area twice, contact resistance formed in the device sparse area and contact resistance formed in the device dense area can be balanced in the subsequent use process of the semiconductor device, so that the stability of the semiconductor device is improved, and the contact resistance is reduced.

Drawings

Fig. 1 to 4 are schematic structural views of a semiconductor device formation process;

fig. 5 to 12 are schematic structural views of a semiconductor device formation process in the first embodiment of the present invention;

fig. 13 to 20 are schematic structural views of a semiconductor device formation process in a second embodiment of the present invention;

fig. 21 to 30 are schematic structural views of a semiconductor device formation process in a third embodiment of the present invention;

Detailed Description

The performance stability of the semiconductor devices formed at present is poor.

Fig. 1 to 4 are schematic structural views of a semiconductor device formation process.

Referring to fig. 1, a substrate 100 is provided, including a device dense region 110, a device sparse region 120, and a fin 130.

Referring to fig. 2, a dummy gate structure 140 is formed on the substrate 100.

The dummy gate structure 140 crosses the fin 130.

Referring to fig. 3, a first trench 111 and a second trench 121 are formed in the fin 130 at both sides of the dummy gate structure 140.

Referring to fig. 4, a first stress layer 112 and a second stress layer 122 are epitaxially grown in the first trench 111 and the second trench 121, respectively.

The inventors have found that, when the first stress layer 112 is epitaxially grown in the first trench 111, the first stress layer 112 grows fast, and the volume of the formed first stress layer 112 is large, because the first stress layer 112 grows on the bottom and the sidewall of the first trench 111 simultaneously; when the second stress layer 122 is epitaxially grown in the second trench 121, the volume of the second stress layer 122 formed is smaller, which is because when the second stress layer 122 is epitaxially grown in the second trench 121, the second stress layer 122 only grows at the bottom of the second trench 121, the growth speed is slower, the volume of the second stress layer 122 formed is smaller, the growth speeds of the first stress layer 112 and the second stress layer 122 are not balanced, so that when contact holes are formed again in the subsequent process, the contact resistance formed in the device dense region 110 is smaller, the contact resistance formed in the device sparse region 120 is larger, the contact resistances of the device sparse region and the device dense region are not balanced, and the instability of the use performance of the semiconductor device is easily caused in the use process of the semiconductor device.

The inventor researches and discovers that the volume of the stress layer in the sparse region of the device can be increased by performing stress layer growth twice in the groove of the sparse region of the device, when contact holes are formed subsequently, the contact area between the contact holes and the source and drain can be increased due to the fact that the volume of the stress layer formed in the sparse region of the device is increased, the larger the contact area is, the smaller the contact resistance formed in the sparse region of the device is, the balance between the contact resistance and the contact resistance in the dense region of the device can be achieved, and therefore the stability of the performance of the semiconductor device can be improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

First embodiment

Fig. 5 to 12 are schematic structural views of a semiconductor device formation process in the first embodiment of the present invention.

Referring first to fig. 5, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.

In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.

Referring to fig. 6, a fin 300 is formed on the substrate 200.

The method of forming the fin 300 includes: forming a photoresist layer on the substrate 200; forming a photoresist pattern in the photoresist layer after exposure and development processes; and etching the substrate 200 by using the patterned photoresist layer as a mask, thereby forming the fin portion 300 on the substrate 200.

Referring to fig. 7, a dummy gate structure 400 is formed on the substrate 200, wherein the dummy gate structure 400 crosses the fin 300.

In this embodiment, the material of the dummy gate structure 400 is polysilicon; in other embodiments, the material of the dummy gate structure 400 may also be amorphous carbon or silicon nitride.

The method of forming the dummy gate structure 400 includes: forming a gate oxide layer (not shown in the figure) on the surface of the substrate 200, forming a gate layer on the gate oxide layer, and forming a patterned layer on the gate layer, wherein the patterned layer covers a corresponding region where the dummy gate structure 400 is to be formed; and etching the gate layer and the gate oxide layer by using the patterned layer as a mask until reaching the substrate 200.

The grid oxide layer is made of silicon oxide; the gate oxide layer may be formed in a thermal oxidation process, an atomic deposition process, or a chemical vapor deposition process.

In this embodiment, the gate layer is removed and replaced with a gate dielectric layer of a high-K dielectric material and a gate layer of a metal material.

Referring to fig. 8, first trenches 211 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device dense region 210, while second trenches 221 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device sparse region 220.

In this embodiment, the method for forming the first trench 211 and the second trench 221 is dry etching; the parameters of the dry etching include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.

In other embodiments, the method for forming the first trench 211 and the second trench 221 is anisotropic wet etching, and a suitable etching method may be selected according to actual needs.

Referring to fig. 9, a first stress layer 230 is formed within the first trench 211 and within the second trench 221.

In this embodiment, the first stress layer 230 is formed by an epitaxial growth method; in other embodiments, the method of forming the first stress layer 230 is not limited to epitaxial growth.

In this embodiment, when the semiconductor device is a POMS device, the process conditions for forming the first stress layer 230 are to control the temperature within a range of 500 to 800 ℃, the pressure within a range of 1 to 100 torr, and the selected gas includes Silane (SiH)₄) And hydrogen germanide gas (GeH)₄) The flow rate of the mixed gas is controlled within the range of 70-300 sccm and the time is controlled within the range of 3-120 s.

In this embodiment, when the semiconductor device is NOMSWhen the device is formed, the first stress layer 230 is formed under the process conditions that the temperature is controlled within the range of 500-800 ℃, the pressure is controlled within the range of 1-100 torr, and the selected gas comprises Silane (SiH)₄) And phosphine gas (PH)₃) The flow rate of the mixed gas is controlled within the range of 70-300 sccm and the time is controlled within the range of 3-120 s.

Referring to fig. 10, sacrificial spacers 500 are formed on sidewalls of the dummy gate structure 400.

In this embodiment, the sacrificial spacer 500 covers the first stress layer 230 in the first trench 211.

In this embodiment, the thickness of the sacrificial side wall 500 in the device dense region is 15 to 30 nanometers; when the thickness of the sacrificial side wall 500 is less than 15 nm, the sacrificial side wall 500 adjacent to the side wall of the dummy gate structure 400 cannot fully cover the first stress layer 230 formed in the first trench 211, so that when the subsequent re-epitaxial growth is caused, a stress layer is further formed in the first trench 211, and the volume of the first stress layer 230 is increased; when the thickness of the sacrificial side wall 500 is greater than 30 nm, the sacrificial side wall 500 is too thick, which results in resource waste.

In this embodiment, the thicknesses of the sacrificial side walls 500 formed in the device dense region 210 and the device sparse region 220 are different; in other embodiments, the thickness of the sacrificial spacer 500 may be the same in the device dense region 210 and the device sparse region 220.

In this embodiment, the sacrificial spacer 500 is made of silicon nitride; in other embodiments, the material of the sacrificial sidewall 500 may also be one or more of silicon oxide, silicon carbide, silicon carbonitride, organic matters, or metals.

In this embodiment, the purpose of the sacrificial spacer 500 is to cover the first stress layer 230 formed in the first trench 211, so as to prevent the stress layer from growing again in the first trench 211 when performing epitaxial growth again in the subsequent process.

Referring to fig. 11, a second stress layer 240 is formed on the first stress layer 230 of the second trench 221.

In this embodiment, the second stress layer 240 is formed by an epitaxial growth method, and the reaction gas includes Silane (SiH)₄) Or Silane (SiH)₄) And hydrogen germanide gas (GeH)₄) Combined gas of (3) or Silane (SiH)₄) And phosphine gas (PH)₃) The combined gas of (1).

In this embodiment, the method for forming the second stress layer 240 is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer 240, the process temperature is 500 to 800 ℃, the pressure of the reaction chamber is 1 to 100 torr, and the reaction gas is Silane (SiH)₄) The reaction time is controlled to be 3-120 s.

In this embodiment, the reaction gas for forming the second stress layer 240 is Silane (SiH)₄) In order to simplify the process and increase the production efficiency, Silane (SiH) is used₄) The second stress layer 240 can be formed without applying stress, and the second stress layer 240 is suitable for being formed in both the device sparse region of the POMS device and the device sparse region of the NOMS device, so that the production process can be simplified, and the production efficiency can be improved; with simultaneous use of Silane (SiH)₄) The pressure of the epitaxial growth of the POMS device or the NOMS device is not influenced.

In this embodiment, the purpose of forming the second stress layer 240 on the first stress layer 230 of the second trench 221 is to increase the volume of the stress layer in the second trench 221 in the device sparse region 220, so that when contact holes are formed subsequently, the contact area between the contact holes and the source and drain is increased, and the contact resistance in the device sparse region 220 is reduced, so that the contact resistance and the contact resistance in the device dense region reach a balance, and thus, in the use process of a semiconductor device, the use stability of the semiconductor device is not affected due to too large difference between the contact resistances in the device sparse region and the device dense region.

Referring to fig. 12, the sacrificial sidewall spacers 500 are removed.

In this embodiment, the method for removing the sacrificial side wall 500 may adopt ashing; in other embodiments, the sacrificial spacer 500 may be removed by wet etching or other processes.

A semiconductor device formed using the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; the first trench 211 is located in the fin portion 300 on two sides of the dummy gate structure 400 in the device dense region 210; a second trench 221 located in the fin 300 on both sides of the dummy gate structure 400 in the device sparse region 220; a first stress layer 230 located in the first trench 211 and the second trench 221; a second stress layer 240 on the first stress layer 230 in the second trench 221.

Second embodiment

Fig. 13 to 20 are schematic structural views of a semiconductor device formation process in a second embodiment of the present invention.

Referring to fig. 13, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.

Referring to fig. 14, a fin 300 is formed on the substrate 200.

In this embodiment, the steps of forming the fin portion 300 are the same as those in the first embodiment; in other embodiments, different methods may be used to form the fin 300.

Referring to fig. 15, a dummy gate structure 400 is formed on the substrate 200, wherein the dummy gate structure 400 crosses the fin 300.

In this embodiment, the method of forming the dummy gate structure 400 is the same as that in the first embodiment; in other embodiments, other methods may be used to form the dummy gate structure 400.

Referring to fig. 16, first trenches 211 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device dense region 210, and second trenches 221 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device sparse region 220.

In this embodiment, the fin portion 300 is etched by a wet etching process, and the parameters of the wet etching process include：HNO₃And an aqueous solution of HF, wherein HNO3, HF and H₂The volume ratio of O is 1: 3: (10-800) and the temperature is 40-90 ℃.

In other embodiments, the method of etching the fin 300 may be set according to actual process requirements.

Referring to fig. 17, sacrificial spacers 500 are formed on sidewalls of the dummy gate structure 400 of the device dense region 210.

In this embodiment, the first trench 211 is filled with the sacrificial sidewall 500, so that the first trench 211 is covered first, and a stress layer is not formed in the first trench 211 in a subsequent epitaxial growth process.

In this embodiment, the sacrificial spacer 500 is made of silicon carbonitride; in other embodiments, the material of the sacrificial sidewall 500 may also be one or more of silicon oxide, silicon carbide, silicon nitride, organic matter, or metal.

Referring to fig. 18, a second stress layer 240 is formed within the second trench 221.

In this embodiment, the second stress layer 240 is formed by an epitaxial growth method, and the reaction gas includes Silane (SiH)₄) Or Silane (SiH)₄) And hydrogen germanide gas (GeH)₄) Combined gas of (3) or Silane (SiH)₄) And phosphine gas (PH)₃) The combined gas of (1).

In this embodiment, the process temperature, the chamber pressure and the reaction time for forming the second stress layer 240 are the same as those in the first embodiment; in other embodiments, different process conditions may be used.

Referring to fig. 19, the sacrificial sidewall spacers 500 are removed.

In this embodiment, the sacrificial spacer 500 is removed by using a chemical reagent.

Referring to fig. 20, a first stress layer 230 is formed within the first trench 211; a first stress layer 230 is formed on the second stress layer 240.

In this embodiment, the process conditions for forming the first stress layer 230 are the same as those in the first embodiment; in other embodiments, different process conditions may be used to form the first stress layer 230.

A semiconductor device formed using the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; the first trench 211 is located in the fin portion 300 on two sides of the dummy gate structure 400 in the device dense region 210; a second trench 221 located in the fin 300 on both sides of the dummy gate structure 400 in the device sparse region 220; a second stress layer 240 located in the second trench 221; a first stress layer 230 located in the first trench 211 and on the second stress layer 240.

Third embodiment

Fig. 21 to 30 are schematic structural views of a semiconductor device formation process in a third embodiment of the present invention.

In this embodiment, the device is a POMS device.

Referring to fig. 21, a substrate 200 is provided, the substrate 200 including a device dense region 210 and a device sparse region 220.

Referring to fig. 22, a fin 300 and an isolation structure 600 are formed on the substrate 200.

In this embodiment, an isolation structure 600 is formed on the substrate 200; in other embodiments, the isolation structure 600 may not be formed on the substrate 200.

In this embodiment, the isolation structure 600 may be a shallow trench isolation structure, but is not limited to a shallow trench isolation structure. The isolation structure 600 is used to achieve mutual isolation between devices.

The step of forming the isolation structure 600 includes etching the substrate 200 to form an isolation trench (not shown) in the semiconductor substrate 200; and filling an isolation material into the isolation trench, and flattening the isolation material to form the isolation structure 600.

The isolation material may be silicon oxide, and the process of filling silicon oxide into the isolation trench may be a chemical vapor deposition method or a physical vapor deposition method.

Referring to fig. 23, a dummy gate structure 400 is formed on the substrate 200, and the dummy gate structure 400 crosses the fin 300.

In this embodiment, the method of forming the dummy gate structure 400 is the same as that of the first embodiment.

Referring to fig. 24, a mask layer 401 is formed on the dummy gate structure 400.

In this embodiment, a mask layer 401 is further formed on the dummy gate structure 400; in other embodiments, the mask layer 401 may not be formed on the dummy gate structure 400.

In this embodiment, the mask layer 401 is made of silicon carbide; in other embodiments, the mask layer 301 may also be silicon oxide or silicon nitride.

Referring to fig. 25, a sidewall spacer 402 is formed on the sidewall of the dummy gate structure 400.

In this embodiment, after forming the dummy gate structure 400, forming a sidewall spacer 402 on the sidewall of the dummy gate structure 400; in other embodiments, the sidewall spacers 402 may not be formed on the sidewalls of the dummy gate structure 400.

The side wall 402 is used for defining the position of a source-drain doped layer formed subsequently, and the side wall 302 is used for protecting the side wall of the pseudo gate structure 400, so that the influence of topography defects on a subsequently formed gate layer on the electrical performance of a semiconductor structure is avoided.

In this embodiment, the material of the sidewall 402 is silicon oxide; in other embodiments, the material of the sidewall spacers 402 may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

Referring to fig. 26, first trenches 211 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device dense region 210, and second trenches 221 are formed in the fins 300 on both sides of the dummy gate structure 400 in the device sparse region 220.

Referring to fig. 27, sacrificial spacers 500 are formed on the sidewalls of the spacers 402 of the device dense region 210.

In this embodiment, the sacrificial spacer 500 covers the first trench 211.

Referring to fig. 28, a second stress layer 240 is formed within the second trench 221.

In this embodiment, the second stress layer 240 is formed by epitaxial growth, and the reaction gas is Silane (SiH)₄) And hydrogen germanide gas (GeH)₄) The combined gas of (1); wherein the reaction temperature is controlled to be 500-800 ℃, the pressure of the chamber is controlled to be 1-100 torr, and the reaction time is controlled to be 3-120 s.

In this embodiment, the first epitaxial growth is performed in the second trench 221 in the device sparse region 220 to increase the volume of the stress layer in the second trench 221, so that the volume of the stress layer epitaxially grown in the second trench 221 can be balanced with the volume of the stress layer in the first trench 211 during the subsequent second epitaxial growth, and when a contact hole is formed, the contact resistance of the device sparse region 220 can be balanced with the contact resistance of the device dense region 210, thereby improving the stability of the use performance of the semiconductor device.

Referring to fig. 29, the sacrificial sidewall spacers 500 are removed.

In this embodiment, the sacrificial spacer 500 is removed by ashing.

Referring to fig. 30, a first stress layer 230 is formed within the first trench 211; a first stress layer 230 is formed on the second stress layer 240.

In this embodiment, the first stress layer 230 located on the second stress layer 240 is formed by performing secondary epitaxial growth in the device sparse region 220, so that the volume of the stress layer grown in the second trench 221 and the volume of the stress layer grown in the first trench 211 are balanced, thereby balancing the contact resistance formed in the device sparse region 220 and the device dense region 210, and improving the stability of the performance of the semiconductor device.

A semiconductor device formed using the above method, the semiconductor device comprising a substrate 200, the substrate 200 comprising a device dense region 210 and a device sparse region 220; a fin 300 on the substrate 200; an isolation structure 600 on the substrate 200; a dummy gate structure 400 on the substrate 200, crossing the fin 300; a mask layer 401 located on the top of the dummy gate structure 400; a sidewall 402 located on a sidewall of the dummy gate structure 400; the first trench 211 is located in the fin portion 300 on two sides of the sidewall 402 of the device dense region 210; a second trench 221 located in the fin 300 on both sides of the dummy gate structure 400 in the device sparse region 220; a second stress layer 240 located in the second trench 221; a first stress layer 230 located in the first trench 211 and on the second stress layer 240.

Fourth embodiment

The fourth embodiment is different from the third embodiment only in the method of forming the second stress layer 240.

In this embodiment, the device is an NOMS device.

In this embodiment, the method for forming the second stress layer is an epitaxial growth method, and in the epitaxial growth method for forming the second stress layer, the process temperature is 50 to 800 ℃, the pressure of the reaction chamber is 1 to 100 torr, and the reaction gas includes Silane (SiH)₄) And phosphine gas (PH)₃) The reaction time is 3-120 s.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.