Oscillator circuit
阅读说明：本技术 振荡器电路 (Oscillator circuit ) 是由 松野典朗 于 2020-04-17 设计创作，主要内容包括：本申请涉及振荡器电路。提供了一种小面积振荡器电路。该振荡器电路包括第一恒流源和第二恒流源、比较器、第一电容元件和第二电容元件以及电阻元件。在第一状态下,第一电容元件连接到第一恒流源和固定电压节点,第二电容元件连接到第二恒流源和第一电流源,电阻元件连接到第二恒流源。在第二状态下,第一电容元件连接到第二恒流源和第一恒流源,第二电容元件连接到第二恒流源和固定电压节点,电阻元件连接到第一恒流源。(The present application relates to oscillator circuits. A small area oscillator circuit is provided. The oscillator circuit includes first and second constant current sources, a comparator, first and second capacitance elements, and a resistance element. In the first state, the first capacitive element is connected to the first constant current source and the fixed voltage node, the second capacitive element is connected to the second constant current source and the first current source, and the resistive element is connected to the second constant current source. In the second state, the first capacitive element is connected to the second constant current source and the first constant current source, the second capacitive element is connected to the second constant current source and the fixed voltage node, and the resistive element is connected to the first constant current source.)
1. An oscillator circuit, comprising:
a first constant current source;
a second constant current source;
a comparator having a first input terminal connected to the first constant current source and a second input terminal connected to the second constant current source;
a first capacitive element having a first terminal and a second terminal;
a second capacitive element having a third terminal and a fourth terminal;
a resistive element having a fifth terminal connected to one of the first and second constant current sources and a sixth terminal connected to a fixed voltage node; and
wherein in a first state, the first terminal is connected to the first constant current source, the second terminal is connected to the fixed voltage node, the third terminal is connected to the second constant current source, the fourth terminal is connected to the first current source, the fifth terminal is connected to the second constant current source, and
wherein in a second state, the first terminal is connected to the second constant current source, the second terminal is connected to the first constant current source, the third terminal is connected to the second constant current source, the fourth terminal is connected to the fixed voltage node, and the fifth terminal is connected to the first constant current source.
2. The oscillator circuit according to claim 1, further comprising a switch control circuit that controls a connection relationship of the first constant current source, the second constant current source, the fixed voltage node, the first capacitive element, the second capacitive element, and the resistive element based on an output signal of the comparator.
3. An oscillator circuit, comprising:
a first constant current source;
a second constant current source;
a comparator having one input terminal connected to the first constant current source and the other input terminal connected to the second constant current source;
a first capacitive element;
a second capacitance element;
a resistance element having one side connected to one of the first constant current source and the second constant current source and the other terminal connected to the fixed voltage node; and
a switch control circuit that controls a connection relationship of the first constant current source, the second constant current source, the fixed voltage node, the first capacitive element, the second capacitive element, and the resistive element based on an output signal of the comparator;
wherein the switch control circuit switches a first state and a second state,
wherein in the first state, one side of the first capacitance element is connected to the first constant current source, the other side of the first capacitance element is connected to the fixed voltage node, one side of the second capacitance element is connected to the second constant current source, the other side of the second capacitance element is connected to the first current source, and the one side of the resistance element is connected to the second constant current source, and
wherein, in the second state, the one side of the first capacitive element is connected to the second constant current source, the other side of the first capacitive element is connected to the first constant current source, the one side of the second capacitive element is connected to the second constant current source, the other side of the second capacitive element is connected to the fixed voltage node, and the one side of the resistive element is connected to the first constant current source.
4. The oscillator circuit of claim 3,
wherein polarities of currents flowing through the first capacitive element are opposite to each other in the first state and in the second state, and
wherein polarities of currents flowing through the second capacitive element are opposite to each other in the first state and in the second state.
5. The oscillator circuit of claim 3,
wherein when transitioning from the first state to the second state, a polarity of a current flowing through the first capacitive element is reversed, and
wherein a polarity of a current flowing through the second capacitive element is reversed when transitioning from the second state to the first state.
6. The oscillator circuit according to any one of claims 3 to 5,
wherein the resistance element is a variable resistance element whose resistance value is adjustable.
7. An oscillator circuit, comprising:
a first constant current source for supplying a first constant current,
a second constant current source for supplying a second constant current,
a comparator, comprising:
an input terminal connected to said first constant current source; and
another input terminal connected to the second constant current source;
a first capacitive element;
a second capacitance element;
a resistive element, comprising:
a side connected to one side of the first constant current source and the second constant current source;
the other side connected to the fixed voltage node,
a switch control circuit that controls connection of the first capacitive element, the second capacitive element, and the resistive element;
wherein the switch control circuit switches first to fourth states according to an output of the comparator,
wherein in a first state, one side of the first capacitance element is connected to the first constant current source, the other side of the first capacitance element is connected to the fixed voltage node, one side of the second capacitance element is connected to the second constant current source, the other side of the second capacitance element is connected to the first constant current source, and the one side of the resistance element is connected to the second constant current source,
wherein in a second state, one side of the first capacitive element is connected to the first constant current source, the other side of the first capacitive element is connected to the second constant current source, one side of the second capacitive element is connected to the fixed voltage node, the other side of the second capacitive element is connected to the second constant current source, and the one side of the resistive element is connected to the first constant current source,
wherein in a third state, one side of the first capacitive element is connected to the fixed voltage node, the other side of the first capacitive element is connected to the first constant current source, one side of the second capacitive element is connected to the first constant current source, the other side of the second capacitive element is connected to the second constant current source, and the one side of the resistive element is connected to the second constant current source, and
wherein in a fourth state, one side of the first capacitive element is connected to the second constant current source, the other side of the first capacitive element is connected to the first constant current source, one side of the second capacitive element is connected to the second constant current source, the other side of the second capacitive element is connected to the fixed voltage node, and the one side of the resistive element is connected to the first constant current source.
Technical Field
The present invention relates to an oscillator circuit.
Background
The clock oscillator circuit is built in a semiconductor device such as a general microcomputer. A clock oscillator circuit is a circuit for generating a clock signal for defining operations of internal blocks such as a CPU (central processing unit) and peripheral functional blocks.
In order to reduce the size and cost of the device, a so-called on-chip oscillator (configured without external components such as a crystal oscillator) may be used for the clock oscillator circuit. In general, the frequency accuracy of an on-chip oscillator is lower than that of a clock oscillator circuit using an external oscillator. Therefore, the application of the on-chip oscillator is limited.
The disclosed techniques are listed below.
<
The clock oscillator circuit of
T＝2RC (1)
Disclosure of Invention
However, the oscillator circuit disclosed in
The present disclosure is to solve the above-described problems, and provides an oscillator circuit having a small area. Other objects and novel features will become apparent from the description of the specification and drawings.
Means for solving the problems
According to one embodiment, an oscillator circuit includes: a first constant current source; a second constant current source; a comparator having one input terminal connected to the first constant current source and the other input terminal connected to the second constant current source; a first capacitive element; a second capacitance element; a resistance element having one terminal connected to one of the first constant current source and the second constant current source and the other terminal connected to a fixed voltage node; and a switch control circuit for controlling a connection relationship between the first and second constant current sources, the fixed voltage node, the first and second capacitance elements, and the resistance element. The switch control circuit switches between a first state in which one of the first capacitance elements is connected to the first constant current source and the other is connected to the fixed voltage node, and a second state in which one of the second capacitance elements is connected to the second constant current source and the other is connected to the first constant current source, and one side of the resistor element is connected to the second constant current source; in the second state, one of the first capacitive elements is connected to the second constant current source and the other is connected to the second constant current source, one of the second capacitive elements is connected to the second constant current source and the other is connected to the fixed voltage node, and one side of the resistor element is connected to the first constant current source, in accordance with the output of the comparator.
ADVANTAGEOUS EFFECTS OF INVENTION
According to one embodiment, the RC time constant of the oscillator circuit for realizing the same frequency can be made smaller than that of the comparative example. The area of at least one of the resistance element and the capacitance element may be reduced to reduce the area of the oscillator circuit.
Drawings
Fig. 1 is a diagram showing the configuration of an
Fig. 2 is a diagram for explaining an equivalent circuit when the positive phase clock signal CLK of the
Fig. 3 is a diagram for explaining an equivalent circuit when the inverted clock signal CLKB of the
Fig. 4 is a diagram showing changes in the potentials of the nodes NX and NY of the
Fig. 5 is a diagram showing voltage conversion between terminals of the capacitive elements C1 and C2 of the
Fig. 6 is a diagram showing the configuration of an
Fig. 7 is a circuit diagram for explaining a circuit configuration of a decoder DC according to the second embodiment.
Fig. 8 is a diagram for explaining the switch control signals S0 through S11 output from the decoder DC according to the second embodiment.
Fig. 9 is a diagram showing an equivalent circuit of a first connection state of the
Fig. 10 is a diagram showing an equivalent circuit of a second connection state of the
Fig. 11 is a diagram showing an equivalent circuit of a third connection state of the
Fig. 12 is a diagram showing an equivalent circuit of a fourth connection state of the
Fig. 13 is a diagram showing changes in the potentials of the nodes NX and NY of the
Fig. 14 is a diagram showing transition of the voltage between the terminals of the capacitive elements C1 and C2 of the
Fig. 15 is a diagram for explaining a state when the
Fig. 16 is a diagram for explaining a state when the second connection state of the
Detailed Description
In the drawings, the same or corresponding components are denoted by the same reference numerals, and the description thereof will not be repeated.
< first embodiment >
Fig. 1 is a diagram showing the configuration of an
Referring to fig. 1, an
The comparison unit CMP includes a comparator CP and inverters IV0 and IV 1. The inverter IV0 inverts the output of the comparator CP to output the non-inverted clock signal CLK.
The inverter IV1 inverts the input of the inverter IV0 and outputs the inverted clock signal CLKB.
One of the capacitor elements C1 is a node NA0, and the other is a
For example, the current sources CS1, CS2 are configured by a current mirror circuit using MOS transistors.
The switches SW1 to SW6 are composed of MOS transistors, for example. The current source CS1 is connected between the power supply node (power supply voltage VDD) and the node NX, and supplies a constant current Ic.
The current source CS2 is connected between the power supply node (power supply voltage VDD) and the node NY, and supplies a constant current Ic.
One input terminal of the comparator CP is connected to the node NX, and the other input terminal is connected to the node NY. The comparator CP compares the potential of the node NX with the potential of the node NY, and outputs a signal corresponding to the comparison result.
The node NA0 of the capacitive element C1 is connected to the node NX. The node NA1 of the capacitive element C1 is connected to the fixed voltage VSS (fixed voltage node) via the switch SW 3. The switch SW3 receives the non-inverted clock signal CLK.
Node NB0 of capacitive element C2 is connected to node NY. The node NB1 of the capacitive element C2 is connected to a fixed voltage VSS (fixed voltage node) via the switch SW 4. Switch SW4 receives inverted clock signal CLKB.
The switch SW1 is connected between node NX and node NC and receives an input of the inverted clock signal CLKB.
The switch SW2 is connected between the node NY and the node NC, and receives an input of the non-inverted clock signal CLK.
The switch SW5 is connected between node NA1 and node NB0 and receives an input of the inverted clock signal CLKB.
The switch SW6 is connected between the node NA0 and the node NB1, and receives an input of the non-inverted clock signal CLK.
The switches SW1 to SW6 constitute a switch control circuit for controlling the connection relationship between the current sources CS1, CS2 and a fixed voltage node (fixed voltage VSS), the capacitance elements C1, C2 and the resistance element R1.
The resistance element R1 is connected between the node NC and a fixed voltage node (fixed voltage VSS). The resistance element R1 is a variable resistance element whose resistance value is adjustable. The oscillation frequency can be adjusted by adjusting the resistance value. The oscillation frequency can be adjusted not only by adjusting the resistance value but also by adjusting the capacitance values of the capacitive elements C1 and C2. Specifically, the capacitance values of the capacitive elements C1 and C2 may also be adjusted by adding an adjustment mechanism to the capacitive elements C1 and C2, or the oscillation frequency may be adjusted by adjusting the capacitance values of the capacitive elements C1 and C2 and the resistance value of the resistive element R1.
(operation of oscillator circuit) next, the operation of the oscillator circuit will be described.
The switches SW1, SW4, and SW5 are controlled by the inverted clock signal CLKB, and are controlled to be turned on when, for example, the inverted clock signal CLKB is at a high level.
The switches SW2, SW3, and SW6 are controlled by the positive phase clock signal CLK, and are controlled to be turned on when, for example, the positive phase clock signal CLK is at a high level.
When the positive phase clock signal CLK is at the high level, the switches SW2, SW3, and SW6 are turned on, and the switches SW1, SW4, and SW5 are turned off. When the inverted clock signal CLK is at a high level, the switches SW2, SW3, and SW6 are turned off, and the switches SW1, SW4, and SW5 are turned on.
Fig. 2 is a diagram for explaining an equivalent circuit when the positive phase clock signal CLK of the
As shown in fig. 2, the capacitor element C1 is charged by a 0.5Ic current of a constant current Ic supplied from the
The remaining 0.5Ic of the constant current I supplied from the current source CS1 discharges the electric charge stored in the capacitance element C2.
A current 1.5Ic (the sum of the current 0.5Ic discharged from the capacitive element C2 and the current Ic supplied from the current source CS 2) flows to the resistive element R1.
As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1.
When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the high level to the low level. The inverted clock signal CLKB output from the inverter IV1 changes from a low level to a high level.
Fig. 3 is a diagram for explaining an equivalent circuit when the inverted clock signal CLKB of the
As shown in fig. 3, in the constant current Ic supplied by the current source CS2, the capacitive element C2 is charged with a current of 0.5 Ic. As a result, the potential of the node NB0 rises in proportion to time.
The remaining current 0.5Ic of the constant current Ic supplied from the current source CS2 discharges the electric charge stored in the capacitance element C1.
A current 1.5Ic (which is the sum of the current 0.5I discharged from the capacitive element C1 and the current Ic supplied from the current source CS 1) flows to the resistive element R1.
As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing to the resistance element R1.
When the potential of the node NY rising with time reaches the potential of the node NX, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the low level to the high level. The inverted clock signal CLKB output from the inverter IV1 changes from a high level to a low level.
Thus, the positive phase clock signal CLK repeats transitions from the high level to the low level and from the low level to the high level. Therefore, the
Fig. 4 is a diagram for explaining changes in the potentials of the nodes NX and NY of the
As shown in fig. 4, a period until the potential of the node NX reaches a constant voltage (reference voltage) of the node NY corresponds to a period of 1/2 of the oscillation period. The capacitive element C1 is charged with a current of 0.5Ic, and the potential of the node NX rises.
Therefore, when the oscillation period is defined as T, the capacitance values of the capacitance elements C1 and C2 are defined as C, the resistance value of the resistance element R1 is defined as R, and the current values of the current sources CS1 and CS2 are defined as Ic, the following relationship of the following expression (2) is established.
0.5Ic(T/2)/C＝1.5Ic·R (2)
Therefore, the oscillation period T is determined as shown in equation (3) and is 6 times the product of the resistance value R and the capacitance C.
T＝6RC (3)
As shown in fig. 4, in an actual circuit, the comparator CP has a delay time from the time when the input signal changes until the output signal changes. As a result, overshoot (overshot) occurs in the nodes NX and NY.
Fig. 5 is a diagram for explaining transition of a voltage between terminals of the capacitive elements C1 and C2 of the
As shown in fig. 5, the terminal voltages of the capacitive elements C1 and C2 are ideally triangular waves that reciprocate between 0 and a reference voltage. On the other hand, as shown, the cycle is delayed by this amount because two undershoots and two overshoots occur.
In view of this, when the delay time of the comparator CP is Td, the oscillation period Ta of the
Ta＝6RC+4Td (4)
(influence of oscillation frequency accuracy) the delay time Td of the comparator CP is changed by noise components such as transistor elements constituting the comparator CP. The main term of the power noise is fluctuation of the delay time Td due to low frequency noise. In order to improve the frequency accuracy, it is necessary to reduce the ratio of Td in the oscillation period Ta.
As a comparative example, in the conventional method, the oscillation period in consideration of the comparator delay time is determined by the following equation (5).
Ta＝2RC+2Td (5)
Therefore, compared with the comparator according to the comparative example, the product of RC when the same frequency is set may be 1/3, the circuit area may be significantly reduced.
Further, according to the
< second embodiment >
Fig. 6 is a diagram for explaining the configuration of the
Referring to fig. 6, the
The comparison unit CMP includes a comparator CP and inverters IV0,
The inverter IV1 inverts the input of the inverter IV0 and outputs the inverted clock signal CLKB.
In the capacitive element C1, one side is a node NA0, and the other side is a
For example, the current sources CS1, CS2 are configured by a current mirror circuit using MOS transistors.
The switches SW1 and SW2 are formed of MOS transistors, for example. The current source CS1 is connected between the power supply node (power supply voltage VDD) and the node NX, and supplies a constant current Ic.
The current source CS2 is connected between the power supply node (power supply voltage VDD) and the node NY, and supplies a constant current Ic.
One input terminal of the comparator CP is connected to the node NX, and the other input terminal is connected to the node NY. The comparator CP compares the potential of the node NX with the potential of the node NY, and outputs a signal corresponding to the comparison result.
The node NA0 of the capacitive element C1 is connected to the three-
The node NA1 of the capacitive element C1 is connected to the three-
The node NB0 of the capacitive element C2 is connected to the three-output switch ST 3. The three-output switch ST3 connects the node NB0 to any one of a fixed voltage node (fixed voltage VSS), a node NX, and a node NY according to the switch control signals S6, S8, and S10 output from the decoder DC.
The node NB1 of the capacitive element C2 is connected to the three-output switch ST 4. The three-output switch ST4 connects the node NB1 to any one of a fixed voltage node (fixed voltage VSS), a node NX, and a node NY according to the switch control signals S7, S9, and S11 output from the decoder DC.
The resistance element R1 is connected between the node NC and a fixed voltage node (fixed voltage VSS). The resistance element R1 is a variable resistance element whose resistance value is adjustable. The oscillation frequency can be adjusted by adjusting the resistance value.
The switch SW1 is connected between node NX and node NC and receives an input of the inverted clock signal CLKB.
The switch SW2 is connected between the node NY and the node NC, and receives an input of the non-inverted clock signal CLK.
The switches SW1 and SW2, three-output switches ST1 to ST4, and the decoder DC constitute a switch control circuit for controlling the connection relationship of the current sources CS1 and CS2, the fixed voltage node (fixed voltage VSS), the capacitive elements C1, C2, and the resistive element R1.
Fig. 7 is a circuit diagram for explaining a circuit configuration of a decoder DC according to the second embodiment. Referring to fig. 7, the decoder DC includes frequency dividers 40 AND 42, inverters IV2 AND IV3, AND (AND) circuits AD0 to AD 11.
The frequency divider 40 divides the frequency of the positive phase clock signal CLK by 1/2 and outputs the divided frequency as the switch control signal S0. The switch control signal S0 (high) connects the node NA0 and the node NX.
The inverter IV2 inverts the output of the frequency divider 40 and outputs the inverted output as the switch control signal S1. The switch control signal S1 (high) connects the node NA1 and the node NX.
The AND circuit AD0 outputs the AND logical operation result of the output of the inverter IV2 AND the inverted clock signal CLKB as the switch control signal S2. The switch control signal S2 (high) connects the node NA0 and the node NY.
The AND circuit AD1 outputs the AND logical operation result of the output of the frequency divider 40 AND the inverted clock signal CLKB as the switch control signal S3. The switch control signal S3 (high) connects the node NA1 and the node NY.
The AND circuit AD2 outputs the AND logical operation result of the output of the inverter IV2 AND the positive phase clock signal CLK as the switching control signal S4. The switch control signal S4 (high level) connects the node NA0 and the fixed voltage node (fixed voltage VSS).
The AND circuit AD3 outputs the result of the AND logical operation of the output of the frequency divider 40 AND the positive phase clock signal CLK as the switch control signal S5. The switch control signal S5 (high level) connects the node NA1 and the fixed voltage node (fixed voltage VSS).
The frequency divider 42 divides the frequency of the inverted clock signal CLKB by 1/2 and outputs the divided frequency as the switch control signal S6. The switch control signal S6 (high) connects node NB0 and node NY.
The inverter IV3 inverts the output of the frequency divider 42 and outputs the inverted output as the switch control signal S7. The switch control signal S7 (high) connects node NB1 and node NY.
The AND circuit AD4 outputs the AND logical operation result of the output of the inverter IV3 AND the normal phase clock signal CLK as the switching control signal S8. The switch control signal S8 (high) connects node NB0 and node NX.
The AND circuit AD5 outputs the AND logical operation result of the output of the frequency divider 42 AND the normal phase clock signal CLK as the switch control signal S9. The switch control signal S9 (high) connects node NB1 and node NX.
The AND circuit AD6 outputs the AND logical operation result of the output of the inverter IV3 AND the inverted clock signal CLKB as the switch control signal S10. The switch control signal S10 (high level) connects the node NB0 and the fixed voltage node (fixed voltage VSS).
The AND circuit AD7 outputs the AND logical operation result of the output of the frequency divider 42 AND the inverted clock signal CLKB as the switch control signal S11. The switch control signal S11 (high level) connects the node NB1 and the fixed voltage node (fixed voltage VSS).
Fig. 8 is a diagram for explaining the switch control signals S0 through S11 output from the decoder DC according to the second embodiment.
Referring to fig. 8, in time T0, the positive phase clock signal CLK is set to the high level and the negative phase clock signal BCLK is set to the low level.
Accordingly, the switch control signal S0 is set to the high level. The switch control signal S2 is set to a low level. The switch control signal S4 remains low. The three-output switch ST1 connects the node NA0 and the node NX.
The switch control signal S1 is set to a low level. The switch control signal S3 remains low. The switch control signal S5 is set high. The three-output switch ST2 connects the node NA1 and the fixed voltage node (fixed voltage VSS).
The switch control signal S8 remains low. The switch control signal S6 remains high. The switch control signal S10 remains low. Switch ST3 connects node NB0 and node NY.
The switch control signal S9 is set high. The switch control signal S7 remains low. The switch control signal S11 is set to a low level. The switch ST4 connects the node NB1 and the node NX.
This sets the first connection state. Next, at time T1, the positive phase clock signal CLK is set to the low level, and the negative phase clock signal BCLK is set to the high level.
Accordingly, the switch control signal S0 remains high. The switch control signal S2 remains low. The switch control signal S4 remains low. The three-output switch ST1 connects the node NA0 and the node NX.
The switch control signal S1 remains low. The switch control signal S3 is set to high level. The switch control signal S5 remains low. The three-output switch ST2 connects node NA1 and node NY.
The switch control signal S8 remains low. The switch control signal S6 is set to a low level. The switch control signal S10 is set to high level. The switch ST3 connects the node NB0 and a fixed voltage node (fixed voltage VSS).
The switch control signal S9 is set to low. The switch control signal S7 is set high. The switch control signal S11 remains low. Switch ST4 connects node NB1 and node NY.
This sets the second connection state. At time T2, the positive phase clock signal CLK is set to the high level and the negative phase clock signal BCLK is set to the low level.
Accordingly, the switch control signal S0 is set to the low level. The switch control signal S2 remains low. The switch control signal S4 is set to high. The three-output switch ST1 connects the node NA0 and the fixed voltage node (fixed voltage VSS).
The switch control signal S1 is set to high level. The switch control signal S3 is set to a low level. The switch control signal S5 remains low. The three-output switch ST2 connects the node NA1 and the node NX.
The switch control signal S8 is set to high level. The switch control signal S6 remains low. The switch control signal S10 is set to a low level. The switch ST3 connects the node NB0 and the node NX.
The switch control signal S9 remains low. The switch control signal S7 is set to high. The switch control signal S11 remains low. Switch ST4 connects node NB1 and node NY.
This sets the third connection state. At time T3, the positive phase clock signal CLK is set to the low level and the negative phase clock signal BCLK is set to the high level.
Accordingly, the switch control signal S0 remains low. The switch control signal S2 is set to high level. The switch control signal S4 is set to low. The three-output switch ST1 connects node NA0 and node NY.
The switch control signal S1 remains high. The switch control signal S3 remains low. The switch control signal S5 remains low. The three-output switch ST2 connects the node NA1 and the node NX.
The switch control signal S8 is set to a low level. The switch control signal S6 is set to high level. The switch control signal S10 remains low. Switch ST3 connects node NB0 and node NY.
The switch control signal S9 remains low. The switch control signal S7 is set to low. The switch control signal S1 is set to high level. The switch ST4 connects the node NB1 and a fixed voltage node (fixed voltage VSS).
This sets the fourth connection state. The connection state at time T4 is set to the first connection state, similar to the connection state at time T0. The connection state at time T5 is set to the second connection state, similar to the connection state at time T1. The connection state at time T6 is set to the third connection state, similar to the connection state at time T2. The connection state at time T7 is set to the fourth connection state, similar to the connection state at time T3. The same applies to the time after the time T8.
Next, the operation of the
Fig. 9 is a diagram showing an equivalent circuit of a first connection state of the
In the first connection state, the three output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the fixed voltage node (fixed voltage VSS). Switch ST3 connects node NB0 and node NY. The switch ST4 connects the node NB1 and the node NX.
As shown in fig. 9, the capacitor element C1 is charged with a 0.5Ic current of the constant current Ic supplied from the
The remaining current 0.5Ic of the constant current Ic supplied from the current source CS1 discharges the electric charge stored in the capacitance element C2.
A current 1.5Ic (which is the sum of the current 0.5Ic discharged from the capacitive element C2 and the current Ic supplied from the current source CS 2) flows to the resistive element R1.
As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing to the resistance element R1.
When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the high level to the low level. The inverted clock signal CLKB output from the inverter IV1 changes from the low level to the high level.
Fig. 10 is a diagram for explaining an equivalent circuit of a second connection state of the
In the second connection state, the three-output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects node NA1 and node NY. The switch ST3 connects the node NB0 and a fixed voltage node (fixed voltage VSS). Switch ST4 connects node NB1 and node NY.
As shown in fig. 10, the capacitance element C2 is charged by a 0.5Ic current of the constant current Ic supplied from the
The residual current 0.5Ic of the constant current Ic supplied from the current source CS2 discharges the electric charge stored in the capacitive element C1.
A current 1.5Ic (which is the sum of the current 0.5I discharged from the capacitive element C1 and the current Ic supplied from the current source CS 1) flows to the resistive element R1.
As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing to the resistance element R1.
When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the low level to the high level. The inverted clock signal CLKB output from the inverter IV1 changes from the high level to the low level.
Fig. 11 is a diagram for explaining an equivalent circuit of a third connection state of the
In the third connection state, the three output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the fixed voltage node (fixed voltage VSS). Switch ST3 connects node NB0 and node NY. The switch ST4 connects the node NB1 and the node NX.
As shown in fig. 11, the capacitance element C1 is charged by a 0.5Ic current of the constant current Ic supplied from the
The remaining current 0.5Ic of the constant current Ic supplied from the current source CS1 discharges the electric charge stored in the capacitance element C2.
A current 1.5Ic (which is the sum of the current 0.5Ic discharged from the capacitive element C2 and the current Ic supplied from the current source CS 2) flows to the resistive element R1.
As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1.
When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the high level to the low level. The inverted clock signal CLKB output from the inverter IV1 changes from the low level to the high level.
Fig. 12 is a diagram for explaining an equivalent circuit of a fourth connection state of the
In the fourth connection state, the three output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects node NA1 and node NY. The switch ST3 connects the node NB0 and a fixed voltage node (fixed voltage VSS). Switch ST4 connects node NB1 and node NY.
As shown in fig. 12, the capacitive element C2 is charged by a current 0.5Ic of the constant current Ic supplied from the
The remaining current 0.5Ic of the constant current Ic supplied from the current source CS2 discharges the electric charge stored in the capacitance element C1.
A current 1.5Ic (which is the sum of the current 0.5I discharged from the capacitive element C1 and the current Ic supplied from the current source CS 1) flows to the resistive element R1.
As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1.
When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The non-inverted clock signal CLK output from the inverter IV0 transitions from the low level to the high level. The inverted clock signal CLKB output from the inverter IV1 changes from the high level to the low level.
Thus, the positive phase clock signal CLK repeats transitions from the high level to the low level and from the low level to the high level. Thus, the
Fig. 13 is a diagram for explaining changes in the potentials of the nodes NX and NY of the
As shown in fig. 13, a period until the potential of the node NX reaches a constant voltage (reference voltage) of the node NY corresponds to a period of 1/2 of the oscillation period. The capacitive element C1 is charged with a current of 0.5Ic, and the potential of the node NX rises.
Therefore, when the oscillation period is T, the capacitance values of the capacitance elements C1, C2 are C, the resistance value of the resistance element R1 is R, and the current values of the current sources CS1, CS2 are Ic, the ideal oscillation period T is 6RC, similarly to the first embodiment.
On the other hand, in the actual circuit, the comparator CP has a delay time from when the input signal changes to when the output signal changes, similarly to the first embodiment. As a result, overshoot occurs in the nodes NX and NY.
Fig. 14 is a diagram for explaining transition of a voltage between terminals of the capacitive elements C1 and C2 of the
As shown in fig. 14, the terminal voltages of the capacitive elements C1 and C2 ideally have triangular waves that reciprocate between 0 and a reference voltage.
In the
Ta＝6RC+2Td (6)
Therefore, the
The
Fig. 15 is a diagram for explaining a state when the
As shown in fig. 15, the voltage between the terminals of the node NA0 and the node NA1 of the capacitive element C1 is set to the reference voltage VREF + the overshoot voltage Δ V by the influence of the delay of the comparator CP. At this time, the terminal voltage between the node NB1 and the node NB0 of the capacitive element C2 is set to the voltage Δ V.
Fig. 16 is a diagram for explaining a state when the second connection state of the
As shown in fig. 16, according to the switching of the second connection state, the potential of the node NY is set to the voltage Δ V of the terminal voltage between the node NB1 and the node NB0 of the capacitive element C2.
The potential of the node NX is set to the reference voltage VREF +2 Δ V. Since the potential of the node NX converges to the reference voltage VREF, the component of the voltage Δ V originally present at the node NY also disappears due to the capacitive voltage division during the process. That is, the overshoot voltage Δ V is eliminated.
Also, the same phenomenon occurs when transitioning from the third connection state described with reference to fig. 11 to the fourth connection state described with reference to fig. 12.
Therefore, compared with the
Although the present disclosure has been specifically described based on the above-described embodiments, the present disclosure is not limited to these embodiments, and needless to say, various modifications may be made without departing from the gist thereof.
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