阅读说明：本技术 一种脉冲产生电路 (Pulse generating circuit ) 是由 彭家旭 于 2019-04-16 设计创作，主要内容包括：本发明实施例公开了一种脉冲产生电路,所述脉冲产生电路包括：控制电路以及脉冲信号生成电路；其中,所述控制电路适于接入所述脉冲信号生成电路生成的脉冲信号,所述控制电路适于响应于所述脉冲信号的第一边沿,延时输出控制信号的第二边沿,所述第二边沿的跳变方向与所述第一边沿反向；所述脉冲信号生成电路适于接入时钟信号以及所述控制信号,所述脉冲信号生成电路适于跟随时钟信号的第一边沿生成所述脉冲信号的第一边沿,并且适于跟随所述控制信号的第二边沿生成所述脉冲信号的第二边沿。本发明实施例中的技术方案可以改变输出的脉冲信号的脉冲宽度。(The embodiment of the invention discloses a pulse generating circuit, which comprises: a control circuit and a pulse signal generating circuit; the control circuit is suitable for being connected into the pulse signal generated by the pulse signal generating circuit, and the control circuit is suitable for responding to a first edge of the pulse signal and delaying to output a second edge of the control signal, wherein the transition direction of the second edge is opposite to that of the first edge; the pulse signal generating circuit is suitable for being connected with a clock signal and the control signal, and is suitable for generating a first edge of the pulse signal along with a first edge of the clock signal and generating a second edge of the pulse signal along with a second edge of the control signal. The technical scheme in the embodiment of the invention can change the pulse width of the output pulse signal.)

1. A pulse generating circuit, comprising: a control circuit and a pulse signal generating circuit; wherein the content of the first and second substances,

the control circuit is suitable for being connected into the pulse signal generated by the pulse signal generating circuit, and the control circuit is suitable for responding to a first edge of the pulse signal and delaying and outputting a second edge of the control signal, wherein the transition direction of the second edge is opposite to that of the first edge;

the pulse signal generating circuit is suitable for being connected with a clock signal and the control signal, and is suitable for generating a first edge of the pulse signal along with a first edge of the clock signal and generating a second edge of the pulse signal along with a second edge of the control signal.

2. The pulse generating circuit according to claim 1, wherein the pulse signal generating circuit comprises: a first initial pulse signal generating circuit, a second initial pulse signal generating circuit, and an inverter circuit coupled to the first initial pulse signal generating circuit and the second initial pulse signal generating circuit, respectively;

the first initial pulse signal generating circuit is adapted to generate a second edge of an initial pulse signal following a first edge of the clock signal when the clock signal is at a first level, and to maintain the initial pulse signal at a second level until the second edge of the clock signal arrives;

the second initial pulse signal generating circuit is adapted to maintain the second level of the initial pulse signal until the second edge of the control signal comes before the clock signal is at the second level, and is adapted to generate the first edge of the initial pulse signal following the second edge of the control signal when the clock signal is at the second level;

the inversion circuit is suitable for inverting the initial pulse signal and outputting a first edge and a second edge of the pulse signal;

the first edge is an edge where the first level jumps to the second level, and the second edge is an edge where the second level jumps to the first level.

3. The pulse generating circuit according to claim 2, wherein the first edge is a rising edge, the second edge is a falling edge, the first level is a high level, the second level is a low level, and the first initial pulse signal generating circuit includes: a leading signal generating sub-circuit, a first initial pulse signal generating sub-circuit, a first switching sub-circuit, and a locking sub-circuit;

the input end of the preposed signal generating sub-circuit is coupled to a power supply, and the preposed signal generating sub-circuit is suitable for outputting a preposed signal with high level according to the voltage provided by the power supply when the clock signal is at low level;

the input end of the first initial pulse signal generation sub-circuit is suitable for being connected with the preposition signal and the control signal, and the first initial pulse signal generation sub-circuit is suitable for generating a first initial pulse signal according to the preposition signal and the control signal;

the input end of the first switch sub-circuit is suitable for being connected with the first initial pulse signal, is suitable for being switched on when the clock signal is at a high level, generates a falling edge of the initial pulse signal, and is suitable for maintaining the initial pulse signal at a low level before the falling edge of the clock signal arrives;

the input end of the locking sub-circuit is suitable for accessing the first initial pulse signal and locking the preposed signal based on the first initial pulse signal when the clock signal is at a low level.

4. The pulse generating circuit of claim 3, wherein the first initial pulse signal generating sub-circuit comprises a first NAND gate.

5. The pulse generating circuit of claim 3, wherein the clock signal comprises a forward clock signal and a reverse clock signal, a first edge of the clock signal being a rising edge of the forward clock signal, a second edge of the clock signal being a falling edge of the forward clock signal; the first switch sub-circuit comprises: a first PMOS tube and a first NMOS tube;

the source electrode of the first PMOS tube is coupled to the output end of the first initial pulse signal generation sub-circuit, the grid electrode of the first PMOS tube is coupled to the inverted clock signal, and the drain electrode of the first PMOS tube is coupled to the input end of the inverting circuit;

the drain electrode of the first NMOS tube is coupled to the source electrode of the first PMOS tube, the grid electrode of the first NMOS tube is coupled to the positive clock signal, and the source electrode of the first NMOS tube is coupled to the drain electrode of the first PMOS tube.

6. The pulse generating circuit of claim 3, wherein the clock signal comprises a forward clock signal and a reverse clock signal, a first edge of the clock signal being a rising edge of the forward clock signal, a second edge of the clock signal being a falling edge of the forward clock signal; the preamble signal generating sub-circuit includes: a second PMOS tube and a second NMOS tube;

the source electrode of the second PMOS tube is coupled to a power supply, the grid electrode of the second PMOS tube is coupled to the positive clock signal, and the drain electrode of the second PMOS tube is coupled to the input end of the first initial pulse signal generating sub-circuit;

the drain electrode of the second NMOS tube is coupled to a power supply, the grid electrode of the second NMOS tube is coupled to the reverse clock signal, and the source electrode of the second NMOS tube is coupled to the drain electrode of the second PMOS tube.

7. The pulse generating circuit of claim 3, wherein the clock signal comprises a forward clock signal and a reverse clock signal, a first edge of the clock signal being a rising edge of the forward clock signal, a second edge of the clock signal being a falling edge of the forward clock signal; the locking sub-circuit includes: the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube;

the source electrode of the third PMOS tube is coupled to a power supply, the grid electrode of the third PMOS tube is coupled to the reverse clock signal, and the drain electrode of the third PMOS tube is coupled to the source electrode of the fourth PMOS tube;

the grid electrode of the fourth PMOS tube is coupled to the output end of the first initial pulse signal generation sub-circuit, and the drain electrode of the fourth PMOS tube is coupled to the input end of the first initial pulse signal generation sub-circuit;

the drain electrode of the third NMOS tube is coupled to the drain electrode of the fourth PMOS tube, the gate electrode of the third NMOS tube is coupled to the gate electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is coupled to the drain electrode of the fourth NMOS tube;

the grid electrode of the fourth NMOS tube is coupled to the positive clock signal, and the source electrode of the fourth NMOS tube is grounded.

8. The pulse generating circuit according to claim 2, wherein the first edge is a rising edge, the second edge is a falling edge, the first level is a high level, the second level is a low level, and the second initial pulse signal generating circuit comprises: a second initial pulse signal generating sub-circuit and a second switching sub-circuit;

the input end of the second initial pulse signal generating sub-circuit is suitable for being connected with the pulse signal and the control signal, and the second initial pulse signal generating sub-circuit is suitable for generating a second initial pulse signal according to the control signal and the pulse signal;

the input end of the second switch sub-circuit is suitable for being connected with the second initial pulse signal, is suitable for being switched on when the clock signal is at a low level, and is suitable for maintaining the initial pulse signal at the low level before the falling edge of the control signal comes, and the rising edge of the initial pulse signal is generated along with the falling edge of the control signal.

9. The pulse generating circuit of claim 8, wherein the second initial pulse signal generating sub-circuit comprises a second nand gate.

10. The pulse generating circuit of claim 8, wherein the clock signal comprises a forward clock signal and a reverse clock signal, a first edge of the clock signal being a rising edge of the forward clock signal, a second edge of the clock signal being a falling edge of the forward clock signal; the second switch sub-circuit comprises: a fifth PMOS tube and a fifth NMOS tube;

a source electrode of the fifth PMOS tube is coupled to an output end of the second initial pulse signal generation sub-circuit, a grid electrode of the fifth PMOS tube is coupled to the forward clock signal, and a drain electrode of the fifth PMOS tube is coupled to an input end of the reverse circuit;

the drain of the fifth NMOS transistor is coupled to the output of the second initial pulse signal generation sub-circuit, the gate of the fifth NMOS transistor is coupled to the inverted clock signal, and the source of the fifth NMOS transistor is coupled to the drain of the fifth PMOS transistor.

11. The pulse generating circuit of claim 2, wherein the inverting circuit comprises a first inverter.

12. The pulse generating circuit of claim 1, wherein the control circuit comprises: the second phase inverter, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the sixth NMOS tube, the seventh NMOS tube, the ninth PMOS tube, the eighth NMOS tube, the third phase inverter and the fourth phase inverter;

the input end of the second inverter is coupled to the output end of the pulse signal generating circuit, and the output end of the second inverter is coupled to the gates of the sixth PMOS tube and the sixth NMOS tube;

the source electrode of the sixth PMOS tube is coupled to a power supply, and the drain electrode of the sixth PMOS tube is coupled to the source electrode of the seventh PMOS tube;

the grid electrode of the seventh PMOS tube is grounded, and the drain electrode of the seventh PMOS tube is coupled to the source electrode of the eighth PMOS tube;

the grid electrode of the eighth PMOS tube is grounded, and the drain electrode of the eighth PMOS tube is coupled to the drain electrode of the sixth NMOS tube;

the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is coupled to the grid electrode of the nine PMOS tube;

the grid electrode of the seventh NMOS tube is coupled to the drain electrode of the sixth NMOS tube, and the source electrode and the drain electrode of the seventh NMOS tube are both grounded;

the source electrode of the ninth PMOS tube is coupled to a power supply, the gate electrode of the ninth PMOS tube is coupled to the gate electrode of the eighth NMOS tube, and the drain electrode of the ninth PMOS tube is coupled to the drain electrode of the eighth NMOS tube;

the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is coupled to the input end of the third inverter;

an output of the third inverter is coupled to an input of the fourth inverter;

the output end of the fourth inverter is suitable for outputting the control signal.

13. The pulse generating circuit of claim 1, further comprising: and the clock signal generating circuit takes an initial clock signal as input and outputs the clock signal.

14. The pulse generating circuit of claim 13, wherein the clock signal comprises a forward clock signal and a reverse clock signal;

the clock signal generation circuit includes: a fifth inverter and a sixth inverter;

the output end of the fifth inverter is coupled with the input end of the sixth inverter, and the fifth inverter is suitable for inverting the input initial clock signal and outputting the inverted clock signal;

the sixth inverter is adapted to invert the reverse clock signal and output the forward clock signal.

15. The pulse generating circuit of claim 1, further comprising: and the shaping output circuit is suitable for shaping and outputting the pulse signal generated by the pulse signal generating circuit.

16. The pulse generating circuit of claim 15, wherein the shaping output circuit comprises: a seventh inverter and an eighth inverter;

an input end of the seventh inverter is coupled to an output end of the pulse signal generating circuit, an output end of the seventh inverter is coupled to an input end of the eighth inverter, and the seventh inverter and the eighth inverter are adapted to shape and output the pulse signal.

17. The pulse generating circuit of claim 1, wherein the control circuit delays for a period greater than a first level period of the clock signal.

Technical Field

The invention relates to the field of circuits, in particular to a pulse generating circuit.

Background

The emergence of Non-volatile Memory (NVM) provides a new approach for expanding computer Memory, and is widely applied to various System On Chip (SOC).

In IP and system interface communication protocols, there are respective timing restrictions, and misoperation of a system clock, for example, a clock duty ratio change, has a significant influence on whether data read out from an IP is correct or not.

How to change the pulse width of the output pulse signal becomes an urgent problem to be solved.

Disclosure of Invention

The problem to be solved by the invention is to change the pulse width of the output pulse signal.

To solve the above problems, the present invention provides a pulse generating circuit, comprising: a control circuit and a pulse signal generating circuit; the control circuit is suitable for being connected into the pulse signal generated by the pulse signal generating circuit, and the control circuit is suitable for responding to a first edge of the pulse signal and delaying to output a second edge of the control signal, wherein the transition direction of the second edge is opposite to that of the first edge; the pulse signal generating circuit is suitable for being connected with a clock signal and the control signal, and is suitable for generating a first edge of the pulse signal along with a first edge of the clock signal and generating a second edge of the pulse signal along with a second edge of the control signal.

Optionally, the pulse signal generating circuit includes: a first initial pulse signal generating circuit, a second initial pulse signal generating circuit, and an inverter circuit coupled to the first initial pulse signal generating circuit and the second initial pulse signal generating circuit, respectively; the first initial pulse signal generating circuit is adapted to generate a second edge of an initial pulse signal following a first edge of the clock signal when the clock signal is at a first level, and to maintain the initial pulse signal at a second level until the second edge of the clock signal arrives; the second initial pulse signal generating circuit is adapted to maintain the second level of the initial pulse signal until the second edge of the control signal comes before the clock signal is at the second level, and is adapted to generate the first edge of the initial pulse signal following the second edge of the control signal when the clock signal is at the second level; the inversion circuit is suitable for inverting the initial pulse signal and outputting a first edge and a second edge of the pulse signal; the first edge is an edge where the first level jumps to the second level, and the second edge is an edge where the second level jumps to the first level.

Optionally, the first edge is a rising edge, the second edge is a falling edge, the first level is a high level, the second level is a low level, and the first initial pulse signal generating circuit includes: a leading signal generating sub-circuit, a first initial pulse signal generating sub-circuit, a first switching sub-circuit, and a locking sub-circuit; the input end of the preposed signal generating sub-circuit is coupled to a power supply, and the preposed signal generating sub-circuit is suitable for outputting a preposed signal with high level according to the voltage provided by the power supply when the clock signal is at low level; the input end of the first initial pulse signal generation sub-circuit is suitable for being connected with the preposition signal and the control signal, and the first initial pulse signal generation sub-circuit is suitable for generating a first initial pulse signal according to the preposition signal and the control signal; the input end of the first switch sub-circuit is suitable for being connected with the first initial pulse signal, is suitable for being switched on when the clock signal is at a high level, generates a falling edge of the initial pulse signal, and is suitable for maintaining the initial pulse signal at a low level before the falling edge of the clock signal arrives; the input end of the locking sub-circuit is suitable for accessing the first initial pulse signal and locking the preposed signal based on the first initial pulse signal when the clock signal is at a low level.

Optionally, the first initial pulse signal generating sub-circuit includes a first nand gate.

Optionally, the clock signal includes a forward clock signal and a reverse clock signal, a first edge of the clock signal is a rising edge of the forward clock signal, and a second edge of the clock signal is a falling edge of the forward clock signal; the first switch sub-circuit comprises: a first PMOS tube and a first NMOS tube; the source electrode of the first PMOS tube is coupled to the output end of the first initial pulse signal generation sub-circuit, the grid electrode of the first PMOS tube is coupled to the inverted clock signal, and the drain electrode of the first PMOS tube is coupled to the input end of the inverting circuit; the drain electrode of the first NMOS tube is coupled to the source electrode of the first PMOS tube, the grid electrode of the first NMOS tube is coupled to the positive clock signal, and the source electrode of the first NMOS tube is coupled to the drain electrode of the first PMOS tube.

Optionally, the clock signal includes a forward clock signal and a reverse clock signal, a first edge of the clock signal is a rising edge of the forward clock signal, and a second edge of the clock signal is a falling edge of the forward clock signal; the preamble signal generating sub-circuit includes: a second PMOS tube and a second NMOS tube; the source electrode of the second PMOS tube is coupled to a power supply, the grid electrode of the second PMOS tube is coupled to the positive clock signal, and the drain electrode of the second PMOS tube is coupled to the input end of the first initial pulse signal generating sub-circuit; the drain electrode of the second NMOS tube is coupled to a power supply, the grid electrode of the second NMOS tube is coupled to the reverse clock signal, and the source electrode of the second NMOS tube is coupled to the drain electrode of the second PMOS tube.

Optionally, the clock signal includes a forward clock signal and a reverse clock signal, a first edge of the clock signal is a rising edge of the forward clock signal, and a second edge of the clock signal is a falling edge of the forward clock signal; the locking sub-circuit includes: the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube; the source electrode of the third PMOS tube is coupled to a power supply, the grid electrode of the third PMOS tube is coupled to the reverse clock signal, and the drain electrode of the third PMOS tube is coupled to the source electrode of the fourth PMOS tube; the grid electrode of the fourth PMOS tube is coupled to the output end of the first initial pulse signal generation sub-circuit, and the drain electrode of the fourth PMOS tube is coupled to the input end of the first initial pulse signal generation sub-circuit; the drain electrode of the third NMOS tube is coupled to the drain electrode of the fourth PMOS tube, the gate electrode of the third NMOS tube is coupled to the gate electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is coupled to the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is coupled to the positive clock signal, and the source electrode of the fourth NMOS tube is grounded.

Optionally, the first edge is a rising edge, the second edge is a falling edge, the first level is a high level, the second level is a low level, and the second initial pulse signal generating circuit includes: a second initial pulse signal generating sub-circuit and a second switching sub-circuit; the input end of the second initial pulse signal generating sub-circuit is suitable for being connected with the pulse signal and the control signal, and the second initial pulse signal generating sub-circuit is suitable for generating a second initial pulse signal according to the control signal and the pulse signal; the input end of the second switch sub-circuit is suitable for being connected with the second initial pulse signal, is suitable for being switched on when the clock signal is at a low level, and is suitable for maintaining the initial pulse signal at the low level before the falling edge of the control signal comes, and the rising edge of the initial pulse signal is generated along with the falling edge of the control signal.

Optionally, the second initial pulse signal generating sub-circuit includes a second nand gate.

Optionally, the clock signal includes a forward clock signal and a reverse clock signal, a first edge of the clock signal is a rising edge of the forward clock signal, and a second edge of the clock signal is a falling edge of the forward clock signal; the second switch sub-circuit comprises: a fifth PMOS tube and a fifth NMOS tube; a source electrode of the fifth PMOS tube is coupled to an output end of the second initial pulse signal generation sub-circuit, a grid electrode of the fifth PMOS tube is coupled to the forward clock signal, and a drain electrode of the fifth PMOS tube is coupled to an input end of the reverse circuit; the drain of the fifth NMOS transistor is coupled to the output of the second initial pulse signal generation sub-circuit, the gate of the fifth NMOS transistor is coupled to the inverted clock signal, and the source of the fifth NMOS transistor is coupled to the drain of the fifth PMOS transistor.

Optionally, the inverting circuit comprises a first inverter.

Optionally, the control circuit includes: the second phase inverter, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the sixth NMOS tube, the seventh NMOS tube, the ninth PMOS tube, the eighth NMOS tube, the third phase inverter and the fourth phase inverter; the input end of the second inverter is coupled to the output end of the pulse signal generating circuit, and the output end of the second inverter is coupled to the gates of the sixth PMOS tube and the sixth NMOS tube; the source electrode of the sixth PMOS tube is coupled to a power supply, and the drain electrode of the sixth PMOS tube is coupled to the source electrode of the seventh PMOS tube; the grid electrode of the seventh PMOS tube is grounded, and the drain electrode of the seventh PMOS tube is coupled to the source electrode of the eighth PMOS tube; the grid electrode of the eighth PMOS tube is grounded, and the drain electrode of the eighth PMOS tube is coupled to the drain electrode of the sixth NMOS tube; the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is coupled to the grid electrode of the nine PMOS tube; the grid electrode of the seventh NMOS tube is coupled to the drain electrode of the sixth NMOS tube, and the source electrode and the drain electrode of the seventh NMOS tube are both grounded; the source electrode of the ninth PMOS tube is coupled to a power supply, the gate electrode of the ninth PMOS tube is coupled to the gate electrode of the eighth NMOS tube, and the drain electrode of the ninth PMOS tube is coupled to the drain electrode of the eighth NMOS tube; the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is coupled to the input end of the third inverter; an output of the third inverter is coupled to an input of the fourth inverter; the output end of the fourth inverter is suitable for outputting the control signal.

Optionally, the pulse generating circuit further includes: and the clock signal generating circuit takes an initial clock signal as input and outputs the clock signal.

Optionally, the clock signal includes a forward clock signal and a reverse clock signal; the clock signal generation circuit includes: a fifth inverter and a sixth inverter; the output end of the fifth inverter is coupled with the input end of the sixth inverter, and the fifth inverter is suitable for inverting the input initial clock signal and outputting the inverted clock signal; the sixth inverter is adapted to invert the reverse clock signal and output the forward clock signal.

Optionally, the pulse generating circuit further comprises: and the shaping output circuit is suitable for shaping and outputting the pulse signal generated by the pulse signal generating circuit.

Optionally, the shaping output circuit includes: a seventh inverter and an eighth inverter; an input end of the seventh inverter is coupled to an output end of the pulse signal generating circuit, an output end of the seventh inverter is coupled to an input end of the eighth inverter, and the seventh inverter and the eighth inverter are adapted to shape and output the pulse signal.

Optionally, the delay duration of the control circuit is greater than the first level period of the clock signal.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in an embodiment of the present invention, the pulse generating circuit includes a control circuit and a pulse signal generating circuit, wherein the control circuit is adapted to receive the pulse signal generated by the pulse signal generating circuit, the control circuit is adapted to delay a second edge of the control signal in response to a first edge of the pulse signal, a transition direction of the second edge is opposite to that of the first edge, the pulse signal generating circuit is adapted to receive a clock signal and the control signal, and the pulse signal generating circuit is adapted to generate the first edge of the pulse signal following the first edge of the clock signal and generate the second edge of the pulse signal following the second edge of the control signal. Therefore, the second edge of the pulse signal is generated along with the second edge of the control signal, the generation time of the second edge of the pulse signal can be adjusted by adjusting the time of the control signal output by the control circuit, and the pulse width of the pulse signal can be adjusted.

Drawings

FIG. 1 is a schematic diagram of a pulse generating circuit;

FIG. 2 is a waveform diagram of a pulse signal generated by a pulse generating circuit;

FIG. 3 is a schematic diagram of a pulse generating circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first initial pulse signal generating circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a second initial pulse signal generating circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pulse generation circuit according to an embodiment of the present invention;

fig. 7 is a waveform diagram of a pulse signal generated by the pulse generating circuit shown in fig. 6.

Detailed Description

As can be seen from the background art, how to change the pulse width of the output pulse signal is an urgent problem to be solved.

Referring to fig. 1, in a PULSE generating circuit, an initial clock signal CLK is input to a digital circuit, and a PULSE signal PULSE is output after being delayed by the digital circuit. The digital circuit may include a plurality of inverters and a nand gate connected in series, and the output PULSE signal PULSE varies with a variation of the initial clock signal CLK. Referring to fig. 2, a waveform diagram of a PULSE signal generated by a PULSE generating circuit is shown, where 1 is a waveform of an initial clock signal CLK, 2 is a waveform of an output PULSE signal PULSE, a PULSE width of the PULSE signal PULSE coincides with a PULSE width of the initial clock signal CLK, and a PULSE width L1 of the PULSE signal PULSE is affected by a duty ratio of high and low levels of the initial clock signal CLK.

In an embodiment of the present invention, the pulse generating circuit includes a control circuit and a pulse signal generating circuit, wherein the control circuit is adapted to receive the pulse signal generated by the pulse signal generating circuit, the control circuit is adapted to delay a second edge of the control signal in response to a first edge of the pulse signal, a transition direction of the second edge is opposite to that of the first edge, the pulse signal generating circuit is adapted to receive a clock signal and the control signal, and the pulse signal generating circuit is adapted to generate the first edge of the pulse signal following the first edge of the clock signal and generate the second edge of the pulse signal following the second edge of the control signal. Therefore, the second edge of the pulse signal is generated along with the second edge of the control signal, the generation time of the second edge of the pulse signal can be adjusted by adjusting the time of the control signal output by the control circuit, and the pulse width of the pulse signal can be adjusted.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to a schematic structure diagram of a pulse generating circuit shown in fig. 3, in an embodiment of the present invention, the pulse generating circuit 30 may include: a control circuit 31 and a pulse signal generation circuit 32.

In a specific implementation, the control circuit 31 is adapted to access the pulse signal generated by the pulse signal generating circuit 32, and the control circuit 31 is adapted to delay a second edge of the output control signal in response to a first edge of the pulse signal, where a transition direction of the second edge is opposite to that of the first edge. The pulse signal generating circuit 32 is adapted to receive a clock signal and the control signal, and the pulse signal generating circuit 32 is adapted to generate a first edge of the pulse signal following a first edge of the clock signal and to generate a second edge of the pulse signal following a second edge of the control signal.

The term "coupled" in the embodiments of the present invention refers to direct connection or indirect connection, and the meaning of "coupled" in the following is consistent and will not be described one by one.

In the embodiment of the present invention, the generation of another signal following one signal means that another signal is generated after one signal, that is, another signal is generated by being triggered by one signal. Taking the first edge of the clock signal and the first edge of the pulse signal as an example, the generation of the first edge of the clock signal triggers the generation of the first edge of the pulse signal, i.e., the first edge of the pulse signal follows the first edge of the clock signal.

In a specific implementation, the first edge may be a rising edge and the second edge may be a falling edge, or the first edge may be a falling edge and the second edge may be a rising edge, which is not limited in this respect.

It will be understood by those skilled in the art that "first" and "second" in the embodiments of the present invention are merely for convenience of description and do not represent specific limitations on the implementation thereof.

In a specific implementation, the delay time of the control circuit 31 is longer than the first level period of the clock signal, so that the second edge of the control signal generated by the control circuit 31 is later than the second edge of the clock signal, the pulse width of the output pulse signal can be made longer than the first level period of the clock signal, and the pulse width of the output pulse signal can be further changed.

With continued reference to fig. 3, in a specific implementation, the pulse signal generation circuit 32 may include: a first initial pulse signal generating circuit 321, a second initial pulse signal generating circuit 322, and an inverting circuit 323 respectively coupled to the first initial pulse signal generating circuit 321 and the second initial pulse signal generating circuit 322.

In a specific implementation, the first initial pulse signal generating circuit 321 is adapted to generate a second edge of an initial pulse signal following the first edge of the clock signal when the clock signal is at the first level, and is adapted to maintain the initial pulse signal at the second level before the second edge of the clock signal arrives. The second initial pulse signal generating circuit 322 is adapted to maintain the second level of the initial pulse signal before the clock signal is at the second level and the second edge of the control signal arrives, and is adapted to generate the first edge of the initial pulse signal following the second edge of the control signal when the clock signal is at the second level. The inversion circuit 323 is adapted to invert the initial pulse signal and output a first edge and a second edge of the pulse signal.

In a specific implementation, the first level and the second level are different levels, and are respectively a high level or a low level. Specifically, the following cases may be included: the first level is high level, and the second level is low level; or the first level is low and the second level is high. The first edge is an edge where the first level jumps to the second level, and the second edge is an edge where the second level jumps to the first level.

Fig. 6 shows a schematic structure diagram of a pulse generating circuit according to an embodiment of the present invention, and in an implementation, the inverting circuit 323 may include a first inverter I1. It will be understood by those skilled in the art that the inverting circuit 323 can be other circuit devices that can invert the circuit signal in the specific implementation, and is not limited thereto.

By providing the inverting circuit, the initial pulse signals generated by the first initial pulse signal generating circuit and the second initial pulse signal generating circuit are inverted, and the pulse signals are output, so that the initial level state of the output pulse signals can be kept consistent with the initial level state of the clock signals.

As described above, the first edge and the second edge have opposite transition directions, the first edge may be a rising edge or a falling edge, the second edge may be a falling edge or a rising edge, the first level may be a high level, the second level may be a low level, or the first level may be a low level and the second level may be a high level.

In an embodiment of the invention, the first edge is a rising edge, the second edge is a falling edge, the first level is a high level, and the second level is a low level. Referring to fig. 4 in combination, in a specific implementation, the first initial pulse signal generating circuit 321 may include: a preamble signal generating sub-circuit 3211, a first initial pulse signal generating sub-circuit 3212, a first switching sub-circuit 3213, and a locking sub-circuit 3214.

In a specific implementation, an input terminal of the preamble signal generating sub-circuit 3211 is coupled to a power supply, and the preamble signal generating sub-circuit 3211 is adapted to output a preamble signal of a high level according to a voltage provided by the power supply when the clock signal is at a low level. The input terminal of the first initial pulse signal generating sub-circuit 3212 is adapted to receive the preamble signal and the control signal, and the first initial pulse signal generating sub-circuit 3212 is adapted to generate a first initial pulse signal according to the preamble signal and the control signal. The input terminal of the first switch sub-circuit 3213 is adapted to receive the first initial pulse signal, to turn on when the clock signal is at a high level, to generate a falling edge of the initial pulse signal, and to maintain the initial pulse signal at a low level before the falling edge of the clock signal arrives. The input end of the locking sub-circuit 3214 is adapted to receive the first initial pulse signal, and is adapted to lock the preamble signal based on the first initial pulse signal when the clock signal is at a low level.

The description will be continued by taking the pulse generating circuit shown in fig. 6 as an example. In a specific implementation, the first initial pulse signal generating sub-circuit 3212 may include a first nand gate U1, a first input of the first nand gate U1 is connected to the control signal LRESET, a second input of the first nand gate U1 is connected to the preamble, and the first nand gate U1 is adapted to generate the first initial pulse signal according to the control signal LRESET and a level state of the preamble. For example, if both the control signal LRESET and the preamble signal are at a high level, the first nand gate U1 outputs a first initial pulse signal at a low level, and if at least one of the control signal LRESET and the preamble signal is at a low level, the first nand gate U1 outputs a first initial pulse signal at a high level.

In a specific implementation, the clock signals may include a forward clock signal CK and a reverse clock signal CK _ N. It will be understood by those skilled in the art that the first edge of the clock signal may be a rising edge of the positive clock signal CK, and the second edge of the clock signal may be a falling edge of the positive clock signal CK.

With continued reference to fig. 6, in a specific implementation, the first switch sub-circuit 3213 may include: a first PMOS transistor MP1 and a first NMOS transistor MN 1. The source of the first PMOS transistor MP1 is coupled to the output terminal of the first initial pulse signal generating sub-circuit 3212, the gate of the first PMOS transistor MP1 is coupled to the inverted clock signal CK _ N, and the drain of the first PMOS transistor MP1 is coupled to the input terminal of the inverting circuit 323. The drain of the first NMOS transistor MN1 is coupled to the source of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 is coupled to the positive clock signal CK, and the source of the first NMOS transistor MN1 is coupled to the drain of the first PMOS transistor MP 1.

In an implementation, when the forward clock signal CK is at a high level and the reverse clock signal CK _ N is at a low level, the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on, and the first initial pulse signal generated by the first initial pulse signal generating sub-circuit 3212 is output to the reverse circuit 323 through the first PMOS transistor MP1 and the first NMOS transistor MN 1.

It will be understood by those skilled in the art that the above embodiments are only examples, and in other embodiments, the first switch sub-circuit 3213 may be a circuit device for turning on and off the circuit, which is not limited thereto.

With continued reference to the pulse generation circuit shown in fig. 6, in a specific implementation, the preamble signal generation sub-circuit 3211 may include: a second PMOS transistor MP2 and a second NMOS transistor MN 2.

A source of the second PMOS transistor MP2 is coupled to a power VDD, a gate of the second PMOS transistor MP2 is coupled to the positive clock signal CK, and a drain of the second PMOS transistor MP2 is coupled to an input terminal of the first initial pulse signal generating sub-circuit 3212. The drain of the second NMOS transistor MN2 is coupled to a power supply VDD, the gate of the second NMOS transistor MN2 is coupled to the inverted clock signal CK _ N, and the source of the second NMOS transistor MN2 is coupled to the drain of the second PMOS transistor MP 2.

In a specific implementation, when the forward clock signal CK is at a low level and the backward clock signal CK _ N is at a high level, the second PMOS transistor MP2 and the second NMOS transistor MN2 are turned on to output a high-level preamble signal.

With continued reference to fig. 6, in a specific implementation, the lock stator circuit 3214 may include: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, and a fourth NMOS transistor MN 4.

The source of the third PMOS transistor MP3 is coupled to a power supply VDD, the gate of the third PMOS transistor MP3 is coupled to the inverted clock signal CK _ N, and the drain of the third PMOS transistor MP3 is coupled to the source of the fourth PMOS transistor MP 4. The gate of the fourth PMOS transistor MP4 is coupled to the output terminal of the first initial pulse signal generating sub-circuit 3212, and the drain of the fourth PMOS transistor MP4 is coupled to the input terminal of the first initial pulse signal generating sub-circuit 3212. The drain of the third NMOS transistor MN3 is coupled to the drain of the fourth PMOS transistor MP4, the gate of the third NMOS transistor MN3 is coupled to the gate of the fourth PMOS transistor MP4, and the source of the third NMOS transistor MN3 is coupled to the drain of the fourth NMOS transistor MN 4. The gate of the fourth NMOS transistor MN4 is coupled to the positive clock signal CK, and the source of the fourth NMOS transistor MN4 is grounded VSS.

The level state of the preamble signal inputted to the first initial pulse signal generation sub-circuit is locked by the lock sub-circuit, and when the forward clock signal is at a high level, the first initial pulse signal generation sub-circuit can maintain the first initial pulse signal at a low level outputted.

Fig. 5 shows a schematic structural diagram of a second initial pulse signal generating circuit in an embodiment of the present invention, and in a specific implementation, the second initial pulse signal generating circuit 322 may include: a second initial pulse signal generation sub-circuit 3221 and a second switching sub-circuit 3222. Wherein an input end of the second initial pulse signal generating sub-circuit 3221 is adapted to access the pulse signal and the control signal, and the second initial pulse signal generating sub-circuit 3221 is adapted to generate a second initial pulse signal according to the control signal and the pulse signal. The input end of the second switch sub-circuit 3222 is adapted to access the second initial pulse signal, to turn on when the clock signal is at a low level, and to maintain the initial pulse signal at a low level before a falling edge of the control signal, and to generate a rising edge of the initial pulse signal following the falling edge of the control signal.

Continuing with the example of the pulse generating circuit shown in fig. 6, in a specific implementation, the second initial pulse signal generating sub-circuit 3221 may include a second nand gate U2. In a specific implementation, a first input of the second nand gate U2 is adapted to receive the pulse signal, a second input of the second nand gate U2 is adapted to receive the control signal LRESET, and the second nand gate U2 is adapted to generate a second initial pulse signal according to the pulse signal and the control signal LRESET.

Specifically, if both the control signal LRESET and the pulse signal are at a high level, the second nand gate U2 outputs a first initial pulse signal at a low level, and if at least one of the control signal LRESET and the pulse signal is at a low level, the second nand gate U2 outputs a first initial pulse signal at a high level.

As mentioned above, the clock signal may include a forward clock signal CK and a reverse clock signal CK _ N, a first edge of the clock signal is a rising edge of the forward clock signal CK, and a second edge of the clock signal is a falling edge of the forward clock signal CK.

With continued reference to fig. 6, in a specific implementation, the second switch sub-circuit 3222 may include: a fifth PMOS transistor MP5 and a fifth NMOS transistor MN 5. A source of the fifth PMOS transistor MP5 is coupled to the output terminal of the second initial pulse signal generating sub-circuit 3221, a gate of the fifth PMOS transistor MP5 is coupled to the forward clock signal CK, and a drain of the fifth PMOS transistor MP5 is coupled to the input terminal of the inverting circuit 323. A drain of the fifth NMOS transistor MN5 is coupled to the output terminal of the second initial pulse signal generating sub-circuit 3221, a gate of the fifth NMOS transistor MN5 is coupled to the inverted clock signal CK _ N, and a source of the fifth NMOS transistor MN5 is coupled to a drain of the fifth PMOS transistor MP 5.

It will be understood by those skilled in the art that the description herein is merely for example, and in other embodiments, the second switch sub-circuit 3222 may be a circuit device for implementing circuit on and off, which is not limited thereto.

By providing a first initial pulse signal generating circuit that generates a second edge of an initial pulse signal when the clock signal is at a first level and maintains the initial pulse signal at a second level until the second edge of the clock signal arrives, a second initial pulse signal generating circuit that maintains the second level of the initial pulse signal before the clock signal is at the second level and the second edge of the control signal arrives and generates a first edge of the initial pulse signal following the second edge of the control signal when the clock signal is at the second level, and an inverter circuit that is adapted to invert the initial pulse signal and output the first edge and the second edge of the pulse signal. The transition of the pulse signal from the first level to the second level follows the changing transition of the control signal, so that the pulse width of the resulting pulse signal can be changed.

With continued reference to fig. 6, in a specific implementation, the control circuit 31 may include: a second inverter I2, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a ninth PMOS transistor MP9, an eighth NMOS transistor MN8, a third inverter I3, and a fourth inverter I4.

In a specific implementation, an input terminal of the second inverter I2 is coupled to the output terminal of the pulse signal generating circuit 32, and an output terminal of the second inverter I2 is coupled to the gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN 6.

Further, a source of the sixth PMOS transistor MP6 is coupled to a power supply VDD, and a drain of the sixth PMOS transistor MP6 is coupled to a source of the seventh PMOS transistor MP 7. The gate of the seventh PMOS transistor MP7 is grounded to VSS, and the drain of the seventh PMOS transistor MP7 is coupled to the source of the eighth PMOS transistor MP 8. The gate of the eighth PMOS transistor is grounded VSS, and the drain of the eighth PMOS transistor MP8 is coupled to the drain of the sixth NMOS transistor MN 6. The source of the sixth NMOS transistor MN6 is grounded to VSS, and the drain of the sixth NMOS transistor MN6 is coupled to the gate of the ninth PMOS transistor MP 9.

In one implementation, the gate of the seventh NMOS transistor MN7 is coupled to the drain of the sixth NMOS transistor MN6, and the source and drain of the seventh NMOS transistor MN7 are both grounded to VSS. The source of the ninth PMOS transistor MP9 is coupled to the power VDD, the gate of the ninth PMOS transistor MP9 is coupled to the gate of the eighth NMOS transistor MN8, and the drain of the ninth PMOS transistor MP9 is coupled to the drain of the eighth NMOS transistor MN 8. The source of the eighth NMOS transistor MN8 is grounded to VSS, and the drain of the eighth NMOS transistor MN8 is coupled to the input of the third inverter I3.

In a specific implementation, the output of the third inverter I3 is coupled to the input of the fourth inverter I4. The output of the fourth inverter I4 is adapted to output the control signal LRESET.

It should be understood by those skilled in the art that the foregoing is only an example of the control circuit 31, in a specific implementation, the control circuit 31 may also be in other forms to implement the delay output control signal LRESET, and the circuit structure of the control circuit is not particularly limited.

With continued reference to fig. 3, in a specific implementation, the pulse generation circuit 30 may further include: and a clock signal generation circuit 33, wherein the clock signal generation circuit 33 receives an initial clock signal as an input and outputs the clock signal.

As previously described, the clock signal may include a forward clock signal and a reverse clock signal. In combination with the pulse generating circuit shown in fig. 6, in a specific implementation, the clock signal generating circuit 33 may include: a fifth inverter I5 and a sixth inverter I6.

In a specific implementation, an output terminal of the fifth inverter I5 is coupled to an input terminal of the sixth inverter I6, the fifth inverter I5 is adapted to invert the input initial clock signal CLK and output the inverted clock signal CK _ N, and the sixth inverter I6 is adapted to invert the inverted clock signal CK _ N and output the forward clock signal CK.

In other embodiments, the clock signal generating circuit 33 may include only one inverter, the forward clock signal CK may be the initial clock signal CLK, and the reverse clock signal CK _ N may be a signal obtained by inverting the clock signal through the inverter.

It will be understood by those skilled in the art that the foregoing is merely exemplary and not limiting to the circuit configuration of the clock signal generating circuit 33, and in other embodiments, the circuit configuration may be in other forms, which are not limited thereto.

With continued reference to fig. 3, in a specific implementation, the pulse generation circuit 30 may further include: a shaping output circuit 34, wherein the shaping output circuit 34 is suitable for shaping and outputting the pulse signal generated by the pulse signal generating circuit 32.

With continued reference to the pulse generation circuit shown in fig. 6, in a specific implementation, the shaping output circuit 34 may include: a seventh inverter I7 and an eighth inverter I8.

In a specific implementation, an input terminal of the seventh inverter I7 is coupled to the output terminal of the PULSE signal generating circuit 22, an output terminal of the seventh inverter I7 is coupled to an input terminal of the eighth inverter I8, and the seventh inverter I7 and the eighth inverter I8 are adapted to shape the PULSE signal FB to output a shaped PULSE signal PULSE.

The pulse signal is shaped and output through the shaping output circuit, interference signals in the pulse signal can be eliminated, and the pulse signal with a regular waveform can be output.

In order to facilitate a more clear understanding of the present invention for those skilled in the art, the following description is provided with reference to a waveform diagram of a pulse signal generated by the pulse generating circuit of fig. 6 shown in fig. 7.

In a specific implementation, after the pulse generating circuit is powered on, the level state of the pulse signal FB output by the pulse signal generating circuit 32 is uncertain because the high-low level of the input initial clock signal CLK is uncertain. When the pulse signal FB output from the pulse signal generation circuit 32 is at a high level, the control circuit 31 outputs the control signal LRESET at a low level by a delay. The pulse signal generation circuit 32 receives the low-level control signal LRESET as an input, and can change the output pulse signal FB to a low level, thereby completing initialization of the pulse generation circuit.

Referring to fig. 6 and 7 in combination, after the circuit is initialized, when the input initial clock signal CLK is at a low level, the second initial pulse signal generating circuit 322 outputs the initial pulse signal at a high level according to the accessed control signal LRESET at a high level and the pulse signal FB at a low level, so that the inverter circuit 323 outputs the pulse signal FB at a low level, corresponding to the signal waveform shown in the time period T1 in fig. 7.

When the initial clock signal CLK jumps from the low level to the high level, the first initial pulse signal generating circuit 321 outputs an initial pulse signal according to the accessed control signal LRESET and the preamble signal. Since the leading signal generating sub-circuit 3211 outputs a leading signal at a high level according to the voltage supplied from the power supply VDD when the initial clock signal CLK is at a low level, and the control signal LRESET is at a high level, the first initial pulse signal generating circuit 321 outputs an initial pulse signal at a low level and the inverter circuit 323 outputs a pulse signal FB at a high level when the initial clock signal CLK jumps from a low level to a high level, so that a rising edge F2 (shown in fig. 7) of the pulse signal FB is generated according to a rising edge F1 (shown in fig. 7) of the initial clock signal CLK.

When the initial clock signal CLK maintains a high level, the lock sub-circuit 3214 receives the low-level first initial pulse signal output from the first initial pulse signal generating sub-circuit 3212, and locks the preamble signal input to the first initial pulse signal generating sub-circuit 3212 at a high level. The first initial pulse signal generating sub-circuit 3212 keeps outputting the first initial pulse signal at a low level, and the inverter circuit 323 keeps outputting the pulse signal FB at a high level, corresponding to the signal waveform shown in the time period T2 in fig. 7.

When the initial clock signal CLK jumps from the high level to the low level, the second initial pulse signal generation circuit 322 outputs the initial pulse signal of the low level according to the accessed control signal LRESET of the high level and the pulse signal FB of the high level, and the inverter circuit 323 outputs the pulse signal FB of the high level, thereby maintaining the pulse signal FB at the high level.

Further, when the high-level pulse signal FB is input to the control circuit 21 and delayed by the control circuit 31 to output the low-level control signal LRESET, at this time, the initial clock signal CLK is at a low level, the second initial pulse signal generating circuit 322 outputs the high-level initial pulse signal according to the accessed low-level control signal LRESET and the high-level pulse signal FB, and the inverting circuit 323 outputs the low-level pulse signal FB. Thus, the falling edge F3 of the pulse signal FB is generated following the falling edge F4 of the control signal LRESET.

In the pulse generating circuit shown in fig. 6, the delay time of the control circuit 31 is longer than the high level period of the initial pulse signal CLK, and thus, the pulse width L3 of the generated pulse signal FB is larger than the pulse width L2 of the initial clock signal CLK, changing the pulse width of the generated pulse signal FB.

In the embodiment of the invention, the output time of the falling edge of the control signal can be adjusted by adjusting the delay time output by the control circuit, and the falling edge of the pulse signal output by the pulse signal generating circuit is generated along with the falling edge of the control signal, so that the pulse width of the output pulse signal can be changed.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.