阅读说明：本技术 薄膜晶体管及其制造方法、阵列基板和显示装置 (Thin film transistor, manufacturing method thereof, array substrate and display device ) 是由 闫雷 李峰 方业周 樊君 李磊 孟艳艳 姚磊 薛进进 王成龙 王金锋 候林 郭 于 2019-01-29 设计创作，主要内容包括：本公开提供了一种薄膜晶体管及其制造方法、阵列基板和显示装置。所述薄膜晶体管包括：位于衬底一侧的有源层；第一层间电介质层,位于所述有源层远离所述衬底的一侧；源极,贯穿所述第一层间电介质层、且连接到所述有源层；第二层间电介质层,位于所述第一层间电介质层远离所述有源层的一侧、且覆盖所述源极；和漏极,包括第一部分,所述第一部分贯穿所述第二层间电介质层和所述第一层间电介质层、且连接到所述有源层。(The disclosure provides a thin film transistor, a manufacturing method thereof, an array substrate and a display device. The thin film transistor includes: an active layer on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source electrode penetrating the first interlayer dielectric layer and connected to the active layer; the second interlayer dielectric layer is positioned on one side, far away from the active layer, of the first interlayer dielectric layer and covers the source electrode; and a drain electrode including a first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.)

1. A thin film transistor, comprising:

an active layer on one side of the substrate;

a first interlayer dielectric layer located on one side of the active layer away from the substrate;

a source electrode penetrating the first interlayer dielectric layer and connected to the active layer;

the second interlayer dielectric layer is positioned on one side, far away from the active layer, of the first interlayer dielectric layer and covers the source electrode; and

a drain electrode including a first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

2. The thin film transistor of claim 1, wherein the drain electrode further comprises:

a second portion connected to the first portion, on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, the second portion being configured to be connected to a first electrode.

3. The thin film transistor of claim 2, wherein an orthographic projection of the second portion of the drain on the substrate partially overlaps with an orthographic projection of the source on the substrate.

4. The thin film transistor of claim 3, wherein a second portion of the drain electrode extends on a surface of the second interlayer dielectric layer in a direction toward the source electrode.

5. The thin film transistor of any of claims 1-4, wherein the active layer has at least one of a first recess and a second recess, wherein:

the source contacts the bottom and sides of the first recess and the first portion of the drain contacts the bottom and sides of the second recess.

6. The thin film transistor of claim 5, further comprising a buffer layer between the substrate and the active layer, wherein at least one of the first portions of the source and drain electrodes extends into the buffer layer.

7. The thin film transistor of claim 6, further comprising:

a light shielding layer located between the substrate and the buffer layer;

wherein an orthographic projection of the active layer on the substrate overlaps with an orthographic projection of the light shielding layer on the substrate.

8. The thin film transistor of claim 7, wherein the thin film transistor comprises a gate dielectric layer and a gate, wherein:

the gate dielectric layer is positioned on one side of the active layer far away from the substrate;

the gate is positioned on one side of the gate dielectric layer far away from the active layer;

the first interlayer dielectric layer is positioned on one side of the gate dielectric layer far away from the substrate and covers the gate.

9. The thin film transistor of claim 8, wherein the material of the active layer comprises polysilicon.

10. An array substrate, comprising:

the thin film transistor according to any one of claims 1 to 9.

11. The array substrate of claim 10, further comprising:

a planarization layer on a side of the second interlayer dielectric layer of the thin film transistor away from the first interlayer dielectric layer, the planarization layer having an opening extending to a second portion of the drain of the thin film transistor; and

a first electrode at least partially disposed in the opening and in contact with a second portion of the drain electrode.

12. The array substrate of claim 11, wherein the first electrode is a pixel anode;

the array substrate further includes: the insulating layer is positioned on one side of the second part of the first electrode, which is far away from the drain electrode;

and the common electrode is positioned on one side of the insulating layer, which is far away from the first electrode.

13. The array substrate of claim 11, wherein the first electrode is an anode.

14. A display device, comprising: the array substrate of any one of claims 10-13.

15. A method of manufacturing a thin film transistor, comprising:

forming an active layer on one side of a substrate;

forming a first interlayer dielectric layer on one side of the active layer away from the substrate;

forming a source electrode penetrating the first interlayer dielectric layer and connected to the active layer;

forming a second interlayer dielectric layer which is positioned on one side of the first interlayer dielectric layer far away from the active layer and covers the source electrode; and

forming a drain electrode including a first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

16. The method of claim 15, wherein forming a source electrode through the first interlayer dielectric layer and connected to the active layer comprises:

forming a first opening through the first interlayer dielectric layer, the first opening exposing a portion of the active layer;

forming the source electrode at least partially in the first opening and in contact with the active layer.

17. The method of claim 16, wherein forming a drain comprises:

forming a second opening through the second interlayer dielectric layer and the first interlayer dielectric layer, the second opening exposing a portion of the active layer;

and forming the drain electrode, wherein a first part of the drain electrode is positioned in the second opening and is in contact with the active layer.

18. The method of claim 17, wherein forming an active layer on one side of the substrate comprises:

forming a buffer layer on the one side of the substrate;

forming the active layer on one side of the buffer layer far away from the substrate;

wherein at least one of the first portions of the source and drain extends into the buffer layer.

19. The method of claim 18, wherein forming a buffer layer on the one side of the substrate comprises:

forming a light-shielding layer on the one side of the substrate;

forming the buffer layer on the one side of the substrate and covering the light-shielding layer;

wherein an orthographic projection of the active layer on the substrate at least partially overlaps with an orthographic projection of the light shielding layer on the substrate.

20. The method of claim 19, further comprising:

after an active layer on one side of the substrate is formed, a gate dielectric layer is formed on one side, far away from the substrate, of the active layer;

forming a gate on the side of the gate dielectric layer far away from the active layer;

wherein the first interlayer dielectric layer is positioned on one side of the gate dielectric layer far away from the substrate and covers the gate.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method for manufacturing the thin film transistor, an array substrate, and a display device.

Background

To meet the high resolution display requirement, the PPI (pixel Per Inch, number of Pixels Per Inch) of the display panel needs to be higher and higher. Especially, display products based on VR (Virtual Reality) technology have more stringent requirements on resolution.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided a thin film transistor including: an active layer on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source electrode penetrating the first interlayer dielectric layer and connected to the active layer; the second interlayer dielectric layer is positioned on one side, far away from the active layer, of the first interlayer dielectric layer and covers the source electrode; and a drain electrode including a first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

In some embodiments, the drain further comprises: a second portion connected to the first portion, on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, the second portion being configured to be connected to a first electrode.

In some embodiments, an orthographic projection of the second portion of the drain on the substrate partially overlaps an orthographic projection of the source on the substrate.

In some embodiments, a second portion of the drain extends on a surface of the second interlayer dielectric layer in a direction toward the source.

In some embodiments, the active layer has at least one of a first recess and a second recess, wherein: the source contacts the bottom and sides of the first recess and the first portion of the drain contacts the bottom and sides of the second recess.

In some embodiments, the thin film transistor further comprises a buffer layer between the substrate and the active layer, wherein at least one of the first portions of the source and drain electrodes extends into the buffer layer.

In some embodiments, the thin film transistor further comprises: a light shielding layer located between the substrate and the buffer layer; wherein an orthographic projection of the active layer on the substrate overlaps with an orthographic projection of the light shielding layer on the substrate.

In some embodiments, the thin film transistor comprises a gate dielectric layer and a gate, wherein: the gate dielectric layer is positioned on one side of the active layer far away from the substrate; the gate is positioned on one side of the gate dielectric layer far away from the active layer; the first interlayer dielectric layer is positioned on one side of the gate dielectric layer far away from the substrate and covers the gate.

In some embodiments, the material of the active layer comprises polysilicon.

According to another aspect of the embodiments of the present disclosure, there is provided an array substrate including: the thin film transistor according to any one of the above embodiments.

In some embodiments, the array substrate further comprises: a planarization layer on a side of the second interlayer dielectric layer of the thin film transistor away from the first interlayer dielectric layer, the planarization layer having an opening extending to a second portion of the drain of the thin film transistor; and a first electrode at least partially located in the opening and in contact with a second portion of the drain electrode.

In some embodiments, the first electrode is a pixel anode; the array substrate further includes: the insulating layer is positioned on one side of the second part of the first electrode, which is far away from the drain electrode; and the common electrode is positioned on one side of the insulating layer, which is far away from the first electrode.

In some embodiments, the first electrode is an anode.

According to still another aspect of the embodiments of the present disclosure, there is provided a display device including: the array substrate according to any of the above embodiments.

According to still another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a thin film transistor, including: forming an active layer on one side of a substrate; forming a first interlayer dielectric layer on one side of the active layer away from the substrate; forming a source electrode penetrating the first interlayer dielectric layer and connected to the active layer; forming a second interlayer dielectric layer which is positioned on one side of the first interlayer dielectric layer far away from the active layer and covers the source electrode; and forming a drain electrode including a first portion penetrating the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

In some embodiments, forming a source electrode through the first interlayer dielectric layer and connected to the active layer comprises: forming a first opening through the first interlayer dielectric layer, the first opening exposing a portion of the active layer; forming the source electrode at least partially in the first opening and in contact with the active layer.

In some embodiments, forming the drain comprises: forming a second opening through the second interlayer dielectric layer and the first interlayer dielectric layer, the second opening exposing a portion of the active layer; and forming the drain electrode, wherein a first part of the drain electrode is positioned in the second opening and is in contact with the active layer.

In some embodiments, forming an active layer on one side of the substrate comprises: forming a buffer layer on the one side of the substrate; forming the active layer on one side of the buffer layer far away from the substrate; wherein at least one of the first portions of the source and drain extends into the buffer layer.

In some embodiments, forming a buffer layer on the one side of the substrate comprises: forming a light-shielding layer on the one side of the substrate; forming the buffer layer on the one side of the substrate and covering the light-shielding layer; wherein an orthographic projection of the active layer on the substrate at least partially overlaps with an orthographic projection of the light shielding layer on the substrate.

In some embodiments, the method further comprises: after an active layer on one side of the substrate is formed, a gate dielectric layer is formed on one side, far away from the substrate, of the active layer; forming a gate on the side of the gate dielectric layer far away from the active layer; wherein the first interlayer dielectric layer is positioned on one side of the gate dielectric layer far away from the substrate and covers the gate.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 is a schematic structural diagram of a thin film transistor according to one embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure;

fig. 6 is a schematic structural view of an array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural view of an array substrate according to another embodiment of the present disclosure;

FIG. 8 is a schematic flow chart diagram of a method of fabricating a thin film transistor according to one embodiment of the present disclosure;

fig. 9A-9G illustrate schematic cross-sectional views of structures resulting from different stages of forming a thin film transistor, according to some embodiments of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be intervening components between the specific component and the first component or the second component. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without having an intervening component, or may be directly connected to the other components without having an intervening component.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

When the PPI is large, the Pitch (Pitch) between adjacent sub-pixels needs to be small. The inventors have noticed that, since the pitch between adjacent sub-pixels is small, when forming the source and drain electrodes of the thin film transistor in each sub-pixel, the source and drain electrodes are easily overlapped, resulting in poor reliability of the thin film transistor, thereby generating a display defect such as a dark spot, which affects the display effect.

Therefore, the embodiment of the disclosure provides the following technical solutions.

Fig. 1 is a schematic structural diagram of a thin film transistor according to one embodiment of the present disclosure.

As shown in fig. 1, the thin film transistor 100 includes an active layer 102, a first interlayer dielectric layer 103, a source electrode 104, a second interlayer dielectric layer 105, and a drain electrode 106 on one side of a substrate 101.

The substrate 101 may be, for example, a glass substrate. However, the present disclosure is not limited thereto. For example, in some embodiments, the substrate 101 may also be a flexible substrate such as a Polyimide (PI) substrate.

The active layer 102 is located on one side, e.g., an upper side, of the substrate 101. In some embodiments, the material of the active layer 102 may include polysilicon, such as Low Temperature Polysilicon (LTPS). In other embodiments, the material of the active layer 102 may include an oxide semiconductor.

The first inter-layer dielectric layer 103 is located on a side of the active layer 102 remote from the substrate 101. For example, the material of the first interlayer dielectric layer 103 may include an oxide of silicon, a nitride of silicon, an oxynitride of silicon, and the like.

The source electrode 104 penetrates the first interlayer dielectric layer 103 and is connected to the active layer 102. The source 104 may be, for example, a stack of Ti/Al/Ti. In some embodiments, the source 104 may be in contact with a surface (also referred to as an upper surface) of the active layer 102 on a side away from the substrate 101.

The second interlayer dielectric layer 105 is located on a side of the first interlayer dielectric layer 103 away from the active layer 102 and covers the source electrode 104. The material of the second interlayer dielectric layer 105 may be the same as or different from the material of the first interlayer dielectric layer 105. For example, the material of the second interlayer dielectric layer 105 may include an oxide of silicon, a nitride of silicon, an oxynitride of silicon, and the like.

The drain 106 includes a first portion 116. The first portion 116 penetrates the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103, and is connected to the active layer 102. In some embodiments, the first portion 116 may be in contact with a surface of the active layer 102 on a side away from the substrate 101. By way of example, the first portion 116 may be a stack of Ti/Al/Ti, for example. It is understood that thin film transistor 100 also includes a gate dielectric layer and a gate electrode. In some embodiments, the thin film transistor 100 may be a top gate type thin film transistor. In other embodiments, the thin film transistor 100 may be a bottom gate type thin film transistor. In the case where the thin film transistor 100 is a top gate thin film transistor, as shown in fig. 1, the gate dielectric layer 107 is located on a side of the active layer 102 away from the substrate 101, the gate electrode 108 is located on a side of the gate dielectric layer 107 away from the active layer 102, and the first interlayer dielectric layer 103 is located on a side of the gate dielectric layer 107 away from the substrate 101 and covers the gate electrode 108. In some embodiments, the gate dielectric layer 107 may cover the active layer 102.

In the above embodiment, the source electrode 104 penetrates the first interlayer dielectric layer 103, the second interlayer dielectric layer 105 covers the source electrode 104, and the first portion 116 of the drain electrode 106 penetrates the second interlayer dielectric layer 105. In such a thin film transistor, the source electrode 104 and the drain electrode 106 are located on different layers, and the source electrode 104 and the drain electrode 106 are not overlapped even if they are arranged close to each other in a direction parallel to the surface of the substrate 101, thereby improving the reliability of the thin film transistor. When the thin film transistor is applied to the display panel, the occurrence of poor display phenomena such as dark spots caused by the overlapping of the source electrode and the drain electrode can be reduced, and the display effect of the display panel is improved.

Fig. 2 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.

In contrast to the thin film transistor 100 shown in fig. 1, the drain electrode 106 in the thin film transistor 200 shown in fig. 2 further includes a second portion 126 connected to the first portion 116. The second portion 126 is located on a side of the second interlayer dielectric layer 105 remote from the first interlayer dielectric layer 103. The second portion 126 is configured to be connected to the first electrode. Here, the first electrode may be, for example, a pixel electrode or an anode electrode.

In some embodiments, the orthographic projection of the second portion 126 of the drain electrode 106 on the substrate 101 partially overlaps the orthographic projection of the source electrode 104 on the substrate 101, thereby facilitating a reduction in the size of the thin film transistor. In some embodiments, the second portion 126 of the drain electrode 106 extends on the surface of the second interlayer dielectric layer 105 in a direction toward the source electrode 104, rather than in a direction away from the source electrode 104, thereby contributing to further reducing the size of the thin film transistor.

In the above embodiment, the drain electrode 106 further includes the second portion 126 configured to be connected to the first electrode. The second inter-level dielectric layer 105 covers the source 104 and the second portion 126 of the drain 106 is located on a side of the second inter-level dielectric layer 105 remote from the first inter-level dielectric layer 103. Such a thin film transistor makes the contact of the first electrode with the drain electrode 106 more reliable. In addition, since the second portions 126 of the source electrode 104 and the drain electrode 106 are located at different layers, they do not overlap even if they are disposed very close to each other in a direction parallel to the surface of the substrate 101, thereby improving reliability of the thin film transistor. When the thin film transistor is applied to the display panel, the occurrence of poor display phenomena such as dark spots caused by the overlapping of the source electrode and the drain electrode can be reduced, and the display effect of the display panel is improved.

Fig. 3 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure.

In contrast to the thin film transistor 200 shown in fig. 2, the active layer 102 in the thin film transistor 300 shown in fig. 3 may have at least one of a first recess and a second recess. Here, the source electrode 104 contacts the bottom and side surfaces of the first recess, and the first portion 116 of the drain electrode 106 contacts the bottom and side surfaces of the second recess. Such a thin film transistor may increase a contact area of at least one of the first portions 116 of the source and drain electrodes 104 and 106 with the active layer 102, thereby reducing contact resistance.

Fig. 4 is a schematic structural diagram of a thin film transistor according to still another embodiment of the present disclosure.

In contrast to the thin film transistor 300 shown in fig. 3, the thin film transistor 400 shown in fig. 4 further includes a buffer layer 109 between the substrate 101 and the active layer 102. In some embodiments, buffer layer 109 may include, for example, a silicon nitride layer and a silicon oxide layer. A silicon nitride layer is located between the substrate 101 and a silicon oxide layer, which is located between the silicon nitride layer and the active layer 102. The silicon nitride layer can block metal ions such as sodium ions and potassium ions in the substrate 101 from entering the active layer 102, so as to prevent the metal ions from adversely affecting the performance of the active layer 102. The silicon oxide layer has a better interface performance with the active layer 102 on one hand, and also has a thermal insulation effect on the other hand. For example, the active layer 102 is polysilicon into which amorphous silicon is converted using Excimer Laser Annealing (ELA), and the oxide layer of silicon may block heat from being transferred downward when the amorphous silicon is irradiated with laser light, so that the amorphous silicon may be more efficiently converted into polysilicon.

At least one of the first portions 116 of the source 104 and the drain 106 may penetrate the active layer 102 and extend into the buffer layer 109, such as an oxide layer of silicon in the buffer layer 109. For example, a portion of the source electrode 104 is embedded in the buffer layer 109. As another example, a portion of first portion 116 may be embedded in buffer layer 109. As another example, a portion of the source 104 and a portion of the first portion 116 are both embedded in the buffer layer 109.

Fig. 5 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present disclosure.

In contrast to the thin film transistor 400 shown in fig. 4, the thin film transistor 500 shown in fig. 5 further includes a light-shielding layer 110 between the substrate 101 and the buffer layer 109. Here, an orthographic projection of the active layer 102 on the substrate 101 at least partially overlaps with an orthographic projection of the light shielding layer 110 on the substrate 101. In some embodiments, the material of the light-shielding layer 110 may include a metal material such as molybdenum having light-shielding properties.

The light shielding layer 110 may shield light (e.g., light emitted from a backlight module in the case of a thin film transistor applied in a liquid crystal display panel) from a side of the substrate 101 away from the active layer 102 to reduce a current generated by the active layer 102 upon irradiation of the light, thereby reducing a leakage current of the thin film transistor 400.

It should be noted that, although fig. 3-5 illustrate the drain 106 including the second portion 126, this is not limiting. In some embodiments, the drain 106 may not include the second portion 126.

Fig. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

As shown in fig. 6, the array substrate 600 includes a thin film transistor (e.g., the thin film transistor 100/200/300/400/500) provided in any of the above embodiments.

In some embodiments, the array substrate 600 may further include a planarization layer 201 and a first electrode 202.

The planarization layer 201 is located on a side of the second interlayer dielectric layer 105 of the thin film transistor 400 away from the first interlayer dielectric layer 103. The planarization layer 201 has an opening 211 that exposes a portion of the second portion 126 of the drain electrode 106 of the thin film transistor 400, i.e., the opening 211 is connected to the second portion 126. The material of the planarization layer 201 may include, for example, a resin material or the like.

The first electrode 202 is at least partially located in the opening 211 and is in contact with the second portion 126. For example, a portion of the first electrode 202 is located on the bottom and the sidewall of the opening 211, and the other portion is located on the planarization layer 201.

In some embodiments, the first electrode 202 may be an anode. In this case, the array substrate may further include a pixel defining layer partially covering the first electrode 202.

In other embodiments, the first electrode 202 may be a pixel electrode. In some embodiments, the array substrate may further include a common electrode (to be described later in conjunction with fig. 7). In other embodiments, the array substrate may not include the common electrode, for example, the common electrode may be disposed in the color filter substrate.

Fig. 7 is a schematic structural view of an array substrate according to another embodiment of the present disclosure.

Compared to the array substrate 600 of fig. 6, the array substrate 700 of fig. 7 further includes an insulating layer 203 and a common electrode 204. The insulating layer 203 is located on a side of the first electrode 202 away from the second portion 126, and the common electrode 204 is located on a side of the insulating layer 203 away from the first electrode 202. The insulating layer 203 isolates the first electrode 202 from the common electrode 204 to insulate the first electrode 202 from the common electrode 204. In some embodiments, the insulating layer 203 may cover a portion of the planarization layer 201. For example, the material of the insulating layer 203 may include silicon nitride or the like.

The embodiment of the disclosure also provides a display device. The display device may include the array substrate 600/700 of any of the above embodiments. In some embodiments, the display device may be any product or component with a display function, such as a display panel, a mobile terminal, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic paper, a virtual reality system, and the like.

In some embodiments, the display device may be an Organic Light-emitting diode (OLED) display panel. In other embodiments, the display device may be a liquid crystal display panel. Because the source electrode and the drain electrode of the thin film transistor in the display panel are positioned at different layers, the occurrence of poor display phenomena such as dark spots and the like caused by the lap joint of the source electrode and the drain electrode is reduced, and the display effect of the display panel is improved.

Fig. 8 is a flow chart illustrating a method of fabricating a thin film transistor according to one embodiment of the present disclosure. Fig. 9A-9G illustrate schematic cross-sectional views of structures resulting from different stages of forming a thin film transistor, according to some embodiments of the present disclosure. A process of forming a thin film transistor according to some embodiments of the present disclosure is described below with reference to fig. 8 and 9A-9G.

In step 802, an active layer 102 is formed on one side of a substrate 101, as shown in fig. 9A.

In some implementations, the buffer layer 109 on the side of the substrate 101 may be formed first, and then the active layer 102 may be formed on the side of the buffer layer 109 away from the substrate 101. In other implementations, the light-shielding layer 110 on one side of the substrate 101 may be formed first, the buffer layer 109 on one side of the substrate 101 and covering the light-shielding layer 110 may be formed, and the active layer 102 may be formed on one side of the buffer layer 109 away from the substrate 101. Here, an orthographic projection of the active layer 102 on the substrate 101 at least partially overlaps with an orthographic projection of the light shielding layer 110 on the substrate 101.

In some embodiments, referring to fig. 9A, after forming the active layer 102 on the side of the substrate 101, a gate dielectric layer 107 is formed on the side of the active layer 102 away from the substrate 101, and then a gate electrode 108 is formed on the side of the gate dielectric layer 107 away from the active layer 102. Such a manner can form a top gate type thin film transistor. In some implementations, the gate dielectric layer 107 may cover the active layer 102.

In other embodiments, a gate may be formed on a side of the substrate 101 and then a gate dielectric layer may be formed on a side of the gate away from the substrate 101 before forming the active layer 102 on the side of the substrate 101. Such a manner can form a bottom gate type thin film transistor.

At step 804, the first inter-level dielectric layer 103 is formed on the side of the active layer 102 away from the substrate 101, as shown in fig. 9B. In some embodiments, first inter-level dielectric layer 103 may be on a side of gate dielectric layer 107 away from substrate 101 and cover gate 108.

At step 806, a source electrode 104 is formed through the first inter-layer dielectric layer 103 and connected to the active layer 102.

For example, a first opening 10 may be formed through the first interlayer dielectric layer 103, the first opening 10 exposing a portion of the active layer 102, as shown in fig. 9C. In some implementations, the first opening 10 exposes an upper surface of the active layer 102. In other implementations, the first opening 10 may extend below the upper surface of the active layer 102. For example, the first interlayer dielectric layer 103 and the active layer 102 may be respectively etched using a suitable etchant to form the first opening 10. Then, a source electrode 104 at least partially located in the first opening 10 and contacting the active layer 102 is formed, as shown in fig. 9D.

In some embodiments, in the case of forming the buffer layer 109, the formed first opening 10 may extend into the buffer layer 109, i.e., the active layer 102 may be over-etched to reduce process difficulty. In this case, the source electrode 104 may extend into the buffer layer 109.

In step 808, a second interlayer dielectric layer 105 is formed on the first interlayer dielectric layer 103 away from the active layer 102 and covering the source electrode 104, as shown in fig. 9E.

In step 810, a drain electrode 106 is formed, thereby forming a thin film transistor. Here, the drain 106 includes at least a first portion 116. The first portion 116 penetrates the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103, and is connected to the active layer 102. In some embodiments, the drain 106 further includes a second portion 126 connected to the first portion 116. The second portion 126 is located on a side of the second interlayer dielectric layer 105 remote from the first interlayer dielectric layer 103. In some embodiments, the orthographic projection of the second portion 126 on the substrate 101 partially overlaps the orthographic projection of the source 104 on the substrate 101.

For example, a second opening 20 may be formed through the second interlayer dielectric layer 105 and the first interlayer dielectric layer 103, the second opening 20 exposing a portion of the active layer 102, as shown in fig. 9F. In some implementations, the second opening 20 exposes an upper surface of the active layer 102. In other implementations, the second opening 20 may extend below the upper surface of the active layer 102. Then, the source electrode 106 is formed as shown in fig. 9G. Here, the first portion 116 of the source electrode 106 is located in the second opening 20 and is in contact with the active layer 102.

In some embodiments, in the case of forming the buffer layer 109, the formed second opening 20 may extend into the buffer layer 109, i.e., the active layer 102 may be over-etched to reduce process difficulty. In this case, the first portion 116 may extend into the buffer layer 109.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.