Chromium-silicon film resistor and preparation method thereof
阅读说明：本技术 一种铬硅系薄膜电阻及其制备方法 (Chromium-silicon film resistor and preparation method thereof ) 是由 杨尚洁 杨永峰 张万垚 李林 折宇 陈宝忠 于 2021-06-15 设计创作，主要内容包括：本发明属于薄膜电阻制备技术领域,公开了一种铬硅系薄膜电阻及其制备方法,包括以下步骤：在衬底上使用化学气相沉积法沉积二氧化硅绝缘层；使用物理气相沉积法在二氧化硅绝缘层上先沉积铬硅电阻层,再沉积钛钨层；使用化学气相沉积法在钛钨层上沉积二氧化硅层,作为硬掩膜；在硬掩膜上完成电阻图形的制备；对二氧化硅层进行刻蚀,形成硬掩膜窗口；使用强氧化溶剂对硬掩膜窗口的钛钨层进行去除；对铬硅电阻层进行干法预刻蚀；使用湿法化学腐蚀法对铬硅电阻层进行腐蚀,得到铬硅系薄膜电阻。使用硬掩膜作为刻蚀阻挡层可解决湿法腐蚀的侵蚀问题,使用干法预刻蚀解决湿法腐蚀速率非线性变化的问题,可有效控制电阻图形的宽度、长度,提高电阻的精度。(The invention belongs to the technical field of thin film resistor preparation, and discloses a chromium-silicon thin film resistor and a preparation method thereof, wherein the preparation method comprises the following steps: depositing a silicon dioxide insulating layer on the substrate by using a chemical vapor deposition method; depositing a chromium-silicon resistance layer on the silicon dioxide insulating layer by using a physical vapor deposition method, and then depositing a titanium-tungsten layer; depositing a silicon dioxide layer on the titanium-tungsten layer by using a chemical vapor deposition method to serve as a hard mask; completing the preparation of a resistance pattern on the hard mask; etching the silicon dioxide layer to form a hard mask window; removing the titanium-tungsten layer of the hard mask window by using a strong oxidation solvent; carrying out dry pre-etching on the chromium silicon resistance layer; and corroding the chromium-silicon resistor layer by using a wet chemical corrosion method to obtain the chromium-silicon thin film resistor. The hard mask is used as an etching barrier layer, so that the corrosion problem of wet etching can be solved, the problem of nonlinear change of the wet etching rate is solved by using dry pre-etching, the width and the length of a resistor pattern can be effectively controlled, and the resistance precision is improved.)
1. A preparation method of a chromium-silicon film resistor is characterized by comprising the following steps:
s1, depositing a silicon dioxide insulating layer (2) on the substrate (1) by using a chemical vapor deposition method;
s2, depositing a chromium-silicon resistance layer (3) on the silicon dioxide insulating layer (2) by using a physical vapor deposition method, and then depositing a titanium-tungsten layer (4);
s3, depositing a silicon dioxide layer on the titanium tungsten layer (4) by using a chemical vapor deposition method to be used as a hard mask (5);
s4, completing the preparation of a resistance pattern on the hard mask (5);
s5, etching the silicon dioxide layer to form a hard mask window;
s6, removing the titanium-tungsten layer (4) of the hard mask window by using a strong oxidation solvent;
s7, carrying out dry pre-etching on the chromium-silicon resistor layer (3);
and S8, etching the chromium-silicon resistor layer (3) by using a wet chemical etching method to obtain the chromium-silicon film resistor.
2. The method for preparing the chromium-silicon thin film resistor as claimed in claim 1, wherein after S8, the chromium-silicon thin film resistor is post-processed, comprising the following steps:
(1) removing the photoresist on the surface silicon dioxide insulating layer (2) by a dry photoresist removing process;
(2) and (4) removing the residual photoresist and the polymer generated by dry pre-etching in S7 by adopting wet organic cleaning.
3. The method of claim 1, wherein the wet chemical etching process in S8 uses a mixture of nitric acid, hydrofluoric acid, and water.
4. The method of claim 1, wherein the temperature of the strong oxidation solvent is 30-80 ℃.
5. The method of claim 1, wherein the thickness of the silicon dioxide insulating layer (2) is 1-2 μm.
6. The method for preparing a chromium-silicon thin film resistor as claimed in claim 1, wherein the chromium-silicon resistor layer (3) has a thickness of
7. A method for manufacturing a chromium-silicon based thin film resistor as claimed in claim 1, characterized in that the thickness of the titanium-tungsten layer (4) is
8. The method of claim 1, wherein the chemical vapor deposition is performed by plasma chemical vapor deposition at a RF power of 300-2000W and a temperature of 350-500 ℃.
9. The method for preparing a chromium-silicon thin film resistor as claimed in claim 1, wherein the physical vapor deposition method comprises: the power source adopts a direct current source, a medium frequency source or a radio frequency source, and the power is controlled to be 100-2000W.
10. The chromium-silicon thin film resistor prepared by the preparation method of any one of claims 1 to 9 is characterized by comprising a substrate (1), a silicon dioxide insulating layer (2), a chromium-silicon resistor layer (3), a titanium-tungsten layer (4) and a hard mask (5) which are arranged from bottom to top; the width of the Cr-Si thin film resistor is 5-8 um.
Technical Field
The invention belongs to the technical field of thin film resistor preparation, and particularly relates to a chromium-silicon thin film resistor and a preparation method thereof.
Background
With the continuous progress and development of semiconductor integrated circuits, different diffusion resistors and injection resistors cannot meet the actual product requirements, and the requirements of high-precision thin film resistors on analog integrated circuits are further improved. Compared with diffusion and injection resistors, the metal film resistor has lower temperature coefficient, smaller parasitic parameter and wider range of sheet resistance value, and has higher resistance precision.
At present, no mature and effective manufacturing method exists for the width of chromium-silicon resistance (Cr-Si) below 10 μm in an analog integrated circuit.
Disclosure of Invention
The invention aims to provide a chromium-silicon thin film resistor and a preparation method thereof, which solve the problem that the chromium-silicon thin film resistor (Cr-Si) with the width of less than 10 mu m can not be prepared in the prior art.
The invention is realized by the following technical scheme:
a preparation method of a chromium-silicon film resistor comprises the following steps:
s1, depositing a silicon dioxide insulating layer on the substrate by using a chemical vapor deposition method;
s2, depositing a chromium-silicon resistance layer on the silicon dioxide insulating layer by using a physical vapor deposition method, and then depositing a titanium-tungsten layer;
s3, depositing a silicon dioxide layer on the titanium tungsten layer by using a chemical vapor deposition method to be used as a hard mask;
s4, preparing a resistance pattern on the hard mask;
s5, etching the silicon dioxide layer to form a hard mask window;
s6, removing the titanium-tungsten layer of the hard mask window by using a strong oxidation solvent;
s7, carrying out dry pre-etching on the chromium-silicon resistance layer;
and S8, etching the chromium-silicon resistor layer by using a wet chemical etching method to obtain the chromium-silicon film resistor.
Further, after S8, post-processing the cr-si based thin film resistor, specifically including the steps of:
(1) removing the photoresist on the silicon dioxide insulating layer on the surface layer by a dry photoresist removing process;
(2) and (4) removing the residual photoresist and the polymer generated by dry pre-etching in S7 by adopting wet organic cleaning.
Further, in S8, the solution used in the wet chemical etching method is a mixed solution of nitric acid, hydrofluoric acid, and water.
Further, the temperature of the strong oxidation solvent is 30 ℃ to 80 ℃.
Further, the thickness of the silicon dioxide insulating layer is 1-2 μm.
Further, the chromium silicon resistance layer has a thickness of
Further, the thickness of the titanium tungsten layer is
Further, the chemical vapor deposition method adopts a plasma chemical vapor deposition method, the radio frequency power is 300W-2000W, and the temperature is 350 ℃ to 500 ℃.
Further, the physical vapor deposition method specifically comprises: the power source adopts a direct current source, a medium frequency source or a radio frequency source, and the power is controlled to be 100-2000W.
The invention also discloses a chromium-silicon thin film resistor prepared by the preparation method of the public security particles, which comprises a substrate, a silicon dioxide insulating layer, a chromium-silicon resistor layer, a titanium-tungsten layer and a hard mask which are arranged from bottom to top; the width of the Cr-Si thin film resistor is 5-8 um.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention discloses a preparation method of a chromium-silicon thin film resistor, which comprises the steps of firstly copying a hard mask pattern on a resistor layer by adopting a photoetching technology and a plasma etching technology, then etching the resistor pattern by using the hard mask as an etching barrier layer and using a dry pre-etching and wet etching method to form the thin film resistor with the width of less than 10 mu m; compared with the prior art, the method has the advantages that the etching problem of wet etching can be solved by using the hard mask as the etching barrier layer, the problem of nonlinear change of the wet etching rate can be solved by using dry pre-etching, the width and the length of the resistor graph can be effectively controlled by the method, and the resistor precision is improved.
Drawings
FIG. 1 is a flow chart of the method for manufacturing a chromium-silicon based thin film resistor according to the present invention.
FIG. 2 is a schematic structural diagram of a Cr-Si based thin film resistor according to the present invention.
Wherein, 1 is a substrate, 2 is a silicon dioxide insulating layer, 3 is a chromium silicon resistance layer, 4 is a titanium tungsten layer, and 5 is a hard mask.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
Example 1
The invention discloses a preparation method of a chromium-silicon film resistor, which comprises the following steps:
s1: a wafer silicon wafer is used as a substrate 1, and a silicon dioxide insulating layer 2 with the thickness of 1 mu m is deposited on the wafer by adopting a chemical vapor deposition process to form an insulating surface.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 300W, the temperature is 400 ℃, and the reaction gas adopts silane and N2O。
Step S2, depositing the chromium silicon resistor layer 3 on the silicon dioxide insulating layer 2 by using a physical vapor deposition method, and then depositing the titanium tungsten layer 4: adopting a direct current power source, controlling the power at 400W, adopting argon and nitrogen as gases, and depositing to obtain the film with the thickness ofHas a thickness ofA titanium tungsten layer 4.
Step S3: chemical vapor deposition of titanium tungsten filmDeposited in a thickness ofThe silicon dioxide layer, which serves as a hard mask 5, is used as a masking layer for subsequent etching.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 300W, and the temperature isThe reaction gas adopts silane and N2O。
Step S4, completing the preparation of the resistor pattern on the hard mask 5:
a layer of photoresist can be coated on the hard mask 5 by adopting the photoetching process of chip manufacturing, and the processes of exposure and development are carried out, so that the required pattern is left on the photoresist, and the width of the resistor is 8 mu m.
Step S5, etching the silicon dioxide layer to form a hard mask window:
a plasma dry etching process for manufacturing the bipolar circuit chip can be adopted to etch a pattern window on the hard mask 5, and the titanium-tungsten layer 4 is stopped, so that no silicon dioxide residue is left on the titanium-tungsten layer 4.
The parameters of the hard mask 5 etching process are as follows: the pressure in the process chamber was adjusted to 1500mT, the RF source power was 600W, and the etching process reaction gases used CF4, CHF3, and Ar.
Step S6: and (3) performing wet etching on the titanium-tungsten layer 4 of the hard mask window by using hydrogen peroxide at the temperature of 30 ℃, and stopping on the chromium-silicon layer to ensure that no titanium-tungsten residue exists on the chromium-silicon layer.
Step S7: and (3) carrying out dry pre-etching on the chromium-silicon resistance layer 3 by adopting a dry plasma etching process: the chromium-silicon resistor layer 3 and the titanium-tungsten layer 4 directly form a nitrogen oxide layer, and the nitrogen oxide layer on the chromium-silicon surface layer needs to be pretreated, so that the chromium-silicon resistor layer 3 can be subjected to wet chemical corrosion subsequently.
The parameters of the dry plasma etching process are as follows: the pressure in the process chamber is 1500mT, the RF source power is 200W, and the etching process reaction gases are CF4 and Ar.
Step S8: and etching the chromium-silicon resistor layer 3 by using a mixed solution of nitric acid, hydrofluoric acid and water at 25 ℃ as a wet chemical etching solution to form the thin film resistor.
Step S9, post-processing: and removing the surface photoresist by a dry photoresist removing process, and removing the residual photoresist and the polymer generated by the dry process by adopting wet organic cleaning.
Example 2
The invention discloses a preparation method of a chromium-silicon film resistor, which comprises the following steps:
s1: a wafer silicon wafer is used as a substrate 1, and a 2-micron silicon dioxide insulating layer 2 is deposited on the wafer by adopting a chemical vapor deposition process to form an insulating surface.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 2000W, the temperature is 500 ℃, and the reaction gas adopts silane and N2O。
Step S2, depositing the chromium silicon resistor layer 3 on the silicon dioxide insulating layer 2 by using a physical vapor deposition method, and then depositing the titanium tungsten layer 4: adopting a radio frequency source, controlling the power at 2000W, adopting argon and nitrogen as gases, and depositing to obtain the film with the thickness ofHas a thickness ofA titanium tungsten layer 4.
Step S3: depositing a titanium tungsten film on the substrate to a thickness ofThe silicon dioxide layer, which serves as a hard mask 5, is used as a masking layer for subsequent etching.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 300W, the temperature is 400 ℃, and the reaction gas adopts silane and N2O。
Step S4, completing the preparation of the resistor pattern on the hard mask 5:
a layer of photoresist can be coated on the hard mask 5 by adopting the photoetching process of chip manufacturing, and the processes of exposure and development are carried out, so that the required pattern is left on the photoresist, and the width of the resistor is 8 mu m.
Step S5, etching the silicon dioxide layer to form a hard mask window:
a dry etching process for manufacturing the bipolar circuit chip can be adopted, a pattern window is etched on the hard mask 5, the titanium-tungsten layer 4 is stopped, and no silicon dioxide residue is left on the titanium-tungsten layer 4.
The parameters of the hard mask 5 etching process are as follows: the pressure in the process chamber was 1500mT, the RF source power was 600W, and the etching reaction gases used CF4, CHF3, and Ar.
Step S6: and (3) performing wet etching on the titanium-tungsten layer 4 of the hard mask window by using 60 ℃ hydrogen peroxide, and stopping on the chromium-silicon layer to ensure that no titanium-tungsten residue exists on the chromium-silicon layer.
Step S7: carrying out dry pre-etching on the chromium silicon resistance layer 3; the chromium-silicon resistor layer 3 and the titanium-tungsten layer 4 directly form a nitrogen oxide layer, and the nitrogen oxide layer on the chromium-silicon surface layer needs to be pretreated, so that the chromium-silicon resistor layer 3 can be subjected to wet chemical corrosion subsequently.
The parameters of the pretreatment process are as follows: the pressure in the process chamber is 1500mT, the power of the radio frequency source is 200W, and CF4 and Ar are used as etching reaction gases.
Step S8: and etching the chromium-silicon resistor layer 3 by using a mixed solution of nitric acid, hydrofluoric acid and water at 25 ℃ as a wet chemical etching solution to form the thin film resistor.
Step S9, post-processing: and removing the surface photoresist by a dry photoresist removing process, and removing the residual photoresist and the polymer generated by the dry process by adopting wet organic cleaning.
Example 3
The invention discloses a preparation method of a chromium-silicon film resistor, which comprises the following steps:
s1: a wafer silicon wafer is used as a substrate 1, and a silicon dioxide insulating layer 2 with the thickness of 1.5 mu m is deposited on the wafer by adopting a chemical vapor deposition process to form an insulating surface.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 1000W, the temperature is 350 ℃, and the reaction gas adopts silane and N2O。
Step S2, depositing the chromium silicon resistor layer 3 on the silicon dioxide insulating layer 2 by using a physical vapor deposition method, and then depositing the titanium tungsten layer 4: adopting a direct current power source, controlling the power at 100W, adopting argon and nitrogen as gases, and depositing to obtain the film with the thickness ofHas a thickness ofA titanium tungsten layer 4.
Step S3: depositing a titanium tungsten film on the substrate to a thickness ofThe silicon dioxide layer, which serves as a hard mask 5, is used as a masking layer for subsequent etching.
The parameters of the chemical vapor deposition process are as follows: the radio frequency power is 300W, the temperature is 400 ℃, and the reaction gas adopts silane and N2O。
Step S4, completing the preparation of the resistor pattern on the hard mask 5:
a layer of photoresist is coated on the hard mask 5 by a photolithography process for chip fabrication, and exposure and development processes are performed to leave a desired pattern on the photoresist, with a resistance width of 5 μm.
Step S5, etching the silicon dioxide layer to form a hard mask window:
a plasma dry etching process for manufacturing the bipolar circuit chip can be adopted to etch a pattern window on the hard mask 5, and the titanium-tungsten layer 4 is stopped, so that no silicon dioxide residue is left on the titanium-tungsten layer 4.
The parameters of the hard mask 5 etching process are as follows: the pressure in the process chamber was 1500mT, the RF source power was 600W, and the reactant gases used CF4, CHF3, and Ar.
Step S6: and (3) performing wet etching on the titanium-tungsten layer 4 of the hard mask window by using hydrogen peroxide at the temperature of 80 ℃, and stopping on the chromium-silicon layer to ensure that no titanium-tungsten residue exists on the chromium-silicon layer.
Step S7: carrying out dry pre-etching on the chromium silicon resistance layer 3; the chromium-silicon resistor layer 3 and the titanium-tungsten layer 4 directly form a nitrogen oxide layer, and the nitrogen oxide layer on the chromium-silicon surface layer needs to be pretreated, so that the chromium-silicon resistor layer 3 can be subjected to wet chemical corrosion subsequently.
The parameters of the pretreatment process are as follows: the pressure in the process chamber was 1500mT, the RF source power was 200W, and the reactant gases used were CF4 and Ar.
Step S8: and etching the chromium-silicon resistor layer 3 by using a mixed solution of nitric acid, hydrofluoric acid and water at 25 ℃ as a wet chemical etching solution to form the thin film resistor.
Step S9, post-processing: and removing the surface photoresist by a dry photoresist removing process, and removing the residual photoresist and the polymer generated by the dry process by adopting wet organic cleaning.
In summary, the hard mask 5 is patterned by dry etching, the excess titanium-tungsten layer 4 is removed by wet etching, the oxynitride layer on the surface of the chromium-silicon layer is removed by dry etching, and the chromium-silicon resistor layer 3 is patterned by wet etching to form the thin film resistor. Compared with the prior art, the chip manufacturing related technology is adopted, the control precision in the manufacturing process of the thin film resistor is improved, and the reliability of the thin film resistor is ensured.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.