阅读说明：本技术 一种像素数据处理方法和集成芯片 (Pixel data processing method and integrated chip ) 是由 魏巍 殷建东 于 2020-07-07 设计创作，主要内容包括：本发明公开了一种像素数据处理方法和集成芯片。该方法包括：若处理像素数据的当前工作频率超出有效工作频率范围,则确定实际并行处理的像素数,以使所述实际并行处理的像素数对应的工作频率低于所述当前工作频率；根据所述实际并行处理的像素数确定像素格式；将所述像素数据每个时钟输入的像素数转换为所述像素格式。上述技术方案通过将每个时钟输入的像素数转换为能够满足所确定的实际并行处理的像素数的格式,以降低处理像素数据的工作频率,提高集成芯片工作的稳定性。(The invention discloses a pixel data processing method and an integrated chip. The method comprises the following steps: if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency; determining a pixel format according to the actual parallel processing pixel number; and converting the number of pixels input by each clock of the pixel data into the pixel format. According to the technical scheme, the pixel number input by each clock is converted into the format capable of meeting the determined pixel number of actual parallel processing, so that the working frequency of pixel data processing is reduced, and the working stability of the integrated chip is improved.)

1. A pixel data processing method is applied to an integrated chip of a video image processing system, and is characterized by comprising the following steps:

if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency;

determining a pixel format according to the actual parallel processing pixel number;

and converting the number of pixels input by each clock of the pixel data into the pixel format.

2. The method of claim 1, further comprising:

and adjusting the actual use size of an internal storage space according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching pixel data into the internal storage space.

3. The method of claim 1, wherein determining the number of pixels actually processed in parallel comprises:

and calculating the actual parallel processing pixel number according to the mapping relation among the frame rate, the bit number of each pixel, the actual parallel processing pixel number and the working frequency, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency.

4. The method of claim 3, further comprising:

if the working frequency corresponding to the actual parallel processing pixel number still exceeds the effective working frequency range, the working frequency corresponding to the actual parallel processing pixel number is made to belong to the effective working frequency range by at least one of the following modes:

adjusting the frame rate;

adjusting the step length of the frame rate adjustment;

and adjusting the number of bits of each pixel.

5. The method of claim 4, wherein the adjusting the frame rate comprises:

and starting from the upper limit of the frame rate which can be supported by the panel, adjusting the frame rate in a descending manner according to the step length of the frame rate adjustment.

6. The method of any one of claims 1-5, further comprising: and improving the total pixel number of the panel display by at least one of the following modes:

adjusting the number of bits of each pixel;

adjusting the frame rate adjustment step length;

adjusting the frame rate;

adjusting the number of pixels actually processed in parallel;

and adjusting the practical use size of the internal storage space.

7. The method according to any of claims 1-6, further comprising, prior to said determining the number of pixels actually processed in parallel:

and adjusting the number of pixels input by each clock of the pixel data, and determining the current working frequency of the processed pixel data.

8. An integrated chip, comprising: a processor and a memory;

the memory is used for caching pixel data;

the processor is provided with:

the parallel data control module is used for determining the actual parallel processing pixel number if the current working frequency of the pixel data to be processed exceeds the effective working frequency range, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency;

the data conversion module is used for determining a pixel format according to the actual parallel processing pixel number;

and the input data control module converts the pixel number input by each clock of the pixel data into the pixel format.

9. The integrated chip of claim 8, further comprising:

and the memory state control module is used for adjusting the actual use size of the internal storage space of the memory according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching the pixel data into the internal storage space of the memory.

10. The integrated chip of claim 8, wherein the memory comprises at least one of: FIFO memory, RAM, ROM, and internal logic module.

Technical Field

The embodiment of the invention relates to the technical field of data communication, in particular to a pixel data processing method and an integrated chip.

Background

Video image processing systems are increasingly used in numerous fields such as device inspection/detection, security monitoring, industrial vision, and artificial intelligence. With the increasing of the resolution of the video image processing system, the number of channels (Lane) used on the terminal device for video display increases, and the Link Rate (LR) also increases, which makes higher and higher requirements on the stability, coordination, and the like of the hardware platform of the video image processing system.

Under the scenario of a large increase in data processing capacity, the capability of an integrated chip to process Pixel data in parallel is limited, and the increase of the bit number (BPP), the Frame Rate (FR), and the like of each Pixel can cause a large increase in the Pixel data to be processed, which is sent into an Intellectual Property (IP) core of the integrated chip, so that the operating frequency of the integrated chip is too high, the data processing performance is reduced, and the stability of the operation of the integrated chip is affected.

Disclosure of Invention

The invention provides a pixel data processing method and an integrated chip, which are used for reducing the working frequency of pixel data processing and improving the working stability of the integrated chip.

In a first aspect, an embodiment of the present invention provides a pixel data processing method, applied to an integrated chip of a video image processing system, including:

if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency;

determining a pixel format according to the actual parallel processing pixel number;

converting the number of Pixels Per Clock (PPC) of the pixel data into the pixel format.

Further, the method also comprises the following steps:

and adjusting the actual use size of the internal storage space according to the pixel number input by each clock and the actual parallel processing pixel number, and caching the pixel data into the internal storage space.

Further, the determining the number of pixels actually processed in parallel includes:

and calculating the actual parallel processing pixel number according to the frame rate, the bit number of each pixel and the mapping relation between the actual parallel processing pixel number and the working frequency, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency.

Further, the method also comprises the following steps:

if the working frequency corresponding to the actual parallel processing pixel number still exceeds the effective working frequency range, the working frequency corresponding to the actual parallel processing pixel number is made to belong to the effective working frequency range by at least one of the following modes:

adjusting the frame rate;

adjusting the step length of the frame rate adjustment;

and adjusting the number of bits of each pixel.

Further, the adjusting the frame rate includes:

and starting from the upper limit of the frame rate which can be supported by the panel, adjusting the frame rate in a descending manner according to the step length of the frame rate adjustment.

Further, the method also comprises the following steps: and improving the total pixel number of the panel display by at least one of the following modes:

adjusting the number of bits of each pixel;

adjusting the frame rate adjustment step length;

adjusting the frame rate;

adjusting the number of pixels actually processed in parallel;

and adjusting the practical use size of the internal storage space.

Further, the adjusting the frame rate includes:

and starting from the lower limit of the frame rate which can be supported by the panel, adjusting the frame rate in an incremental mode according to the step length of the frame rate adjustment.

In a second aspect, an embodiment of the present invention provides an integrated chip, including: a processor and a memory;

the memory is used for caching pixel data;

the processor is provided with:

the parallel data control module is used for determining the actual parallel processing pixel number if the current working frequency of the pixel data to be processed exceeds the effective working frequency range, so that the working frequency corresponding to the actual parallel processing pixel number is lower than the current working frequency;

the data conversion module is used for determining a pixel format according to the actual parallel processing pixel number;

and the input data control module converts the pixel number input by each clock of the pixel data into the pixel format.

Further, the method comprises the following steps:

and the memory state control module is used for adjusting the actual use size of the internal storage space of the memory according to the number of pixels input by each clock and the number of pixels actually processed in parallel, and caching the pixel data into the internal storage space of the memory.

Further, the memory includes at least one of: a First-in-First-out (FIFO) Memory, a Random Access Memory (RAM), a Read-Only Memory (ROM), and an internal logic module.

The embodiment of the invention provides a pixel data processing method and an integrated chip. The method comprises the following steps: if the current working frequency of the processed pixel data exceeds the effective working frequency range, determining the number of pixels actually processed in parallel, so that the working frequency corresponding to the number of pixels actually processed in parallel is lower than the current working frequency; determining a pixel format according to the actual parallel processing pixel number; and converting the number of pixels input by each clock of the pixel data into the pixel format. According to the technical scheme, the pixel number input by each clock is converted into the format capable of meeting the determined pixel number of actual parallel processing, so that the working frequency of pixel data processing is reduced, and the working stability of the integrated chip is improved.

Drawings

Fig. 1 is a flowchart of a pixel data processing method according to an embodiment of the present invention;

fig. 2 is a flowchart of a pixel data processing method according to a second embodiment of the present invention;

fig. 3 is a schematic diagram of a hardware structure of an integrated chip according to a third embodiment of the present invention;

fig. 4 is a schematic structural diagram of an integrated chip processor according to a third embodiment of the present invention;

fig. 5 is a schematic diagram of a pixel data processing process according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures associated with the present invention are shown in the drawings, not all of them.