阅读说明：本技术 电流基准电路、芯片及电子设备 (Current reference circuit, chip and electronic equipment ) 是由 朱志鹏 杨超 张聪 于 2021-09-06 设计创作，主要内容包括：本发明提供一种电流基准电路、芯片及电子设备,包括：电流源模块,电流镜像模块及基准电流产生模块；所述电流源模块用于产生预设的电流源；所述电流镜像模块连接所述电流源模块,基于共源共栅结构镜像所述电流源；所述基准电流产生模块连接所述电流镜像模块,基于共源共栅结构输出基准电流,所述基准电流与所述电流源具有预设比例。本发明的电流基准电路、芯片及电子设备采用共源共栅结构提高电源电压抑制比；并通过并联结构提高单路串联电阻的阻值,进而提高电流镜匹配性；大大提高基准电流的准确性。(The invention provides a current reference circuit, a chip and an electronic device, comprising: the current source module, the current mirror module and the reference current generating module; the current source module is used for generating a preset current source; the current mirror image module is connected with the current source module and mirrors the current source based on a cascode structure; the reference current generation module is connected with the current mirror module and outputs reference current based on a cascode structure, and the reference current and the current source have a preset proportion. The current reference circuit, the chip and the electronic equipment adopt a cascode structure to improve the power supply voltage rejection ratio; the resistance value of the single-circuit series resistor is improved through the parallel structure, and the matching performance of the current mirror is further improved; the accuracy of the reference current is greatly improved.)

1. A current reference circuit, characterized in that the current reference circuit comprises at least:

the current source module, the current mirror module and the reference current generating module;

the current source module is used for generating a preset current source;

the current mirror module is connected with the current source module and comprises n cascode units connected in parallel, and each cascode unit is connected in series between a power supply voltage end and the current source module and outputs a first reference voltage and a second reference voltage; each cascode unit comprises a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube; one end of the first resistor is connected with the power supply voltage end, and the other end of the first resistor is connected with the source electrode of the first PMOS tube; the grid electrode and the drain electrode of the first PMOS tube are connected with the source electrode of the second PMOS tube and output the first reference voltage; the grid electrode and the drain electrode of the second PMOS tube receive the current source and output the second reference voltage; the resistance value of the first resistor is n R, n is a natural number which is more than or equal to 1, and R is a preset resistance value;

the reference current generation module is connected with the current mirror module, receives the first reference voltage and the second reference voltage, and adjusts the current flowing through the reference current generation module based on the first reference voltage and the second reference voltage; the reference current generation module comprises a second resistor, a third PMOS tube and a fourth PMOS tube; one end of the second resistor is connected with the power supply voltage, and the other end of the second resistor is connected with the source electrode of the third PMOS tube; the grid electrode of the third PMOS tube is connected with the first reference voltage, and the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube; the grid electrode of the fourth PMOS tube is connected with the second reference voltage, and the drain electrode of the fourth PMOS tube outputs first reference current; the mirror ratio of a current mirror structure formed by the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 is 1: M, the resistance ratio of the second resistor to the first resistor is M:1, and M is a natural number which is greater than or equal to 1.

2. The current reference circuit of claim 1, wherein: the current source module comprises a power switch tube, a sampling unit and an operational amplifier; one end of the power switch tube is connected with the current mirror module, and the other end of the power switch tube is grounded through the sampling unit; the operational amplifier receives the sampling voltage output by the sampling unit and a reference voltage, amplifies the difference value of the sampling voltage and the reference voltage and outputs the amplified difference value to the control end of the power switch tube.

3. The current reference circuit of claim 2, wherein: the power switch tube is an NMOS tube.

4. A current reference circuit according to claim 2 or 3, wherein: the power switch tube works in a saturation region.

5. The current reference circuit of claim 1, wherein: the first PMOS tube works in a saturation region.

6. The current reference circuit of claim 1, wherein: the reference current generation module further comprises a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the drain electrode and the grid electrode of the first NMOS tube are connected with the drain electrode of the fourth PMOS tube, and the source electrode of the first NMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube; and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the fourth NMOS tube outputs a second reference current.

7. The current reference circuit of claim 6, wherein: the mirror ratio of a current mirror structure formed by the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube is 1: n.

8. A chip, characterized in that it comprises at least: a current reference circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that the electronic device comprises at least: a current reference circuit according to any one of claims 1 to 7.

Technical Field

The invention relates to the field of integrated circuit design, in particular to a current reference circuit, a chip and electronic equipment.

Background

With the continuous development of semiconductor technology, integrated circuits with miniaturized circuit structures are more and more common and more important in the production and life processes of people, and the integrated circuits are widely applied to the fields of signal acquisition, signal processing, signal control and the like, so that the stability and the accuracy of the integrated circuits are more and more important.

The current reference is a standard for judging the magnitude of other currents in the integrated circuit, and directly influences whether the integrated circuit can normally work and whether the accuracy meets the requirement under the condition of normal work. The existing current reference circuit generally adopts a common single-tube current mirror structure, and obtains a desired current reference by mirroring a current source with a preset proportion, but the common single-tube current mirror structure has poor power supply voltage rejection ratio and matching, and the output current reference value has a large error with a designed standard value, so that the working performance of a subsequent circuit is influenced.

Therefore, how to improve the power supply voltage rejection ratio and matching of the current reference circuit has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a current reference circuit, a chip and an electronic device.

To achieve the above and other related objects, the present invention provides a current reference circuit, comprising at least:

the current source module, the current mirror module and the reference current generating module;

the current source module is used for generating a preset current source;

the current mirror module is connected with the current source module and comprises n cascode units connected in parallel, and each cascode unit is connected in series between a power supply voltage end and the current source module and outputs a first reference voltage and a second reference voltage; each cascode unit comprises a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube; one end of the first resistor is connected with the power supply voltage end, and the other end of the first resistor is connected with the source electrode of the first PMOS tube; the grid electrode and the drain electrode of the first PMOS tube are connected with the source electrode of the second PMOS tube and output the first reference voltage; the grid electrode and the drain electrode of the second PMOS tube receive the current source and output the second reference voltage; the resistance value of the first resistor is n R, n is a natural number which is more than or equal to 1, and R is a preset resistance value;

the reference current generation module is connected with the current mirror module, receives the first reference voltage and the second reference voltage, and adjusts the current flowing through the reference current generation module based on the first reference voltage and the second reference voltage; the reference current generation module comprises a second resistor, a third PMOS tube and a fourth PMOS tube; one end of the second resistor is connected with the power supply voltage, and the other end of the second resistor is connected with the source electrode of the third PMOS tube; the grid electrode of the third PMOS tube is connected with the first reference voltage, and the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube; the grid electrode of the fourth PMOS tube is connected with the second reference voltage, and the drain electrode of the fourth PMOS tube outputs first reference current; the mirror ratio of a current mirror structure formed by the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 is 1: M, the resistance ratio of the second resistor to the first resistor is M:1, and M is a natural number which is greater than or equal to 1.

Optionally, the current source module includes a power switch tube, a sampling unit, and an operational amplifier; one end of the power switch tube is connected with the current mirror module, and the other end of the power switch tube is grounded through the sampling unit; the operational amplifier receives the sampling voltage output by the sampling unit and a reference voltage, amplifies the difference value of the sampling voltage and the reference voltage and outputs the amplified difference value to the control end of the power switch tube.

More optionally, the power switch tube is an NMOS tube.

More optionally, the power switch tube operates in a saturation region.

Optionally, the first PMOS transistor operates in a saturation region.

More optionally, the reference current generating module further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the drain electrode and the grid electrode of the first NMOS tube are connected with the drain electrode of the fourth PMOS tube, and the source electrode of the first NMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded; the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube; and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the fourth NMOS tube outputs a second reference current.

More optionally, a mirror ratio of a current mirror structure formed by the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor is 1: n.

To achieve the above and other related objects, the present invention provides a chip including at least the above current reference circuit.

To achieve the above and other related objects, the present invention provides an electronic device including at least the above current reference circuit.

As described above, the current reference circuit, the chip, and the electronic device according to the present invention have the following advantageous effects:

the current reference circuit, the chip and the electronic equipment adopt a cascode structure to improve the power supply voltage rejection ratio; the resistance value of the single-circuit series resistor is improved through the parallel structure, and the matching performance of the current mirror is further improved; the accuracy of the reference current is greatly improved.

Drawings

FIG. 1 is a schematic diagram of a current reference circuit according to the present invention.

FIG. 2 is a schematic diagram of another embodiment of the current reference circuit of the present invention.

Description of the element reference numerals

1-a current reference circuit; 11-a current source module; 111-power switching tube; 112-a sampling unit; 113-an operational amplifier; 12-a current mirror module; 121-cascode cell; 13-reference current generation module.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present embodiment provides a current reference circuit 1, the current reference circuit 1 including:

a current source module 11, a current mirror module 12 and a reference current generating module 13.

As shown in fig. 1, the current source module 11 is used for generating a preset current source.

Specifically, in this embodiment, the current source module 11 includes a power switch tube 111, a sampling unit 112, and an operational amplifier 113; as an example, the power switch tube 111 is implemented by an NMOS tube, and the sampling unit 112 is implemented by a resistor. One end (in this embodiment, the drain of the NMOS transistor) of the power switch 111 is connected to the current mirror module 12, and the other end (in this embodiment, the source of the NMOS transistor) is grounded to GND via the sampling unit 112. The operational amplifier 113 receives the sampling voltage output by the sampling unit 112 and a reference voltage VBG, amplifies a difference between the sampling voltage and the reference voltage VBG, and outputs the amplified difference to the control end (in this embodiment, the gate of the NMOS transistor) of the power switch tube 111; for example, the inverting input terminal of the operational amplifier 113 receives the sampling voltage, and the non-inverting output terminal receives the reference voltage, and in practical applications, the inverter may be added to adjust the correspondence between the polarity of the input terminal and the input signal, which is not limited to this embodiment.

Specifically, assuming that the resistance value of the resistor as the sampling unit is Ra, the preset current source satisfies: i = VBG/Ra, I being the current value of the current source. The VBG and Ra values may be set according to actual requirements, so as to ensure that the power switch tube 111 works in a saturation region, which is not described herein.

It should be noted that any structure capable of obtaining a predetermined current source is applicable to the present invention, and is not limited to this embodiment.

As shown in fig. 1, the current mirror module 12 is connected to the current source module 11, and mirrors the current source based on a cascode structure.

Specifically, the current mirror module 12 includes n cascode units 121 connected in parallel, where n is set to 1 in this embodiment. The cascode unit 121 includes a first resistor R1, a first PMOS transistor PM1, and a second PMOS transistor PM2, and the first PMOS transistor PM1 operates in a saturation region; one end of the first resistor R1 is connected with a power supply voltage VDD, and the other end of the first resistor R1 is connected with the source electrode of the first PMOS transistor PM 1; the gate and the drain of the first PMOS transistor PM1 are connected with the source of the second PMOS transistor PM2 and output the first reference voltage V1; the gate and the drain of the second PMOS transistor PM2 receive the current source and output the second reference voltage V2; the resistance value of the first resistor R1 is set to a preset value R, and the current flowing through the first resistor R1, the first PMOS transistor PM1 and the second PMOS transistor PM2 is equal to the current source.

As shown in fig. 1, the reference current generating module 13 is connected to the current mirror module 12, and outputs a reference current based on a cascode structure, where the reference current and the current source have a preset ratio.

Specifically, the reference current generating module 13 receives the first reference voltage V1 and the second reference voltage V2, and adjusts the current flowing through the reference current generating module 13 based on the first reference voltage V1 and the second reference voltage V2.

Specifically, in the present embodiment, the reference current generating module 13 includes a second resistor R2, a third PMOS transistor PM3, and a fourth PMOS transistor PM 4. One end of the second resistor R2 is connected with the power supply voltage VDD, and the other end of the second resistor R2 is connected with the source electrode of the third PMOS transistor PM 3; the gate of the third PMOS transistor PM3 is connected with the first reference voltage V1, and the drain of the third PMOS transistor PM3 is connected with the source of the fourth PMOS transistor PM 4; the gate of the fourth PMOS transistor PM4 is connected to the second reference voltage V2, and the drain thereof outputs the first reference current IP.

More specifically, as an example, if the mirror ratio of the current mirror structure formed by the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 is 1:1, the value of the first reference current IP is equal to the value I of the current source, and the resistance value of the second resistor R2 is equal to the resistance value of the first resistor R1. The mirror ratio of the current mirror structure formed by the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 is 1: M, and then the resistance ratio of the second resistor R2 to the first resistor R1 is M:1, where M is a natural number greater than or equal to 1. In practical use, the mirror ratio can be adjusted by changing the size of the device or setting a structure in which a plurality of devices are connected in parallel as required, so as to obtain a first reference current with a preset ratio, which is not repeated herein.

Specifically, as another implementation manner of the present invention, the reference current generating module 13 further includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM 4. The drain and the gate of the first NMOS transistor NM1 are connected to the drain of the fourth PMOS transistor PM4, and the source is connected to the drain and the gate of the second NMOS transistor NM 2; the source of the second NMOS transistor NM2 is grounded GND; the source of the third NMOS transistor NM3 is grounded GND, the gate is connected to the gate of the second NMOS transistor NM2, and the drain is connected to the source of the fourth NMOS transistor NM 4; the gate of the fourth NMOS transistor NM4 is connected to the gate of the first NMOS transistor NM1, and the drain outputs a second reference current IN.

More specifically, as an example, if the mirror ratio of the current mirror structure formed by the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 is 1:1, the value of the second reference current IN is equal to the value I of the current source. In practical use, the mirror ratio can be adjusted by changing the size of the device or setting a structure in which a plurality of devices are connected in parallel as required, so as to obtain a second reference current with a preset ratio, which is not repeated herein.

The current reference circuit of the embodiment forms a current mirror of a Cascode structure (Cascode structure) based on the current mirror module of the Cascode structure and the reference current generation module, so that the power supply voltage rejection ratio can be effectively improved, and the stability and accuracy of the reference current are improved.

Example two

As shown in fig. 2, the present embodiment provides a current reference circuit 1, which is different from the first embodiment in that the current mirror module 12 includes n cascode units 121 connected in parallel, each cascode unit 121 is connected in series between a power supply voltage VDD and the current source module 11, and outputs a first reference voltage and a second reference voltage; in the present embodiment, n is a natural number of 2 or more.

Specifically, the structure and the device size of each cascode unit 121 are the same, and for the specific structure, refer to the first embodiment, which is not described herein again. One end of each first resistor R1 in each cascode unit 121 is connected to the power supply voltage VDD, a drain of each second PMOS transistor is connected to the current source module 11, gates of the first PMOS transistors are connected together to output the first reference voltage V1, and gates of the second PMOS transistors are connected together to output the second reference voltage V2. The resistance of each first resistor R1 is n × R, the current flowing through each cascode unit 121 is I/n, and each first PMOS transistor operates in the saturation region. At this time, the resistance value of the second resistor R2 is n × R.

Specifically, when the mirror ratio of the current mirror structure formed by the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 is 1:1, the value of the first reference current IP is I/n; IN order to obtain a second reference current IN equal to the value I of the current source, a mirror ratio of a current mirror structure formed by the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 is 1: n; in practical use, the mirror ratio can be set as required to obtain the corresponding reference current, which is not described herein in detail.

In this embodiment, a plurality of cascode units are connected in parallel, the resistance of the first resistor in each cascode unit is increased by n times, correspondingly, the resistance of the second resistor R2 is increased by n times, and when the power voltage VDD floats (voltage jumps), due to the voltage division of the resistors (the first resistor and the second resistor), the potential jump on the source electrode of the third PMOS transistor is small, and the matching of the current mirror is greatly enhanced.

EXAMPLE III

The present embodiment provides a chip including the current reference circuit 1 according to the first embodiment or the second embodiment. The present embodiment also provides an electronic device including the current reference circuit 1 according to the first embodiment or the second embodiment. The detailed structure is not repeated herein.

According to the invention, the power supply voltage rejection ratio performance and the current matching performance of the current mirror module 12 and the reference current generation module 13 are effectively improved in a mode of a cascode structure and a series connection high-voltage resistor.

In summary, the present invention provides a current reference circuit, a chip and an electronic device, including: the current source module, the current mirror module and the reference current generating module; the current source module is used for generating a preset current source; the current mirror module is connected with the current source module and comprises n cascode units connected in parallel, and each cascode unit is connected in series between a power supply voltage end and the current source module and outputs a first reference voltage and a second reference voltage; each cascode unit comprises a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube; one end of the first resistor is connected with the power supply voltage end, and the other end of the first resistor is connected with the source electrode of the first PMOS tube; the grid electrode and the drain electrode of the first PMOS tube are connected with the source electrode of the second PMOS tube and output the first reference voltage; the grid electrode and the drain electrode of the second PMOS tube receive the current source and output the second reference voltage; the resistance value of the first resistor is n R, n is a natural number which is more than or equal to 1, and R is a preset resistance value; the reference current generation module is connected with the current mirror module, receives the first reference voltage and the second reference voltage, and adjusts the current flowing through the reference current generation module based on the first reference voltage and the second reference voltage; the reference current generation module comprises a second resistor, a third PMOS tube and a fourth PMOS tube; one end of the second resistor is connected with the power supply voltage, and the other end of the second resistor is connected with the source electrode of the third PMOS tube; the grid electrode of the third PMOS tube is connected with the first reference voltage, and the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube; the grid electrode of the fourth PMOS tube is connected with the second reference voltage, and the drain electrode of the fourth PMOS tube outputs first reference current; the mirror ratio of a current mirror structure formed by the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 is 1: M, the resistance ratio of the second resistor to the first resistor is M:1, and M is a natural number which is greater than or equal to 1. The current reference circuit, the chip and the electronic equipment adopt a cascode structure to improve the power supply voltage rejection ratio; the resistance value of the single-circuit series resistor is improved through the parallel structure, and the matching performance of the current mirror is further improved; the accuracy of the reference current is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.