阅读说明：本技术 用于闪存的写入管理机制 (Write management mechanism for flash memory ) 是由 杜建东 萧佳容 杨宗杰 于 2019-05-20 设计创作，主要内容包括：本发明公开了一种管理闪存模块的方法,该闪存模块包括多个区块,该多个区块中的一部分属于一备用池。该方法包括：在该备用池中预留至少一已抹除区块以利一写入操作的进行；监测该至少一已抹除区块的一已抹除时间；以及当该已抹除时间超过一临界值时,执行一替换操作以替换该至少一已抹除区块。本发明通过对于备用池的妥善管理,在有效地减少写入延迟的(通过在备用池中预留至少一个已抹除区块)同时,又避免潜在的存储器单元的物理性伤害(通过限制区块停留在已抹除状态的时间)。同时,本发明管理机制也进一步与垃圾数据回收操作结合,从而更合理地进行对已抹除区块的写入与替换。(The invention discloses a method for managing a flash memory module, wherein the flash memory module comprises a plurality of blocks, and one part of the blocks belongs to a spare pool. The method comprises the following steps: reserving at least one erased block in the spare pool to facilitate the proceeding of a write operation; monitoring an erased time of the at least one erased block; and when the erased time exceeds a threshold value, executing a replacement operation to replace the at least one erased block. The present invention effectively reduces write latency (by reserving at least one erased block in the spare pool) while avoiding potential physical damage to the memory cells (by limiting the time that the block stays in an erased state) through proper management of the spare pool. Meanwhile, the management mechanism of the invention is further combined with garbage data recovery operation, thereby more reasonably writing and replacing the erased blocks.)

1. A method of managing a flash memory module, the flash memory module including a plurality of blocks, a portion of the plurality of blocks belonging to a spare pool, the method comprising:

reserving at least one erased block in the spare pool to facilitate the proceeding of a write operation;

monitoring an erased time of the at least one erased block; and

when the erased time exceeds a threshold value, a replacement operation is performed to replace the at least one erased block.

2. The method of claim 1, wherein the spare pool comprises the at least one erased block and at least one written block.

3. The method of claim 1, wherein the step of monitoring the erase time of the at least one erased block comprises:

establishing a time stamp associated with the at least one erased block; and

and comparing the time information in the time stamp with the critical value regularly.

4. The method of claim 1, wherein the step of performing the replacement operation comprises:

and writing the at least one erased block.

5. The method of claim 4, wherein writing the at least one erased block comprises:

performing a garbage data recovery operation on a plurality of blocks in the flash memory module; and

and writing the at least one erased block by using the recovery data output by the garbage data recovery operation.

6. The method of claim 1, wherein the step of performing the replacement operation comprises:

selecting a first block from at least one written block in the spare pool, and performing an erasing operation on the first block; and

and replacing the at least one erased block with the first block, wherein the erased block has the erased time exceeding the threshold.

7. The method of claim 1, further comprising:

when an access command from a host is not received, the specific data is automatically read from the flash memory module and written back to the flash memory module.

8. A controller for managing a flash memory module, wherein the flash memory module includes a plurality of blocks, and a portion of the plurality of blocks belongs to a spare pool, the controller comprising:

a storage unit for storing a program code; and

a processing unit, coupled to the storage unit, for reading the program code from the storage unit to execute the program code, thereby performing the following operations:

reserving at least one erased block in the spare pool to facilitate the proceeding of a write operation;

monitoring an erased time of the at least one erased block; and

when the erased time exceeds a threshold value, a replacement operation is performed to replace the at least one erased block.

9. The controller according to claim 8, wherein the processing unit executes the program code to establish a time stamp associated with the at least one erased block; and comparing the time information in the time stamp with the critical value regularly.

10. The controller as recited in claim 8, wherein said processing unit executes said program code to write to said at least one erased block to perform said replacement operation.

11. The controller as recited in claim 10 wherein the processing unit executes the program code to perform a garbage collection operation on a plurality of blocks in the flash memory module; and writing the at least one erased block by utilizing the recovery data output by the garbage data recovery operation to execute the replacement operation.

12. The controller of claim 8, wherein the processing unit executes the program code to select at least a first block from the spare pool and perform an erase operation on the at least a first block; and replacing the at least one erased block with the at least one first block, the erased block having the erased time exceeding the threshold.

13. The controller as claimed in claim 8, wherein the controller is controlled by a host, and the processing unit executes the program code to automatically read specific data from the flash memory module and write back the specific data to the flash memory module when an access command issued by the host is not received.

14. A storage device, comprising:

the flash memory module comprises a plurality of blocks, and one part of the blocks belongs to a spare pool; and

a controller for accessing a flash memory module, comprising:

a storage unit for storing a program code; and

a processing unit, coupled to the storage unit, for reading the program code from the storage unit to execute the program code, thereby performing the following operations:

reserving at least one erased block in the spare pool to facilitate the proceeding of a write operation;

monitoring an erased time of the at least one erased block; and

when the erased time exceeds a threshold value, a replacement operation is performed to replace the at least one erased block.

15. The memory device of claim 14, wherein the spare pool comprises the at least one erased block and at least one written block.

16. The memory device of claim 14, wherein the controller is configured to establish a time stamp associated with the at least one erased block; and comparing the time information in the time stamp with the critical value regularly.

17. The memory device of claim 14, wherein the controller is configured to write to the at least one erased block when the erased time exceeds the threshold.

18. The memory device of claim 17, wherein the controller performs a garbage collection operation on the plurality of blocks in the flash memory module when the erased time exceeds the threshold; and writing the at least one erased block by using the recovery data output by the garbage data recovery operation.

19. The memory device according to claim 14, wherein the controller selects at least one first block from the spare pool and performs an erase operation on the at least one first block when the erased time exceeds the threshold; and replacing the at least one erased block with the at least one first block, the erased block having the erased time exceeding the threshold.

20. The memory device as claimed in claim 14, wherein the controller is controlled by a host, and the controller automatically reads specific data from the flash memory module and writes the specific data back to the flash memory module when the controller does not receive an access command issued by the host.

Technical Field

The present invention relates to a flash memory, and more particularly, to a method, a controller and a related memory device for managing a block to be written in the flash memory.

Background

Generally, for a write command issued by a host, a flash memory controller searches an idle erased block from a flash memory to write data into the erased block. However, if the flash memory cell is in an erased state for a long time, unrecoverable physical damage may be caused to the cell. Therefore, it is necessary to provide a write management mechanism to prevent such a problem.

Disclosure of Invention

In view of the above, an objective of the present invention is to disclose a write management mechanism for a flash memory. In the invention, a part of the blocks of the flash memory is divided to be used as spare pools (spare pools). The controller will find out the block from the spare pool to write data, so as to complete the write command issued by the host. Wherein, only a small number of erased blocks (erased blocks) are reserved in the spare pool, and the rest are written blocks (programmed blocks). When the controller receives a write command from the host, the controller will find the reserved erased blocks from the spare pool to write data. After the writing is completed, the controller will search one or more written blocks from the spare pool and perform an erasing operation to serve as a new reserved block. Thus, the number of erased blocks in the blocks of the flash memory can be reduced.

Drawings

FIG. 1 is a block diagram illustrating an architecture of a related memory device, a controller and a flash memory module according to an embodiment of the invention.

FIG. 2 illustrates an association between a flash module and a spare pool.

FIG. 3 is a flowchart illustrating a method for block write management of a flash memory according to an embodiment of the present invention.

FIG. 4 shows the association between the master command and the memory operation command according to the embodiment of the present invention.

Wherein the reference numerals are as follows:

100 storage device

120 controller

122 processing unit

124 memory cell

130 flash memory module

130_1 ~ 130_ N flash memory chip

138 preparation pool

DB _0 DBK, SB _0 SBQ Block

210 to 250 steps

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention to the reader. However, it will be apparent to one skilled in the art how to implement the invention without one or more of the specific details, or with other methods or components, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Moreover, any examples or illustrations presented herein are not intended to be limited or defined by any of the words used therein. Rather, these examples or illustrations should be considered in descriptive sense only and with respect to one particular embodiment. It will be appreciated by those skilled in the art that any words used in these examples or illustrations will encompass other embodiments given elsewhere in this specification. Where words used to indicate such non-limiting examples include, but are not limited to: "for example," such as, "" for example, "" in one embodiment, "and" in an example.

The flowcharts and blocks in the flowcharts within this specification illustrate the architecture, functionality, and operation of what may be implemented by systems, methods and computer software products according to various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagrams may represent a module, segment, or portion of program code, which comprises one or more executable instructions for implementing the specified logical function(s). In addition, each block of the functional block diagrams and/or flowchart illustrations, and combinations of blocks, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer program instructions. These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium implement the function/act specified in the flowchart and/or block diagram block or blocks.

FIG. 1 is a schematic diagram of an embodiment of the present invention. As shown in fig. 1, the memory device 100 includes a controller 120 and a flash memory module 130, and is controlled by a host (host device)200 (the memory device 100 may even be a part of the host 200). The host 200 may include at least one central processing unit (not shown), and controls the operation of the host 200 by operating an operating system and an application program, and is linked with a peripheral device (not shown). The memory device 100 may be used to provide memory space for the host 200 to store program codes and data necessary for operating the operating system and various applications. Examples of the master device 50 may include: a multifunctional mobile phone (tablet), a wearable device (wearable), and a personal computer (personal computer) such as a desktop computer or a notebook computer. Examples of storage device 100 may include (but are not limited to): solid State Drives (SSDs) and various embedded storage devices (e.g., embedded storage devices conforming to the UFS or EMMC specifications).

The controller 120 may be used to access (access) the flash memory module 130. In one embodiment, the Flash memory module 130 may be a stereo NAND type Flash memory (3D NAND-type Flash) and may include at least one Flash memory chip (Flash memory), but this is not a limitation of the present invention. Each flash memory chip comprises a plurality of blocks (blocks), and the data erasing operation of the flash memory module 130 by the controller 120 is performed in units of blocks. In addition, one block can record a specific number of pages (pages), and the data writing operation of the controller 120 to the flash memory module 130 is performed in units of pages.

The controller 120 may include processing circuitry such as a microprocessor 122, and a storage unit 124 such as a Read Only Memory (ROM), wherein the ROM 124 is used for storing program codes and specific data, and the microprocessor 122 is used for executing the program codes to control access to the flash Memory module 130. In addition, the controller 120 may include other interface logic, control logic, or buffer memory, etc. to facilitate various operations described below. However, for the sake of brevity of the description, it is omitted here. Those skilled in the art will understand how to implement the various operations and related applications described in connection with the disclosed circuits and circuit components, after reading the following description.

In this embodiment, the host 200 may indirectly access the memory device 100 by transmitting a host command (host command) and a corresponding logical address to the controller 120. The controller 120 receives a master command (read or write command) and a logical address, translates the master command into a memory operation command, and controls the flash memory module 130 to read, write (program), or erase (erase) a memory unit (memory) or a data page (page), or a block (block) at a specific physical address in the flash memory module 130 according to the memory operation command. Further, the controller 120 executes the program codes and/or references data in the memory unit 124 to perform a series of operations to achieve specific operations to be mentioned below.

As shown in FIG. 2, the flash memory module 130 includes a plurality of blocks, which may be distributed on the flash memory chips 130_ 1-130 _ N. Furthermore, the blocks in the flash memory module 130 can be divided into spare pools (spare pools) 138. Blocks SB 0-SBQ may be included in the spare pool 138, and these blocks may have no data stored therein, or may have invalid data (data that has been stored in other blocks and is no longer updated). In the present invention, all write commands issued by the host 200 are written (data is written) by selecting one or more blocks from the spare pool 138 by the controller 120 according to the data included in the write commands issued by the host 200

Into one or more pages of data of a block). When one or more blocks are written with data by a write command from the host 200, the blocks are moved out of the spare pool 138, and the controller 120 selects one or more blocks, which only store invalid data, from among the blocks DB 0-DBK outside the spare pool 138 to supplement the spare pool 138.

In the present invention, the controller 120 reserves at least one erased block (e.g., block SB _0) in the spare pool 138, which is already in an erased state, because the erase operation of the block takes a considerable amount of time, and the pre-erase operation can reduce the delay of the write operation. When the host 200 issues a write command to the controller 120, the controller 120 writes data transmitted from the host to the erased block SB _0 reserved in the spare pool 138, and before the host 200 issues a next write command to the controller 120, the controller 120 searches for at least one block (e.g., block SB _3) from the written (programmed) blocks SB _1 to SB _ Q in the spare pool 138 and erases the block and reserves the block for a next write operation.

However, as mentioned previously, if the block is in the erased state for too long, irreversible physical damage may be caused to the cells therein. Therefore, the invention can manage the erased blocks in the preparation pool, and write the erased blocks into data after a certain time, thereby avoiding possible damage. Referring to the flowchart shown in fig. 3, fig. 3 shows a process of the method of the present invention, which at least includes the following steps:

step 210: reserving at least one erased block

Step 220: establishing a time stamp of the at least one erased block

Step 230: determining whether the erased time of the at least one erased block exceeds a threshold

Step 240: writing the at least one erased block

Step 250: at least one written block is selected to replace the erased block.

In step 210, the controller 120 performs an erase operation on at least one written block in the preparation pool 138 to convert the at least one written block (e.g., SB _7) from a written state (programmed state) to an erased state in preparation for a possible write operation. Step 210 may occur before the host 200 issues a write command or after the controller 120 writes another erased block. In step 220, the controller 120 establishes a time stamp of the at least one erased block. In step 230, the controller 120 determines whether an erased time of the at least one erased block in the erased state exceeds a threshold according to the time information in the timestamp and the system time, which is used to protect the erased block from unrecoverable physical damage. If the determination result in the step 230 is yes, go to the step 230; if not, the step is continued to be stopped. In step 240, since the controller 120 has found that the erased time of the at least one erased block has exceeded the threshold, it represents that the erased block is at risk of damage. Therefore, the controller 120 writes the at least one erased block from an erased state to a written state to avoid damage.

Furthermore, in one embodiment, the controller 120 may utilize the opportunity to write erased blocks while performing a garbage collection (garbage collection) operation. The controller 120 writes the data collected from the valid pages of the blocks DB 0-DBK into the at least one erased block, thereby converting the at least one erased block into a written block. Thereafter, the process proceeds to step 250, where the controller 120 searches the spare pool 138 for at least one written block (e.g., SB _4) to replace the at least one erased block, and returns to step 210 to perform an erase operation on the at least one written block in preparation for a subsequent write command.

From the above, the present invention effectively protects the memory cells in the flash memory module 130 from damage due to too long time spent in the erased state. On the other hand, since the erased blocks are reserved in the spare pool at any time, the data writing delay can be shortened (i.e., the time for waiting for erasing the written blocks is not needed).

In addition, a feature of the present invention is the control behavior of the controller 120 with respect to the flash memory module 130. Referring to fig. 4, when the host 200 issues a main control command (read or write) to the controller 120, the controller 120 converts the access type, address and related data included in the main control command into a corresponding memory operation command, and accesses the flash memory chips 130_1 to 130_ N in the flash memory module 130.

Since the management of the erased blocks in the present invention is independent of the host command of the host 200, and is performed according to the time stamp of the erased blocks. Therefore, even if the host 200 does not issue the host command to the controller 120, an event may occur that the time stamp of the erased blocks in the spare pool 138 exceeds the threshold value, which may cause the replacement operation of the erased blocks and trigger the garbage data recycling operation. Therefore, in one embodiment, the controller 120 may issue the following sequential command sequences to the flash memory chips 130_ 1-130 _ N when it does not receive any access command from the host 200:

reading: 00h ALE 30h

Writing: 80h ALE 10h

Erasing: 60h ALE D0h

First, if the timestamp of an erased block exceeds the time limit, the process will be triggered to write to the erased block in step 240. As described above, writing to erased blocks may trigger garbage collection operations at the same time. Therefore, the first read command in the command sequence performs a garbage collection operation to read data from the valid pages in the blocks DB0 to DBK outside the spare pool 138. The read data is sent to the controller 120 for error correction (error correction). Then, the processed data is written into the erased block, i.e. the second write command in the command sequence. Finally, step 250 of the process is entered to select another block from the spare pool to erase in place of the erased block, i.e. the third erase command in the command sequence. As can be further seen from the timing diagram below in FIG. 4, the master command may cause the controller 120 to generate the relevant memory operation command, but the controller 120 may still periodically generate the autonomous memory operation command. Therefore, a feature of the present invention is that even when the host 200 does not issue an access command to the controller 120, the controller 120 may autonomously issue to the flash memory module 130: a sequence of sequential commands of read, write, erase.

In summary, the present invention effectively reduces the write latency (by reserving at least one erased block in the spare pool) while avoiding potential physical damage to the memory cells (by limiting the time that the block stays in the erased state) by properly managing the spare pool. Meanwhile, the management mechanism of the invention is further combined with garbage data recovery operation, thereby more reasonably writing and replacing the erased blocks.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.