阅读说明：本技术 一种多路并行数据采样系统及方法 (Multi-channel parallel data sampling system and method ) 是由 丁亮 于 2020-06-30 设计创作，主要内容包括：本发明公开了一种多路并行数据采样系统,包括多路数据并行输入和处理单元,处理单元包括级联的1级处理单元、2级处理单元、……、Y级处理单元,其中,Y≥2且Y为正整数；每级处理单元中包括由多个缓存和数据引擎组成的单元,数据引擎包括MUX和仲裁器,仲裁器监视缓存的数据状态,当一个缓存满足数据读取条件时,仲裁器控制MUX选通该缓存,读取数据并将多个缓存的多路输出聚合为一路数据输出,数据引擎的带宽≥多路输入数据的带宽之和。还公开了一种多路并行采样方法,本发明使多路数据的采集在一颗芯片上实现,实现几十路甚至几百路的并行数据采样。无论在FPGA还是ASIC设计中,都能够产生时序良好的电路结构。(The invention discloses a multi-path parallel data sampling system, which comprises a multi-path data parallel input and processing unit, wherein the processing unit comprises a 1-stage processing unit, a 2-stage processing unit, … … and a Y-stage processing unit which are cascaded, wherein Y is more than or equal to 2 and is a positive integer; each stage of processing unit comprises a unit consisting of a plurality of caches and a data engine, the data engine comprises a MUX and an arbiter, the arbiter monitors the data state of the caches, when one cache meets the data reading condition, the arbiter controls the MUX to gate the cache, the data is read, the multiplexed outputs of the caches are aggregated into one-path data output, and the bandwidth of the data engine is larger than or equal to the sum of the bandwidths of the multiplexed input data. The invention realizes the acquisition of multi-channel data on one chip and realizes the sampling of dozens of or even hundreds of channels of parallel data. Both in FPGA and ASIC designs, a circuit structure with good timing can be produced.)

1. A multi-path parallel data sampling system is characterized by comprising a multi-path data parallel input and processing unit, wherein the processing unit comprises a 1-level processing unit, a 2-level processing unit, … … and a Y-level processing unit which are cascaded, Y is more than or equal to 2, Y is a positive integer, the unit comprises a plurality of buffers and a data engine for reading the buffers, each buffer is used for writing one-path input data, the data engine comprises a MUX and an arbiter, the arbiter monitors the data state of the buffers, when one buffer meets a data reading condition, the arbiter controls the MUX to gate the buffers, the data is read, the multi-path outputs of the plurality of buffers are aggregated into one-path data output, and the bandwidth of the data engine is more than or equal to the sum of the bandwidths of the input data in the plurality of buffers.

2. The system according to claim 1, wherein the bandwidth of the data engine is set by: setting the data bit width of the data engine to be the same as the bit width of the input data, and setting the clock frequency of the MUX and the arbiter to be more than or equal to L multiplied by the clock frequency of the input data, wherein L represents the path number of the input data.

3. The system according to claim 1, wherein the bandwidth of the data engine is set by: the frequency of the data engine is set to be the same as the clock frequency of the input data, and the bit width of the data engine is set to be more than or equal to L multiplied by the bit width of the input data, wherein L represents the path number of the input data.

4. A method for multi-way parallel data sampling, comprising:

step S100: inputting multiple paths of input data into a 1-stage processing unit respectively;

step S200: the input data are respectively written into a plurality of caches, the data engine monitors the state of the caches, and when one cache meets the data reading condition, the arbiter controls the MUX to gate the cache and read the cached data;

step S300: the data engine aggregates the read data of the plurality of caches into a path of data to be output;

step S400: step S200 is sequentially executed from the level 2 processing unit to the level Y processing unit, and finally the level Y processing unit outputs the integrated data in one path, where the following conditions are satisfied: y is more than or equal to 2 and is a positive integer, the bandwidth of the data engine of the processing unit at the Y level is more than or equal to P (Y-1) the bandwidth of the data engine of the processing unit at the P level, wherein P is the cache number of the processing unit at the (Y-1) level.

Technical Field

The invention relates to the technical field of electronic measurement, in particular to a multi-channel parallel data sampling system and a multi-channel parallel data sampling method.

Background

In signal processing and data sampling systems, multiple signal data streams need to be transmitted simultaneously to facilitate signal analysis. The existing common method is as follows: firstly, a Multiplexer (MUX) is made on the FPGA, and with the improvement of data bit width, clock frequency and data path number, the method has many defects on functions and FPGA layout and wiring: firstly, functionally, the data MUX is a time division multiplexing circuit, and only one path of data can be allowed to pass through at any time, so that the synchronism of multi-path data sampling cannot be ensured, and the requirement cannot be met on occasions with very high data synchronization accuracy; moreover, if the bit width of the signal data is large or the clock frequency is high, the combinatorial logic scale of the MUX circuit is greatly affected, which results in poor circuit timing performance. According to design experience, if the multi-path data is more than 30 paths, the FPGA design using the MUX method becomes very difficult to place and route, and the FPGA tool can not complete the placement and routing seriously. The same problem can exist in ASIC designs. Second, the multichannel data splices into data all the way, and the shortcoming of doing so is that all multichannel data need be transmitted at any time, is a waste to sampling transmission bandwidth resource, and the data is formed according to the clock beat concatenation, and the sampling data needs further split processing, just can be used by the analysis, and system flow design changes loaded down with trivial details.

Disclosure of Invention

The invention aims to provide a multi-channel parallel data sampling system and a multi-channel parallel data sampling method, which are used for solving the problem that the synchronism and the time sequence cannot be met in the method for simultaneously transmitting multi-channel signal data in the prior art.

The invention solves the problems through the following technical scheme:

a multi-path parallel data sampling system comprises a multi-path data parallel input and processing unit, wherein the processing unit comprises a 1-level processing unit, a 2-level processing unit, … … and a Y-level processing unit which are cascaded, wherein Y is more than or equal to 2, and Y is a positive integer, the unit comprises a plurality of caches and a data engine for reading the caches, each cache is used for writing one-path input data, the data engine comprises a MUX and an arbiter, the arbiter monitors the data state of the caches, when one cache meets a data reading condition, the arbiter controls the MUX to gate the cache, the data is read, the multi-path outputs of the caches are aggregated into one-path data output, and the bandwidth of the data engine is more than or equal to the sum of the bandwidths of the input data in the caches.

Each stage processing unit processes the parallel input data into a path of data with higher bandwidth, and the data is finally converted into a path of data signal with high bandwidth through the multi-stage processing unit, and the multi-path data is transmitted in a time division multiplexing mode. In order to ensure that the cache cannot be written to be full, overflow and lose data, the bandwidth of the data engine is equal to or larger than the sum of the bandwidths of the multiple paths of input data, and the data engine reads data from the cache at a high speed enough to ensure that the cache cannot be written to be full and overflow. The invention realizes the acquisition of multi-channel data on one chip and realizes the parallel data sampling of dozens of channels or even hundreds of channels. The synchronous acquisition of multi-path data can achieve the synchronous precision of clock beats, and a circuit structure with good time sequence can be generated no matter in FPGA or ASIC design.

The bandwidth setting method of the data engine comprises the following steps: setting the data bit width of the data engine to be the same as the bit width of the input data, and setting the clock frequency of the MUX and the arbiter to be more than or equal to L multiplied by the clock frequency of the input data, wherein L represents the path number of the input data.

The bandwidth setting method of the data engine comprises the following steps: the frequency of the data engine is set to be the same as the clock frequency of the input data, and the bit width of the data engine is set to be more than or equal to L multiplied by the bit width of the input data, wherein L represents the path number of the input data.

A method of multi-way parallel data sampling comprising:

step S100: inputting multiple paths of input data into a 1-stage processing unit respectively;

step S200: the input data are respectively written into a plurality of caches, the data engine monitors the state of the caches, and when one cache meets the data reading condition, the arbiter controls the MUX to gate the cache and read the cached data;

step S300: the data engine aggregates the read data of the plurality of caches into a path of data to be output;

step S400: step S200 is sequentially executed from the level 2 processing unit to the level Y processing unit, and finally the level Y processing unit outputs the integrated data in one path, where the following conditions are satisfied: y is more than or equal to 2 and is a positive integer, the bandwidth of the data engine of the processing unit at the Y level is more than or equal to P (Y-1) the bandwidth of the data engine of the processing unit at the P level, wherein P is the cache number of the processing unit at the (Y-1) level.

Compared with the prior art, the invention has the following advantages and beneficial effects:

(1) the invention realizes the acquisition of multi-channel data on one chip and realizes the parallel data sampling of dozens of channels or even hundreds of channels. Both in FPGA and ASIC designs, a circuit structure with good timing can be produced. Therefore, the design of a time sequence larger-scale acquisition system in the FPGA at a lower end can be realized, and the design cost is reduced.

(2) Each level unit in the multilevel structure can adjust the clock or bit width according to the requirement of the engine bandwidth; if the clock frequency is a design difficulty, the clock frequency can be reduced, and the bit width can be increased; if the logic resource is a design difficulty, the clock frequency can be improved, and the bit width can be reduced. I.e., using adjusted clocks or logic resources to balance the timing and resource difficulties of a circuit design.

(3) The synchronous acquisition of the multi-path data can achieve the synchronous precision of clock beats; and the data are collected in parallel and multiple paths, and the data do not need an additional separation and analysis step.

Drawings

FIG. 1 is a block diagram of the system of the present invention.

Detailed Description

The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.