Latch alarm circuit and electronic equipment
阅读说明：本技术 一种锁存报警电路及电子设备 (Latch alarm circuit and electronic equipment ) 是由 张重阳 于 2020-06-30 设计创作，主要内容包括：本申请涉及一种锁存报警电路及电子设备,属于电子电路技术领域。该锁存报警电路应用于包括由主电源供电的处理器和由辅助电源供电的监控器的电子设备。该锁存报警电路包括至少一路基本电路,每路基本电路均包括RS触发器、同或门电路。RS触发器的第一输入端用于接入主电源按键信号,其输出端用于连接监控器并与第一下拉电阻连接。同或门电路的第一输入端用于接入处理器输入的报警信号,并与上拉电阻连接,其第二输入端用于接入处理器输入的系统状态指示信号,并与第二下拉电阻连接,输出端与RS触发器的第二输入端连接。通过利用RS触发器构成具备一级锁存功能的报警电路来实现对异常状态的锁存,以解决目前异常信息易丢失的问题。(The application relates to a latch alarm circuit and electronic equipment, and belongs to the technical field of electronic circuits. The latch alarm circuit is applied to an electronic device including a processor powered by a main power supply and a monitor powered by an auxiliary power supply. The latch alarm circuit comprises at least one path of basic circuit, and each path of basic circuit comprises an RS trigger and an exclusive-nor circuit. The first input end of the RS trigger is used for accessing a main power supply key signal, and the output end of the RS trigger is used for connecting the monitor and the first pull-down resistor. The first input end of the exclusive-OR circuit is used for accessing an alarm signal input by the processor and is connected with the pull-up resistor, the second input end of the exclusive-OR circuit is used for accessing a system state indicating signal input by the processor and is connected with the second pull-down resistor, and the output end of the exclusive-OR circuit is connected with the second input end of the RS trigger. The alarm circuit with the primary latch function is formed by the RS trigger to latch the abnormal state, so that the problem that the abnormal information is easy to lose at present is solved.)
1. A latch alarm circuit, applied to an electronic device, the electronic device comprising: the system comprises a processor powered by a main power supply and a monitor powered by an auxiliary power supply, wherein the monitor normally works in a state that the system is shut down or the main power supply is closed; the latch alarm circuit includes: at least one basic circuit, each of the basic circuits comprising:
the first input end of the RS trigger is used for accessing a main power supply key signal, the output end of the RS trigger is connected with a first pull-down resistor, and the output end of the RS trigger is used for connecting the monitor;
the first input end of the exclusive OR circuit is connected with the pull-up resistor, the first input end of the exclusive OR circuit is used for accessing the alarm signal input by the processor, the second input end of the exclusive OR circuit is connected with the second pull-down resistor, the second input end of the exclusive OR circuit is used for accessing the system state indication signal input by the processor, and the output end of the exclusive OR circuit is connected with the second input end of the RS trigger.
2. The latch alarm circuit according to claim 1, wherein the number of the basic circuits is multiple, the processor connected to each basic circuit is the same, and the input alarm signal is different.
3. The latch alarm circuit according to claim 1, wherein the number of the basic circuits is multiple, each of the basic circuits corresponds to one of the processors, and the processors corresponding to different basic circuits are different.
4. The latch alarm circuit according to claim 2 or 3, wherein a plurality of the exclusive-nor gates are integrated in the same chip.
5. The latch alarm circuit according to claim 2 or 3, wherein a plurality of the RS flip-flops are integrated in the same chip.
6. An electronic device, comprising:
a processor powered by a main power source;
the monitor is powered by an auxiliary power supply, and the monitor normally works in a state that a system is shut down or the main power supply is closed;
the latch alarm circuit comprises at least one path of basic circuit, and each path of basic circuit comprises: an RS trigger and an exclusive-nor circuit; the first input end of the RS trigger is used for inputting a main power supply key signal, the second input end of the RS trigger is connected with the output end of the exclusive-nor circuit, the output end of the RS trigger is connected with the monitor, and the output end of the RS trigger is also connected with a first pull-down resistor;
the first input end of the exclusive OR circuit is connected with the processor and used for receiving the alarm signal output by the processor, the first input end of the exclusive OR circuit is further connected with a second pull-up resistor, the second input end of the exclusive OR circuit is connected with the processor and used for receiving the system state indication signal output by the processor, and the second input end of the exclusive OR circuit is further connected with a pull-down resistor.
7. The electronic device of claim 6, wherein the number of the basic circuits is multiple, the processor connected to each basic circuit is the same, and the input alarm signal is different.
8. The electronic device of claim 6, wherein the number of the basic circuits is multiple, each of the basic circuits corresponds to one of the processors, and the processors corresponding to different basic circuits are different.
9. The electronic device of claim 7 or 8, wherein multiple exclusive-nor gates are integrated in the same chip.
10. The electronic device of claim 7 or 8, wherein the plurality of RS flip-flops are integrated in the same chip.
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a latch alarm circuit and electronic equipment.
Background
In the process of high-speed development of the information industry, electronic devices of different platforms and different manufacturers reserve special alarm signals with similar functions to output abnormal states of a Central Processing Unit (CPU) to a Baseboard Management Controller (BMC), such as an overheat signal (thermal signal), a major error signal (capacitor signal), a memory event signal (MemEvent signal, issued by a memory), and the like. The BMC is used as a control unit of a mainboard of the electronic equipment, is powered by an auxiliary power supply, normally works in a main power state when the system is started or shut down, is used as a monitor of the CPU, is responsible for monitoring various alarm signals output by the CPU and performs a series of control actions.
When the alarm signals are triggered, the mainboard is powered off, the system is shut down, so that the CPU or the system is protected from being seriously damaged, the BMC serving as the mainboard state monitor can detect the abnormal condition, but after the system is powered off or the abnormal condition is relieved, the alarm signals can be reset, the signal state monitored by the BMC can be restored to a normal value, and thus an engineer cannot often locate the problem.
Disclosure of Invention
In view of this, an object of the present application is to provide a latch alarm circuit and an electronic device, so as to solve the problems that the abnormal information is easily lost and the alarm reason is not easy to be located in the conventional alarm mechanism.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a latch alarm circuit, which is applied to an electronic device, where the electronic device includes: the system comprises a processor powered by a main power supply and a monitor powered by an auxiliary power supply, wherein the monitor normally works in a state that the system is shut down or the main power supply is closed; the latch alarm circuit includes: at least one basic circuit, each of the basic circuits comprising: an RS trigger and an exclusive-nor circuit; the first input end of the RS trigger is used for accessing a main power supply key signal, the output end of the RS trigger is connected with a first pull-down resistor, and the output end of the RS trigger is used for connecting the monitor; the first input end of the exclusive OR circuit is connected with the pull-up resistor, the first input end of the exclusive OR circuit is used for accessing the alarm signal input by the processor, the second input end of the exclusive OR circuit is connected with the second pull-down resistor, the second input end of the exclusive OR circuit is used for accessing the system state indication signal input by the processor, and the output end of the exclusive OR circuit is connected with the second input end of the RS trigger. In the embodiment of the application, the alarm signal input by the processor and the system state indication signal are subjected to exclusive OR logic operation by using an exclusive OR gate circuit and then output to the RS trigger, and the alarm circuit with a primary latch function is formed by using the RS trigger to latch the abnormal state, so that the problems that the current abnormal information is easy to lose and the alarm reason is not easy to locate are solved.
With reference to a possible implementation manner of the embodiment of the first aspect, the number of the basic circuits is multiple, the processors connected to each basic circuit are the same, and the input alarm signals are different. In the embodiment of the application, the multi-channel basic circuit is utilized to respectively carry out primary latching on different alarm signals of the same processor, so that a plurality of different alarm states can be monitored simultaneously, and the applicability and the practicability of the scheme are enhanced.
With reference to one possible implementation manner of the embodiment of the first aspect, the number of the basic circuits is multiple, each basic circuit corresponds to one processor, and the processors corresponding to different basic circuits are different. In the embodiment of the application, the alarm signals of different processors are respectively latched in one level by utilizing the multi-path basic circuit, so that the abnormal state output by the processors can be monitored simultaneously, and the applicability and the practicability of the scheme are enhanced.
With reference to one possible implementation manner of the embodiment of the first aspect, multiple paths of the exclusive-nor gate circuits are integrated in the same chip. In the embodiment of the application, multiple same-OR gates are integrated in the same chip so as to simplify the circuit and reduce the risk of faults.
With reference to one possible implementation manner of the embodiment of the first aspect, a plurality of RS flip-flops are integrated in the same chip. In the embodiment of the application, a plurality of RS triggers are integrated in the same chip, so that the circuit is simplified, and the risk of faults is reduced.
In a second aspect, an embodiment of the present application further provides an electronic device, including: the system comprises a processor, a monitor and a latch alarm circuit; the processor is powered by a main power supply; the monitor is powered by an auxiliary power supply, and the monitor normally works in a state that a system is shut down or the main power supply is closed; the latch alarm circuit comprises at least one path of basic circuit, and each path of basic circuit comprises: an RS trigger and an exclusive-nor circuit; the first input end of the RS trigger is used for inputting a main power supply key signal, the second input end of the RS trigger is connected with the output end of the exclusive-nor circuit, the output end of the RS trigger is connected with the monitor, and the output end of the RS trigger is also connected with a first pull-down resistor;
the first input end of the exclusive OR circuit is connected with the processor and used for receiving the alarm signal output by the processor, the first input end of the exclusive OR circuit is further connected with a second pull-up resistor, the second input end of the exclusive OR circuit is connected with the processor and used for receiving the system state indication signal output by the processor, and the second input end of the exclusive OR circuit is further connected with a pull-down resistor.
With reference to a possible implementation manner of the embodiment of the second aspect, the number of the basic circuits is multiple, the processors connected to each basic circuit are the same, and the input alarm signals are different.
With reference to a possible implementation manner of the embodiment of the second aspect, the number of the basic circuits is multiple, each basic circuit corresponds to one of the processors, and the processors corresponding to different basic circuits are different.
In combination with a possible implementation manner of the embodiment of the second aspect, the plurality of exclusive-nor gates are integrated in the same chip.
With reference to one possible implementation manner of the embodiment of the second aspect, a plurality of RS flip-flops are integrated in the same chip.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Fig. 2 shows a schematic structural diagram of a basic circuit provided in an embodiment of the present application.
Fig. 3 shows a logic diagram of an RS flip-flop according to an embodiment of the present application.
Fig. 4 shows a circuit schematic diagram of a latch alarm circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it is noted that the terms "first", "second", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In view of the fact that the alarm signal causing the abnormal shutdown of the system may be reset when the system is shutdown or the abnormal condition is resolved, and the signal state monitored by the monitor (BMC, also referred to as a Baseboard Management Controller) may be restored to a normal value at this time, so that an engineer often cannot locate the problem, embodiments of the present application provide a latch alarm circuit, which is added before the processor and the monitor, so that the monitor can read the previous abnormal condition through the latch alarm circuit after the signal state is restored, and reset the latch alarm circuit again until the system is restarted, so that even after the abnormal condition of the processor is cleared, even if the monitor does not store the abnormal condition information, the engineer can re-confirm the problem at any time as long as the system does not turn off the auxiliary power supply, and the monitor can re-read the last abnormal condition of the alarm signal at any time, the reason for the location. The principle of the latch alarm circuit will be described below with reference to the application scenario of the latch alarm circuit.
As shown in fig. 1, an embodiment of the present application provides an electronic device, including: the device comprises a processor, a monitor and a latch alarm circuit. The processor is powered by the main power supply, and the monitor is powered by the auxiliary power supply, so that the monitor can normally work in a system shutdown state or a main power supply shutdown state (as long as the auxiliary power supply is not shut down). In the embodiment of the application, the latch alarm circuit with the primary latch function is additionally arranged between the processor and the monitor to latch the abnormal state, so that the problems that the abnormal information is easy to lose and the alarm reason is not easy to locate existing conventional alarm mechanisms are solved.
The latch alarm circuit comprises at least one path of basic circuit. The design principle of each basic circuit is the same, and as shown in fig. 2, each basic circuit includes: the embodiment of the application provides a latch alarm circuit based on an RS trigger, and solves the problems that abnormal information is easy to lose and the reason for alarm is not easy to locate in the conventional alarm mechanism by providing a primary latch function.
Wherein the RS flip-flop includes two input terminals (respectively, the first input terminal (e.g., the first input terminal)
Wherein, the RS flip-flop includes: the two nand gates, i.e., the first nand gate G1 and the second nand gate G2, are connected in cross with each other at their input and output ends to form a basic RS flip-flop, which is a logic diagram, as shown in fig. 3. I.e. the second input (S) of the first NAND-gate G1 is connected to the output (Q) of the second NAND-gate, the output of the first NAND-gate
first, if
Second, if
Third, ifAt this time, the RS trigger keeps the original state.
Fourth, ifThe state of the RS flip-flop cannot be determined at this time and is generally not allowed to occur, i.e. the input of the RS flip-flop
To facilitate understanding of the above-mentioned 4 input-output relationships, a truth table corresponding to the RS flip-flop is given below, as shown in table 1.
TABLE 1
Wherein, Q in Table 10For the last output state, × indicates that the input is not allowed to be 0 at the same time.
The exclusive-nor circuit includes 2 input terminals (a first input terminal (e.g., a) and a second input terminal (e.g., B)) and an output terminal (Y). A first input end of the first input end is connected with the processor and used for receiving an alarm signal (the normal state is 1, the abnormity is 0, the low and effective state is low, and the system can be shut down immediately after being triggered, which can be represented by a CPU _ THERMTRIP _ N in the application) output by the processor, and the first input end is also connected with a second pull-up resistor; the second input end is connected to the processor, and is configured to receive a system state indication signal (for indicating a system state, where power-on is high 1 and power-off is low 0, which may be represented by a CPU _ SLP _ S5 signal) output by the processor, and the second input end of the exclusive-nor circuit is further connected to the pull-down resistor. The exclusive OR gate circuit outputs the system state indicating signal and the alarm signal to a second input end of the RS trigger (such as). The input and output relationship of the exclusive-nor circuit is as follows: the inputs are different, the output is "0", the inputs are the same, and the output is "1".
The exclusive nor circuit is formed by adding a not gate to the output end of the exclusive nor circuit. In addition, the exclusive nor circuit may be configured by only a nand circuit or a nor circuit, which are well known to those skilled in the art and will not be described herein.
The truth table of the signal of each basic circuit is shown in table 2.
TABLE 2
As can be seen from Table 2, due to the pull-down resistor, the CPU _ BMC _ THERMTRIP signal is initially low, and in the power-on state (state ①) when the electronic device is operating normally, once the alarm is triggered, the CPU (e.g., CPU) pulls the CPU _ THERMTRIP _ N signal (e.g., too hot) low to low, and the pulled-down CPU _ THERMTRIP _ N signal (whose true value is 0) is ANDed with the CPU _ SLP _ S5 signal (whose true value is 1), and outputs the low CPU _ THERMTRIP _ N _ R signal to the second input terminal (e.g., the second input terminal of the RS flip-flop) to which the CPU _ SL) At this time, the PWR _ BTN _ N signal (the main power key signal) is still at high level 1, so the CPU _ BMC _ THERMTRIP is set high, the BMC can obtain an alarm state (state ②). after the overheat alarm is triggered, the system is automatically powered off, the CPU _ SLP _ S5 signal is pulled down to low level, then after the abnormal (e.g. overheat) state is released, the CPU _ THERMTRIP _ N signal is restored to normal high level, at this time, the CPU _ THERMTRIP _ N _ R signal state remains unchanged, the CPU _ BMC _ THERMTRIP signal state output by the RS flip-flop remains at high level, that is, the previous state remains unchanged (state ③). in the ③ state, even if the system is powered off, the alarm is released, the BMC can still read the level state of the RS flip-flop output signal CPU _ BMC _ THERMTRIP at any time, the main power key system is restarted in the ③ power off state, and the PWR _ BTN _ N signal is set low and input to the first input terminal (e.g. the first input terminal of the RS flip-flop (
One basic circuit can realize primary latch of one alarm signal, and if different alarm signals (such as an overheat signal, a major error signal, a memory event signal and the like) of the same processor are respectively latched in a primary mode, the number of the basic circuits can be increased. When the number of the basic circuits is multiple (2 paths and more) and only one processor is provided, the alarm signals input by the processors connected to each basic circuit are different.
In addition, a plurality of basic circuits can be used to perform one-stage latch on the alarm signals of a plurality of processors, for example, when the number of the basic circuits is multiple and the number of the processors is the same as that of the basic circuits, each basic circuit corresponds to one processor, and the processors corresponding to different basic circuits are different.
When the number of the basic circuits is multiple, the latch alarm circuit comprises a multiple exclusive OR gate circuit and a plurality of RS triggers, and if the number of the basic circuits is 4, the latch alarm circuit comprises 4 exclusive OR gate circuits and 4 RS triggers. To simplify the circuit, the multiple exclusive-nor circuits can be integrated in the same chip, for example, an SN74HCS7266 chip including 4 exclusive-nor circuits is used. Likewise, multiple RS flip-flops may be integrated into the same chip, such as a chip employing SN74LS279A, which includes 4 RS flip-flops.
It should be noted that one processor may correspond to one basic circuit, or one processor may correspond to multiple basic circuits, which may be designed according to specific requirements. For ease of understanding, the embodiment of the present application shows a circuit schematic diagram of a latch alarm circuit including 4 basic circuits, as shown in fig. 4. Wherein each basic circuit in fig. 4 corresponds to one processor.
The Processor is not limited to the Central Processing Unit (CPU) in the example, and may be a Network Processor (NP), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or a microprocessor or any other conventional Processor.
The latch alarm circuit can be applied to an electronic device comprising the processor powered by the main power supply and the monitor powered by the auxiliary power supply, and the electronic device can be any device with the functional architecture, such as a server.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
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