Two-terminal active capacitor device
阅读说明：本技术 双端子有源电容器装置 (Two-terminal active capacitor device ) 是由 王怀 王浩然 弗雷德·布拉布杰格 于 2019-02-21 设计创作，主要内容包括：具有基于电容值输入C_I的可控电容的有源双端子电容器装置。处理器系统PRS执行算法,该算法利用连接到两个外部端子A、B的可控电开关以及固定值电容器部件C1来控制功率转换器PCV。基于至少对电容器部件C1的两端电压的采样,该算法控制功率转换器PCV,以在外部端子A、B上提供用于匹配电容值输入C_I的所得电容。(An active two-terminal capacitor device having a controllable capacitance based on a capacitance value input C _ I. The processor system PRS executes an algorithm that controls the power converter PCV using controllable electrical switches connected to the two external terminals A, B and a fixed value capacitor component C1. Based on at least the sampling of the voltage across capacitor component C1, the algorithm controls power converter PCV to provide a resulting capacitance on external terminal A, B for matching capacitance value input C _ I.)
1. A capacitor device with a controllable capacitance value input (C _ I) comprises
-a housing (ENC),
a Power Converter (PCV) comprising a plurality of controllable electrical Switches (SWC) interconnected,
a first capacitor component (C1) having a fixed capacitance and being electrically connected to the Power Converter (PCV),
-two external electrical terminals (A, B) arranged to be externally accessible from outside the Enclosure (ENC), wherein at least one of the two external electrical terminals (A, B) is connected to the first capacitor component (C1) and the Power Converter (PCV), and
-a processor system (PRS) arranged to sense at least one input voltage (VC1, VC2) related to one of said two external electrical terminals (A, B) and said first capacitor means (C1) and to process said sensed at least one input voltage (VC1, VC2) according to an algorithm configured to control said Power Converter (PCV) so as to provide a resulting capacitance between said two external electrical terminals (A, B) corresponding to said controllable capacitance value input (C _ I).
2. The capacitor device of claim 1, wherein the processor system (PRS) includes:
-a sampling circuit (SMP) for sampling the sensed at least one input voltage (VC1, VC2) and generating a digital signal output accordingly,
-a digital processor (P) configured to execute an algorithm stored in a memory (M) configured to generate a control signal to control the Power Converter (PCV) in response to the digital signal output from the sampling circuit (SMP) so as to provide the resulting capacitance between the two external electrical terminals (A, B), and
-a gate drive circuit (GD) arranged to control the plurality of controllable electrical Switches (SWC) in response to the control signals from the processor (P).
3. Capacitor device according to claim 1, wherein the processor system (PRS) comprises an analog controller, wherein the algorithm is realized by analog electronic circuits.
4. The capacitor device according to any one of the preceding claims, wherein the Enclosure (ENC) is configured to house the first capacitor component (C1), the Power Converter (PCV) and the processor system (PRS).
5. The capacitor device according to any one of the preceding claims, wherein the Power Converter (PCV) and the processor system (PRS) are arranged inside a resin or gel and positioned inside a housing of the first capacitor component (C1).
6. Capacitor device according to any one of the preceding claims, comprising a self-powering circuit (SPC) connected to receive electric power in a direct or indirect manner from said two external electric terminals (A, B) and to convert said electric power for powering said power converter and said processor system.
7. The capacitor device according to any one of the preceding claims, wherein the processor system (PRS), the Power Converter (PCV) and the first capacitor component (C1) are arranged on a single printed circuit board.
8. A capacitor device according to any one of the preceding claims, configured to receive the controllable capacitance value input (C I) into the memory (M).
9. Capacitor device according to claim 8, wherein the algorithm contains an adjustable coefficient (k) which is adjustable in response to the capacitance value input (C I).
10. A capacitor arrangement according to claim 8 or 9, the capacitor arrangement being configured to receive the controllable capacitance value input (C I) into the memory from outside the housing.
11. A capacitor device according to claim 10, characterized in that the memory (M) is programmable from outside the housing through at least one externally accessible electrical terminal.
12. Capacitor device according to claim 10 or 11, wherein the memory (M) is programmable from outside the housing over a wireless interface.
13. Capacitor device according to claim 8 or 9, configured to receive said controllable capacitance value input (C _ I) through a pre-programmed read-only memory type memory (M) containing at least a pre-programmed code indicative of said controllable capacitance value input (C _ I).
14. A capacitor device according to any one of the preceding claims, configured to receive said controllable capacitance value input (C I) by means of an adjustable device having a plurality of different settings readable by said processor (P).
15. A capacitor arrangement according to any one of the preceding claims, wherein the sampling circuit is arranged to sample a voltage and to generate a digital feedback signal to be provided to the processor (P) accordingly, wherein the algorithm is arranged to adjust the value of the resulting capacitance in response to the digital feedback signal.
16. Capacitor arrangement according to any of the preceding claims, arranged to provide a controllable capacitance value which is at least two times higher than the capacitance of the capacitor component (C1).
17. Capacitor arrangement according to any of the preceding claims, wherein the capacitor component (C1) is an electrolytic capacitor, a film capacitor or a ceramic capacitor.
18. The capacitor arrangement according to any one of the preceding claims, wherein the plurality of controllable electrical switches of the Power Converter (PCV) are connected in a full bridge configuration.
19. Capacitor arrangement according to any of the preceding claims, wherein the power converter comprises a second capacitor component (C2) having a fixed capacitance.
20. A capacitor arrangement according to claim 19, wherein the Sampling Circuit (SC) is arranged to sample a first input voltage (VC1) across the first capacitor component (C1) and a second input voltage (VC2) across the second capacitor component (C2) and to generate the digital signal output accordingly.
21. Capacitor arrangement according to claim 19 or 20, comprising a third capacitor component (C3) having a fixed capacitance, and wherein the first and third capacitor components (C1, C3) are connected in series between the two external electrical terminals (A, B).
22. A capacitor arrangement according to any one of the preceding claims, arranged to handle at least 1kW of power, or at least 100V of voltage, between the two external electrical terminals (A, B).
23. Capacitor arrangement according to any of the preceding claims, arranged to operate with an AC electrical signal at the two external electrical terminals (A, B).
24. Capacitor arrangement according to any of the preceding claims, arranged to operate with a DC electrical signal at the two external electrical terminals (A, B).
25. A power circuit comprising a capacitor arrangement according to any one of the preceding claims.
26. A method for providing a controllable capacitance value (C), the method comprising the steps of:
-receiving (R _ C _ I) an input representing a capacitance value,
-providing a (P _ ENC) housing,
-providing a (P-PCV) power converter comprising a plurality of controllable electrical switches interconnected,
-providing (P _ C1) a first capacitor component having a fixed capacitance and being electrically connected to the power converter,
-providing (P _ A _ B) two external electrical terminals arranged externally accessible from outside the housing, wherein at least one of the two external electrical terminals is connected to the first capacitor part and the power converter,
-sensing (S _ VC1) at least one input voltage related to one of said two external electrical terminals and said first capacitor component, and
-executing (E _ AL) an algorithm configured to generate a control signal to control the power converter in response to the sensed at least one input voltage, so as to provide a resulting capacitance between the two external electrical terminals corresponding to the controllable capacitance value input.
Technical Field
The present invention relates to the field of power systems or power electronic systems, and more particularly, the present invention provides a two-terminal active capacitor device for use in a power electronic system (e.g., a converter). The device can be made compact and the capacitance value can be programmable compared to conventional capacitor components having the same capacitance.
Background
Capacitors are often key components in power systems in terms of cost, volume, and long-term reliability. Capacitors are used in switching circuits, e.g. DC-DC, AC-DC, DC-AC converters, DC bus applications, online anti-shake for stability, adaptive energy buffering, etc.
In particular, high capacitance electrolytic capacitors, which are often used in electrical power (e.g., 10W to several MW) systems, are expensive, bulky, and are known to vary in capacitance over time (years).
Furthermore, each fixed capacitance value requires its own manufacturing line during the manufacturing process. Tunable capacitors are known, but such components are rare at high capacitance values.
Disclosure of Invention
Therefore, in light of the above description, it is an object of the present invention to provide a compact and low cost capacitor device capable of providing a high capacitance that can be adjusted according to a capacitance value input. Furthermore, the device should preferably be able to be used in a wide range of applications with different powers ranging from low power to high power applications.
In a first aspect, the present disclosure provides a capacitor device having a controllable capacitance value input, comprising:
-a housing for holding the device,
a power converter comprising a plurality of controllable electrical switches interconnected,
a first capacitor part having a fixed capacitance and being electrically connected to the power converter,
-two external electrical terminals arranged to be externally accessible from outside the housing, wherein at least one of the two external electrical terminals is connected to the first capacitor component and the power converter, an
-a processor system arranged to sense at least one input voltage related to one of the two external electrical terminals and the first capacitor part, and to process the sensed at least one input voltage according to an algorithm configured to control the power converter so as to provide a resulting capacitance between the two external electrical terminals corresponding to the controllable capacitance value input.
Such a capacitor arrangement is advantageous because it can be seen as an active capacitor with an adjustable capacitance value, especially in embodiments with a self-powering circuit. It can still be provided in a two-terminal package and thus easily be incorporated into existing power circuits to replace conventional capacitor components with fixed capacitance. In particular, the two external electrical terminals may be arranged with the same mutual distance (mutual distance) as the existing passive capacitor component, thereby facilitating replacement of the existing component without further modification. The present disclosure is applicable to low power applications, such as LED driver electronics, and also to high power applications in the kW or MW range.
The fact that the capacitance value is controlled by the processor system means that a high capacitance can be obtained in a housing having a compact size compared to conventional passive capacitor components having the same capacitance. Furthermore, processor-controlled capacitance means that the same capacitance can be maintained for a long time (e.g. +10 or +20 years) even if the capacitance of the first capacitor component changes over time.
Furthermore, the capacitor device is also suitable for high power applications, since the switching circuit topology can be realized with minimal power losses.
Even further, the capacitor arrangement may be configured to allow online adjustment of the resulting capacitance in response to the voltage between the two external electrical terminals. For example, if the observed voltage is within a threshold value, the adjustable capacitance value input may be a nominal capacitance value, and where the voltage exceeds the threshold value, the resulting capacitance may be determined in response to the voltage. Thus, a resulting capacitance can be provided that is responsive to operating conditions (e.g., load or impedance matching) of the application in which the capacitor device is applied. This may allow for an increased efficiency of the power application, which is not possible for capacitor components with a fixed capacitance.
Hereinafter, preferred features and embodiments will be described.
In particular, the algorithm is configured to provide a resulting capacitance of at least 2 times, such as at least 5 times, such as at least 10 times, the fixed capacitance of the first capacitor component.
The processor system may be implemented with a digital processor (e.g., a digital microcontroller) or the algorithm may be implemented as an analog controller with analog electronic circuitry. In the case of a digital processor, the processor system may comprise:
a sampling circuit for sampling the sensed at least one input voltage and generating a digital signal output accordingly,
-a digital processor configured to execute an algorithm stored in a memory, the algorithm configured to generate a control signal to control the power converter in response to the digital signal output from the sampling circuit to provide a resulting capacitance between the two external electrical terminals, and
-a gate drive circuit arranged to control the plurality of controllable electrical switches in response to control signals from the processor.
Preferably, the housing is configured to accommodate the first capacitor component, the power converter and the processor system, e.g. the housing is a box-shaped housing, e.g. a polymer or metal housing, wherein both external electrical terminals are arranged on one side of the housing or on the respective side of the housing. In particular, the housing further houses a self-powered circuit and/or a battery. Thus, a two-terminal active capacitor device is provided which is externally similar to conventional passive capacitor components. At least the housing is preferably used to provide electrical isolation.
In an embodiment, the power converter and processor system may be disposed inside the resin or gel and positioned within the housing of the first capacitor component. Thus, a capacitor arrangement with an increased capacitance compared to the capacitance of the first capacitor part may be obtained, and still sharing the same housing as the first capacitor part.
Preferably, the capacitor means comprises a self-powering circuit connected to receive power in a direct or indirect manner from the two external electrical terminals and to convert the power to power the power converter and the processor system. Thus, the capacitor device can be used as a conventional two-terminal capacitor component without additional inputs. In some applications, batteries may be used to provide the necessary power in lieu of or in addition to self-powered circuitry.
The processor system, the power converter and the first capacitor component may be arranged on a single Printed Circuit Board (PCB), thereby providing a compact element for mounting inside a compact housing.
Depending on the preferred application, the capacitor device may be arranged to receive the controllable capacitance value input in a number of different ways. In some embodiments, the controllable capacitance value input is provided as a pre-stored value in an algorithm stored in a memory, wherein the capacitance value input is provided only once during manufacture of the capacitor device. In other embodiments, the capacitance value input may be provided in the form of an input during normal operation of the capacitor device.
In a preferred embodiment, the capacitor means is configured to receive a controllable capacitance value input into the memory. In particular, the algorithm may include tunable factors or coefficients that may be adjusted in response to capacitance value inputs. The resulting capacitance value can thus be programmed into a memory in which an algorithm is stored. In particular, a predetermined relationship between the factor or coefficient and the resulting capacitance value may be stored in a memory so as to allow for a capacitance value input and a conversion of the factor or coefficient.
In particular, the capacitor arrangement may be configured to receive a controllable capacitance value input into said memory from outside the housing, e.g. through at least one externally accessible electrical terminal and/or through a wireless interface. This allows the capacitance value input to be entered after the capacitive device is manufactured (e.g., during normal operation of the capacitive device). Thus, one capacitor device hardware can be used for differentThe capacitance value of (2). For example, a digital microprocessor based (e.g., MCU CC430 to facilitate a 1GHz radio interface) may be usedTMOr CC2640TM) The processor of (a) obtains such a wireless interface, which allows for external programming of the algorithm, so that the capacitance value input can also be entered wirelessly during manufacture or by a user during normal operation of the capacitor device.
Alternatively, the capacitor device may be configured to receive the controllable capacitance value input through a pre-programmed Read Only Memory (ROM) type memory containing at least a pre-programmed code indicative of the controllable capacitance value input. This allows the capacitance value input to be pre-programmed, for example, to allow pre-fabrication of the components comprising the processor, the power converter and the first capacitor, wherein the ROM memory can be selected to determine the resulting capacitance of the capacitor device in the final manufacturing step.
In some embodiments, the capacitor device is configured to receive a controllable capacitance value input through an adjustable device (e.g., a potentiometer, etc.) having a plurality of different settings that are readable by the processor. In particular, the adjustable device may be mounted on the same PCB on which at least the processor system is mounted. Such an adjustable arrangement allows one capacitor arrangement hardware to be manufactured, which can then be adjusted manually, for example by a user, to provide a particular resulting capacitance.
In some embodiments, the sampling circuit is arranged to sample a voltage (e.g. a voltage between two external electrical terminals or a voltage across the first capacitor component) and to generate a digital feedback signal to be provided to the processor accordingly, wherein the algorithm is arranged to adjust the resulting capacitance value in response to the digital feedback signal. Thereby, for example, the resulting capacitance of the capacitor device may be changed online in response to the operating conditions of the circuit in which the capacitor device is connected. This can be used to improve the efficiency of certain power applications.
In particular, the capacitor component may be an electrolytic capacitor, e.g. having a fixed capacitance of at least 1 μ F, or e.g. having a fixed capacitance of at least 10 μ F. Alternatively, the capacitor component may be a film capacitor or a ceramic capacitor, however other alternatives are also possible.
In particular, the plurality of controllable electrical switches of the power converter may be connected in a full bridge configuration, e.g. comprising 4 controllable electrical switches in an H-bridge configuration. In particular, the controllable electrical switch may comprise an Insulated Gate Bipolar Transistor (IGBT), and/or a controllable electrical switch formed by a MOSFET, a GTO, an IGCT, and/or a power electrical switch based on silicon carbide (SiC) or gallium nitride (GaN) technology.
The power converter preferably comprises a second capacitor component having a fixed capacitance. In particular, the sampling circuit is arranged to sample a first input voltage across the first capacitor component and a second input voltage across the second capacitor component and generate a digital signal output accordingly. In particular, the power converter may comprise a third capacitor component having a fixed capacitance, and wherein the first capacitor component and the third capacitor component are connected in series between two external electrical terminals.
The capacitor arrangement may in particular be designed to handle an electrical power of at least 1kW, for example 10-100kW or even 1MW or higher, and/or be arranged to handle a voltage of at least 100V between the two external electrical terminals. In other embodiments, the capacitor arrangement may be arranged for low power applications, for example in LED driving electronics and the like.
It should be understood that the capacitor device may be arranged to operate with an AC or DC electrical signal at both external electrical terminals. The hardware is the same for AC and DC, but in the algorithm at least one band pass filter should be adapted accordingly, i.e. providing DC component extraction for the DC capacitor and fundamental frequency component extraction for the AC capacitor.
As mentioned in the digital or analog version, the processor and the associated components of the processor system may alternatively be components known to those skilled in the art. In particular, the processor may be a digital microprocessor with digital memory and a sampling system with an analog-to-digital converter, such as is known in the art. Also, gate drive circuits adapted to drive switches of a power converter based on a digital input are known in the art.
In a second aspect, the present disclosure provides a power circuit comprising a capacitor device according to the first aspect. Such a power circuit may be, in particular, a power converter or a rectifier. In general, however, the capacitor arrangement may be used in a variety of circuits, including high power circuits that handle 1-100kW and even up to several MW.
In a third aspect, the present disclosure provides a method for providing a controllable capacitance value, the method comprising the steps of:
-receiving an input indicative of a capacitance value,
-providing a housing for the device,
-providing a power converter comprising a plurality of controllable electrical switches interconnected,
providing a first capacitor part having a fixed capacitance and being electrically connected to the power converter,
-providing two external electrical terminals arranged to be externally accessible from outside the housing, wherein at least one of the two external electrical terminals is connected to the first capacitor component and the power converter, and
-sensing at least one input voltage related to one of the two external electrical terminals and the first capacitor part, and
-executing an algorithm configured to generate a control signal to control the power converter in response to the sensed at least one input voltage, so as to provide a resulting capacitance between the two external electrical terminals corresponding to the controllable capacitance value input.
It will be appreciated that the same advantages and preferred embodiments and features apply to the second and third aspects, as described in the first aspect, and that these aspects may be combined in any manner.
Drawings
The present disclosure will now be described in more detail with reference to the accompanying drawings.
Figure 1 shows a block diagram of an embodiment of a capacitor device,
figure 2 shows another block diagram of an embodiment of a capacitor device,
figures 3a, 3b and 3c show examples of power converter circuits,
figures 4a and 4b show an example of an algorithm with an adjustable coefficient k and a graph showing the relation between k and the resulting capacitance,
figures 5a and 5b show graphs indicating the performance of a particular embodiment,
figure 6 shows an example of an algorithm that implements the capacitance value input as a fixed value,
figure 7 shows an example of a power loss compensation algorithm,
figure 8 shows an example of a self-powering circuit,
figure 9 shows an example of an algorithm with an online variable capacitance,
figure 10 shows the application of a rectifier circuit using the capacitor device of the present disclosure,
FIG. 11 shows an example of the dimensions of a capacitor device embodiment and a conventional capacitor component having a capacitance of only one tenth, and
fig. 12 shows the steps of a method embodiment.
The drawings illustrate particular ways of implementing the inventive concepts and should not be construed as limiting other possible embodiments falling within the scope of the appended claims.
Detailed Description
Fig. 1 shows a block diagram of an embodiment of a capacitor arrangement arranged to receive a controllable capacitance value input C I. The apparatus is arranged to provide a resulting capacitance between the two external electrical terminals A, B such that the resulting capacitance corresponds to the controllable capacitance value input C I.
In the embodiment shown, the casing ENC houses all the following components: the processor circuit PRS, the power converter PCV with a plurality of interconnected controllable electrical switches, the first capacitor means C1 with fixed capacitance, and the self power circuit SPC for supplying all the power demanding means inside the enclosure ENC in a direct or indirect way based on the input from the external terminal A, B. Thus, an active two-terminal capacitor device is provided which allows adjusting its capacitance in response to a capacitance value input C _ I.
As can be seen, a power converter with four controllable electrical switches in an H-bridge configuration, a fixed capacitor component C1, is connected in series between two external electrical terminals A, B. Further, self-supply circuit SPC is also connected to at least one of terminals A, B, or is otherwise connected, directly or indirectly, to terminal A, B. In the illustrated embodiment, the processor system includes a digital microprocessor P with associated memory M having a control algorithm stored therein. As an example, the sampling circuit SMP may be used to sample the voltage across the fixed capacitor component C1 and generate a digital signal output accordingly that is provided to the microprocessor P. The sampling circuit may sample one or two further voltages contained in the digital signal output provided to the microprocessor P. The microprocessor is configured to execute a control algorithm stored in the memory M. The control algorithm is configured to generate a control signal to control the power converter PCV in response to the digital signal output from the sampling circuit SMP, thereby providing a resulting capacitance between the two external electrical terminals A, B. A gate drive circuit GD is arranged to control a plurality of controllable electrical switches SWC of the power converter PCV in response to control signals from the processor P.
In a preferred embodiment, the control algorithm in the memory M contains coefficients that can be adjusted in response to the capacitance value input C _ I to allow the resulting capacitance between the two external electrical terminals to reflect the capacitance value input C _ I.
In this way, an active two-terminal capacitor with adjustable capacitance can be realized.
The connection of the self-powering circuit SPC can be realized in different ways, in which the power comes directly or indirectly from the external terminal A, B. In some embodiments, the self-power circuit SPC may be connected to both power terminals of one of the plurality of controllable electrical switches in the power converter PCV, or in other embodiments, the self-power circuit is connected to the capacitor component, and in further embodiments, the self-power circuit is directly connected to the external terminal A, B. Other connections of the self-powered circuit may also be made through connections via other components of the device to obtain power indirectly from terminal A, B.
The invention is based on the insight that: the processor system and algorithm allow the resulting capacitance to be higher and more stable than conventional capacitor components having the same dimensions. Furthermore, the capacitance value input C _ I allows the capacitor device to have a programmable capacitance. This may be used in various applications to provide hardware that may be programmed to a desired capacitance value after manufacture, or it may be used to provide a user programmable capacitor, or even a capacitor whose capacitance may be adjusted online in response to, for example, a voltage associated with its external electrical terminals A, B.
Fig. 2 shows an embodiment in more detail. In the present embodiment, the power converter includes a second capacitor C2 and a third capacitor C3, both having fixed capacitances. The first and third capacitors C1, C3 are considered to be connected in series between two external electrical terminals A, B. A switching circuit SWC with a controllable electric switch is connected across the third capacitor C3. The second capacitor C2 is connected to the opposite side of the switch circuit SWC from the third capacitor.
The processor system PRS samples two voltages: the voltage VC1 across the first capacitor C1 and the voltage VC2 across the second capacitor C2, which voltages VC1, VC2 are then used in a control algorithm in the processor system PRS to generate drive signals to control controllable electrical switches in the switch circuit SWC. Where C1 and C3 are AC or DC capacitors, graphs are used to indicate the voltage across them.
Fig. 3a-3c show different possible embodiments of the switch circuit SWC of the power converter PCV, i.e. using four, two or six switches. The power converter PCV may be a DC/AC or DC/DC converter.
Fig. 4a shows an example of an implementation of the algorithm, with voltages VC1, VC2 as inputs, as shown in fig. 2. Vcon1 is the control signal related to the equivalent capacitance obtained from the harmonics of VC1 and the coefficient k extracted through the high pass filter HPF. In this algorithm, the resulting capacitance may be adjusted based on a coefficient k, so k may be altered in response to the capacitance value input C _ I to allow the capacitance value input C _ I to adjust the resulting capacitance. The scaling factor a is the ratio between the regulated feedback signal from the voltage across capacitor component C1 and
Fig. 4b shows a graph illustrating a specific embodiment showing the relation between the variable coefficient k and the resulting capacitance in μ F. It can be seen that there is a highly non-linear conversion between the coefficient k and the resulting capacitance. This needs to be compensated for in order to convert the capacitance value input C I into a coefficient k of the resulting capacitance that will result in a match.
For a specific example, fig. 5a shows a diagram representing the impedance matching between a specific implementation of a capacitor arrangement (dashed line) and a passive capacitor component with a fixed capacitance as a function of frequency in amplitude and phase. As can be seen, the impedance match is good at least in the frequency range of 100Hz to 100 kHz.
Fig. 5b shows a graph representing the results of a simulation of the voltage over the capacitor means (active capacitor) and the passive capacitor as a function of time. As shown, the resulting capacitance can be varied between 191-1149 μ F based on the same capacitor device hardware. This means that one hardware component can be manufactured and the capacitor means programmed with the required capacitance value input C _ I to obtain the resulting capacitance over a wide range of capacitances.
Fig. 6 shows another embodiment of the algorithm, which is also based on the voltage inputs VC1,
here, M is a modulation index, which is the maximum value of M in fig. 4a, and Vtric is the amplitude of the PWM triangle signal. Ratio a is the ratio between the regulated feedback signal from the voltage across capacitor component C2 and
The control signal for the variable active capacitor comprises two parts: vcon1 and
In addition, ripple extraction is used to extract ripple from DC or AC signals. Active capacitor hardware is understood to be processor system PRS hardware, power converter PCV and fixed capacitor component C1.
Fig. 7 shows a specific example of the mentioned power loss compensation algorithm part.
Fig. 8 shows a specific example of a self-power supply circuit SPC for supplying power to all the power demand circuits of the capacitor device based on electrical input from the external electrical terminals A, B. Here, the self supply circuit SPC is realized as a circuit connected to two power terminals (e.g. two power terminals of a MOSFET) of one of a plurality of controllable electrical switches in the power converter.
Fig. 9 shows an algorithm implementation in which the resulting capacitance is adjustable online during normal operation, e.g., to adapt to load conditions to achieve a specified voltage ripple ratio. For example, as the load increases, the ripple will be greater if the capacitance is constant. However, based on the variable capacitor device, the capacitance will adapt to the load becoming larger in order to maintain the same voltage ripple ratio for different loads. It can be seen that the algorithm is still based on two voltages VC1, VC2 as inputs.
The voltage ripple ratio function is:
reference is also made here to the above formula given in relation to fig. 6.
Fig. 10 shows a specific example of a single-phase rectifier circuit in which a capacitor device (active capacitor) is used as a DC bus.
Fig. 11 shows a bulky 50mm high box-shaped passive capacitor component (top) and a PCB with hardware components (bottom) having the same basic area as the capacitor component but almost the
Fig. 12 shows steps of an embodiment of a method for providing a controllable capacitance value. The method comprises the following steps: receiving an input that R _ C _1 indicates a capacitance value, e.g., a desired capacitance input by a user. The method comprises the following steps: providing a P _ ENC shell; providing a P _ PCV power converter comprising a plurality of interconnected controllable electrical switches; providing a first capacitor component having a fixed capacitance of P _ C1, and electrically connected to the power converter; two external electrical terminals of P a B are provided, which are arranged to be externally accessible from outside the housing, wherein at least one of the two external electrical terminals is connected to the first capacitor component and the power converter. With these hardware components, the method further comprises: sampling at least one input voltage of S _ VC1 related to one of two external electrical terminals and a first capacitor component; and executing an E AL algorithm (preferably executed on the processor system), wherein the algorithm is configured to generate a control signal to control the power converter in response to the sampled at least one input voltage so as to provide a resulting capacitance between the two external electrical terminals corresponding to the controllable capacitance value input.
In general, the capacitor device according to the present disclosure can be widely applied to power circuit designs, such as renewable energy sources. Specific application examples include: wind generator power converters, photovoltaic inverters, direct current busses of modular multilevel converters in High Voltage Direct Current (HVDC), and motor driven direct current busses.
In summary, the following steps: the present invention provides an active two-terminal capacitor device with a controllable capacitance based on a capacitance value input C _ I. The processor system PRS executes an algorithm that controls the power converter PCV using controllable electrical switches connected to the two external terminals A, B and a fixed value capacitor component C1. Based on at least the sampling of the voltage across capacitor component C1, the algorithm controls power converter PCV to provide a resulting capacitance on external terminal A, B for matching capacitance value input C _ I.
While this disclosure has been described in conjunction with the specified embodiments, it should not be construed as being limited to the examples presented in any way. The scope of the inventive content is to be interpreted according to the appended claims. In the context of the claims, the term "comprising" does not exclude other possible elements or steps. Also, references to items such as "a" or "an" should not be construed as excluding a plurality. The use of reference signs in the claims with respect to elements indicated in the figures shall not be construed as limiting the scope of the present disclosure either. Furthermore, the individual features mentioned in the different claims can be advantageously combined.
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