Dynamic response circuit, oscillator circuit, chip, electronic device, and method
阅读说明:本技术 动态响应电路、振荡器电路、芯片、电子设备及方法 (Dynamic response circuit, oscillator circuit, chip, electronic device, and method ) 是由 陈敏 汪涛 于 2020-06-01 设计创作,主要内容包括:本申请实施例公开了一种动态响应电路、振荡器电路、芯片、电子设备及方法,涉及集成电路技术领域。该动态响应电路应用于振荡器电路,振荡器电路包括至少一对输入对管,每对输入对管包括对称设置的两个输入管;动态响应电路包括开关电容电路以及电压转换电路;开关电容电路,包括多个电容,用于响应时钟信号控制电容进行电荷转移,以获得与时钟信号的频率对应的第一电压;电压转换电路,与开关电容电路连接,用于将第一电压转换为与时钟信号的频率对应的第二电压,并将第二电压输出至输入对管中的一个输入管,以根据第二电压调整输入管的阈值电压。本申请实施例通过获取与频率相关的电压,改变输入对管的尾电流分布,改善振荡器电路的频率特性。(The embodiment of the application discloses a dynamic response circuit, an oscillator circuit, a chip, electronic equipment and a method, and relates to the technical field of integrated circuits. The dynamic response circuit is applied to an oscillator circuit, the oscillator circuit comprises at least one pair of input pair tubes, and each pair of input pair tubes comprises two input tubes which are symmetrically arranged; the dynamic response circuit comprises a switched capacitor circuit and a voltage conversion circuit; the switch capacitor circuit comprises a plurality of capacitors and is used for responding to a clock signal to control the capacitors to carry out charge transfer so as to obtain a first voltage corresponding to the frequency of the clock signal; and the voltage conversion circuit is connected with the switched capacitor circuit and is used for converting the first voltage into a second voltage corresponding to the frequency of the clock signal and outputting the second voltage to one input tube of the input pair tubes so as to adjust the threshold voltage of the input tube according to the second voltage. According to the embodiment of the application, the tail current distribution of the input pair tube is changed by acquiring the voltage related to the frequency, and the frequency characteristic of the oscillator circuit is improved.)
1. A dynamic response circuit is applied to an oscillator circuit, wherein the oscillator circuit comprises at least one pair of input pair tubes, and each pair of input pair tubes comprises two input tubes which are symmetrically arranged; the dynamic response circuit comprises a switched capacitor circuit and a voltage conversion circuit;
the switched capacitor circuit comprises a plurality of capacitors and is used for responding to a clock signal to control the capacitors to carry out charge transfer so as to obtain a first voltage corresponding to the frequency of the clock signal;
the voltage conversion circuit is connected with the switched capacitor circuit and is used for converting the first voltage into a second voltage corresponding to the frequency of the clock signal and outputting the second voltage to one input tube of the input pair tubes so as to adjust the threshold voltage of the input tube according to the second voltage.
2. The dynamic response circuit of claim 1, wherein the voltage conversion circuit comprises a voltage-to-current conversion circuit, a current mirror circuit, and a current-to-voltage conversion circuit;
the voltage-current conversion circuit is connected with the output end of the switched capacitor circuit and is used for converting the first voltage into input current;
the current mirror circuit is connected with the output end of the voltage-current conversion circuit and used for outputting mirror current according to the input current;
the current-voltage conversion circuit is connected with the current mirror circuit and the substrate end of one of the input pair transistors, and is used for converting the mirror current into the second voltage and outputting the second voltage to the substrate end of the connected input transistor.
3. The dynamic response circuit of claim 2, wherein the current-to-voltage conversion circuit comprises an adjustable resistor network for converting the mirrored current to an adjustable second voltage.
4. The dynamic response circuit of claim 2, wherein the mirror current comprises alternating first and second mirror currents; the current mirror circuit comprises a gating circuit, a first current mirror and a second current mirror;
the gating circuit is connected with the first current mirror and the second current mirror and used for conducting the first current mirror when the clock signal is at a first level and conducting the second current mirror when the clock signal is at a second level;
the first current mirror is connected with the voltage-current conversion circuit and the current-voltage conversion circuit and used for generating the first mirror current according to the input current when the first current mirror is conducted;
the second current mirror is connected with the voltage-current conversion circuit and the current-voltage conversion circuit and used for generating the second mirror current according to the input current when the second current mirror is conducted.
5. The dynamic response circuit of claim 4, wherein the gating circuit comprises a first switch and a second switch;
the first switch is connected between the voltage-current conversion circuit and the input branch of the first current mirror and is used for conducting when the clock signal is at a first level;
the second switch is connected between the voltage-current conversion circuit and the input branch of the second current mirror and is used for conducting when the clock signal is at a second level.
6. The dynamic response circuit of claim 4 or 5, wherein the second current mirror is further connected to the input terminal of the switched-capacitor circuit, and the second current mirror is further configured to generate a third mirror current according to the input current when the switched-capacitor circuit is turned on, and input the third mirror current to the switched-capacitor circuit to charge the capacitor of the switched-capacitor circuit.
7. An oscillator circuit, characterized in that the oscillator circuit comprises a comparator circuit, a clock circuit and a dynamic response circuit according to any of claims 1-6;
the comparator circuit comprises at least one pair of input pair tubes, each pair of input pair tubes comprises a first input tube and a second input tube which are symmetrically arranged, and the first input tube of the at least one pair of input pair tubes is connected with the voltage conversion circuit so as to adjust the threshold voltage of the first input tube according to the second voltage output by the voltage conversion circuit; when the threshold voltage of the first input tube is larger than that of the second input tube, the current flowing through the first input tube is larger than that flowing through the second input tube;
the comparator circuit is used for comparing input signals respectively received by the first input tube and the second input tube to obtain output signals and transmitting the output signals to the clock circuit;
and one end of the clock circuit is connected with the output end of the comparator circuit, and the other end of the clock circuit is connected with the switched capacitor circuit and is used for generating a clock signal according to an output signal of the comparator circuit and outputting the clock signal to the switched capacitor circuit.
8. The oscillator circuit of claim 7, further comprising a temperature compensation circuit, wherein the first current mirror and the second current mirror are respectively connected to a current input of the temperature compensation circuit to output the mirror current to the temperature compensation circuit;
the temperature compensation circuit is connected with the substrate end of the second input tube and used for adjusting the threshold voltage of the second input tube according to the mirror image current.
9. The oscillator circuit of claim 8, wherein the temperature compensation circuit comprises a compensation voltage generation circuit and a voltage superposition circuit;
the compensation voltage generation circuit is connected with the current input end and used for acquiring the mirror current, comparing the mirror current with a preset reference current and outputting a first compensation voltage with a temperature characteristic according to a comparison result;
the voltage superposition circuit is connected with the compensation voltage generation circuit and used for acquiring the first compensation voltage, carrying out superposition processing on the first compensation voltage and a preset reference voltage to acquire a second compensation voltage, and outputting the second compensation voltage to the substrate end of the second input tube so as to adjust the threshold voltage of the second input tube according to the second compensation voltage.
10. The oscillator circuit according to claim 9, wherein the compensation voltage generating circuit comprises a positive temperature coefficient voltage generating unit, a current comparing unit, and a weighting unit;
the positive temperature coefficient voltage generating unit is used for generating a voltage with a positive temperature coefficient;
one end of the current comparison unit is connected with the current input end, and the current comparison unit is used for comparing the preset reference current with the mirror current and determining a temperature compensation coefficient according to a comparison result;
the weighting unit is respectively connected with the positive temperature coefficient voltage generating unit and the current comparing unit, and is used for weighting the voltage with the positive temperature coefficient according to the temperature compensation coefficient to obtain the first compensation voltage and outputting the first compensation voltage to the voltage superposition circuit.
11. A chip comprising a dynamic response circuit as claimed in any one of claims 1 to 6 or an oscillator circuit as claimed in any one of claims 7 to 10.
12. An electronic device comprising a device body and a chip as claimed in claim 11.
13. A dynamic response method is applied to an oscillator circuit, wherein the oscillator circuit comprises at least one pair of input pair tubes, and each pair of input pair tubes comprises two input tubes which are symmetrically arranged; the method comprises the following steps:
responding to a clock signal, and obtaining a first voltage corresponding to the frequency of the clock signal;
and converting the first voltage into a second voltage corresponding to the frequency of the clock signal, and outputting the second voltage to one of the input pair tubes so as to adjust the threshold voltage of the input tube according to the second voltage.
Technical Field
The present application relates to the field of integrated circuit technologies, and more particularly, to a dynamic response circuit, an oscillator circuit, a chip, an electronic device, and a method.
Background
With the advent of the internet of things era, the smart home and the intelligent health industry have come to urge greater demands on Micro Control Unit (MCU) chips. With the development of the single chip microcomputer technology (MCU chip), the rapid development of the semiconductor technology and the process enables the performance of the MCU product to be greatly improved, and the MCU with low cost, high precision, high integration and high stability occupies more and more market shares, thereby becoming the focus of attention of MCU manufacturers.
The clock generation circuit is an indispensable module in the field of MCU, and the performance of the clock generation circuit plays a vital role on the MCU chip. In order to save cost, the MCU chip generally integrates an RC oscillator. With the improvement of the performance of the MCU, higher and higher requirements are also put forward on the speed, the precision and the power consumption of the oscillator.
Disclosure of Invention
The application provides a dynamic response circuit, an oscillator circuit, a chip, electronic equipment and a method, which are used for improving the dynamic response capability of an oscillator.
In a first aspect, an embodiment of the present application provides a dynamic response circuit, which is applied to an oscillator circuit, where the oscillator circuit includes at least one pair of input pair transistors, and each pair of input pair transistors includes two input tubes symmetrically arranged; the dynamic response circuit comprises a switched capacitor circuit and a voltage conversion circuit; the switched capacitor circuit comprises a plurality of capacitors and is used for responding to a clock signal to control the capacitors to carry out charge transfer so as to obtain a first voltage corresponding to the frequency of the clock signal; the voltage conversion circuit is connected with the switched capacitor circuit and is used for converting the first voltage into a second voltage corresponding to the frequency of the clock signal and outputting the second voltage to one input tube of the input pair tubes so as to adjust the threshold voltage of the input tube according to the second voltage.
In a second aspect, embodiments of the present application further provide an oscillator circuit, where the oscillator circuit includes a comparator circuit, a clock circuit, and the dynamic response circuit as described in the first aspect above; the comparator circuit comprises at least one pair of input pair tubes, each pair of input pair tubes comprises a first input tube and a second input tube which are symmetrically arranged, and the first input tube of the at least one pair of input pair tubes is connected with the voltage conversion circuit so as to adjust the threshold voltage of the first input tube according to the second voltage output by the voltage conversion circuit; when the threshold voltage of the first input tube is larger than that of the second input tube, the current flowing through the first input tube is larger than that flowing through the second input tube; the comparator circuit is used for comparing input signals respectively received by the first input tube and the second input tube to obtain output signals and transmitting the output signals to the clock circuit; and one end of the clock circuit is connected with the output end of the comparator circuit, and the other end of the clock circuit is connected with the switched capacitor circuit and is used for generating a clock signal according to an output signal of the comparator circuit and outputting the clock signal to the switched capacitor circuit.
In a third aspect, an embodiment of the present application further provides a chip, including the dynamic response circuit according to the first aspect or the oscillator circuit according to the second aspect.
In a fourth aspect, embodiments of the present application further provide an electronic device, which includes a device main body and the oscillator circuit as described in the third aspect.
In a fifth aspect, the embodiments of the present application further provide a dynamic response method, which is applied to an oscillator circuit, where the oscillator circuit includes at least one pair of input pair transistors, and each pair of input pair transistors includes two input pipes symmetrically arranged; the method comprises the following steps: responding to a clock signal, and obtaining a first voltage corresponding to the frequency of the clock signal; and converting the first voltage into a second voltage corresponding to the frequency of the clock signal, and outputting the second voltage to one of the input pair tubes so as to adjust the threshold voltage of the input tube according to the second voltage.
The dynamic response circuit, the oscillator circuit, the chip, the electronic device and the method provided by the embodiment of the application are connected with the switched capacitor circuit through the voltage conversion circuit to obtain a first voltage corresponding to the frequency of the clock signal, obtain a second voltage corresponding to the frequency of the clock signal after conversion, and output the second voltage to one of the input tubes of the input pair tubes in the oscillator circuit so as to adjust the threshold voltage of the input tube according to the second voltage, so that the threshold voltages of the two input tubes are different, the tail current distribution ratio of the two input tubes in the input pair tubes can be changed, the path current of the input tube with relatively higher threshold voltage is smaller than that of the input tube with relatively lower threshold voltage, the turning of the high and low levels of the comparator can be accelerated when the integral input current of the comparator is not changed, the turning delay is reduced, the dynamic response capability of the comparator is improved, and the frequency characteristic of the oscillator circuit is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a schematic diagram of an oscillator circuit suitable for use in embodiments of the present application.
FIG. 2 illustrates a schematic diagram of a dynamic response circuit provided by an embodiment of the present application;
FIG. 3 illustrates a schematic diagram of a dynamic response circuit provided by another embodiment of the present application;
FIG. 4 illustrates a schematic diagram of an oscillator circuit provided by an embodiment of the present application;
FIG. 5 illustrates a schematic diagram of a current mirror load provided by an exemplary embodiment of the present application;
FIG. 6 shows a schematic diagram of a current mirror load provided by another exemplary embodiment of the present application;
FIG. 7 illustrates a schematic diagram of an oscillator circuit provided by another embodiment of the present application;
FIG. 8 illustrates a schematic diagram of a temperature compensation circuit provided by yet another embodiment of the present application;
FIG. 9 is a flow chart illustrating a dynamic response method provided by an embodiment of the present application;
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the embodiments of the present application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
At present, a dual-comparator RC oscillating circuit is generally used to generate a high-speed clock, and the principle is shown in fig. 1. The RC oscillator circuit shown in fig. 1 includes two comparators (comparators CMP1 and CMP2, respectively), an RS latch, and two inverters (first inverter INV1 and second inverter INV2, respectively), wherein the RS latch triggered by a low level is taken as an example for explanation.
Assume that the first output signal G1 of the first inverter INV1 is 0, the second output signal G2 of the inverter INV2 is 1, the switches S1 and S4 are closed, the switches S2 and S3 are opened, the capacitor C1 is charged, the capacitor C2 is discharged, and the reference voltage connected to the positive input terminals of the comparators CMP1 and CMP2 is VREF. Then, as the voltage of the capacitor C1 increases, the output result of the comparator CMP1 flips from high level to low level, and after passing through the RS latch triggered by low level, the first output signal G1 becomes 1 and the second output signal G2 becomes 0. At this time, the switches S1 and S4 are opened, the switches S2 and S3 are closed, the capacitor C2 is charged, the capacitor C1 is discharged, the output result of the comparator CMP2 is inverted along with the voltage rise of the capacitor C2, the high level is changed into the low level, after passing through the RS latch, the first output signal G1 is changed into 0, the second output signal G2 is changed into 1, so that a complete charge-discharge cycle is completed, and a periodic clock signal can be formed by the cyclic reciprocation.
From fig. 1, a formula of the reference voltage VREF can be obtained as formula (1), and an equation as formula (2) can be obtained as follows:
VREF ═ R1 · I1 formula (1)
t.i 2 ═ C1. VREF formula (2)
Wherein I1 is the output current of the current source I1, t is the duration of a charging cycle, C1 is the capacitance of the capacitor C1, and I2 is the output current of the current source I2, the equations (1) and (2) are shown:
due to the symmetrical structure, and I1: i2 ═ 1: n, C1 ═ C2, available from formula (3):
wherein f is the oscillation frequency of the RC oscillation circuit, and as can be seen from formula (4), the oscillation frequency f is related to R1, I1, I2, C1/C2, and if a reasonable ratio between the current I1 and the current I2 is set and fixed to I1: if I2 is 1: N, the oscillation frequency f is dependent on the resistance R1 and only one of the capacitors C1 or C2.
The inventors have found that there may be a delay in the comparator flip, thereby causing fluctuations in the oscillation frequency f. For example, assuming that the comparator has a flip-over delay t1, and the charging time of the capacitors C1 and C2 in one cycle is t2, the time required for the whole cycle is 2(t1+ t 2). Wherein the content of the first and second substances,
at this time, the oscillation frequency f can be obtained by the following equation:
as can be seen from equation (6), if the delay t1 is too long, the period of the output clock will be longer, and the oscillation frequency will be affected, so to accelerate the flip of the comparator, the delay t1 of the comparator will be reduced, and the ratio of the effective charging time t2 of the capacitors C1 and C2 in the whole period will be increased.
As can be seen from fig. 1 and the above analysis, the RS latch is triggered only when the comparator is actively flipped, i.e., high level is flipped to low level, and a state change occurs; when the comparator is turned from low level to high level, the RS latch can not be triggered, and the working state of the whole circuit can not be influenced.
In a conventional oscillator circuit, a symmetrical comparator structure is generally adopted, and when the comparator is inverted from a low level to a high level or from the high level to the low level, the current drive of an internal input pair tube of the comparator is the same. If a high frequency is required, a large current drive is required, so the output frequency of the conventional comparator structure is limited by the comparator.
Therefore, in view of the above problems, embodiments of the present application provide a dynamic response circuit, an oscillator circuit, a chip, an electronic device, and a method, so as to improve the dynamic response capability of a comparator and improve the frequency characteristic of an oscillator. In order to better understand the embodiments of the present application, the dynamic response circuit, the oscillator circuit, the chip, the electronic device, and the method provided by the embodiments of the present application will be described in detail below with specific embodiments.
As shown in fig. 2, fig. 2 schematically illustrates a dynamic response circuit provided by an embodiment of the present application. Wherein the
The
In this embodiment, the
The switched
In some embodiments, the switched-
The
In some embodiments, the tail current Itail is generated by a current source for providing current to the
Since the comparator generally has only one side flip to trigger the change of the state of the RS latch, if the flip is recorded as an effective flip, the dynamic response capability of the comparator can be improved by only accelerating the effective flip, and the frequency characteristic of the
Therefore, the
As shown in fig. 3, fig. 3 schematically illustrates a dynamic response circuit provided in another embodiment of the present application, in this embodiment, the
The voltage-
In this embodiment, the transistor may be a transistor, a MOS transistor, or another transistor, and the resistor may also be various devices having a resistance characteristic, such as a magnetic bead having a resistance characteristic, which is not limited in this embodiment.
The
The current-
In some embodiments, the current-to-
In some embodiments, the switched
In some embodiments, the mirror current output by the
The first
As an embodiment, the
In some embodiments, the second
In a specific example, as shown in fig. 3, the switched
Specifically, when the clock signal CK is at a first level, e.g., CK is high, the switch Sc0, the switch Sc2, and the switch Sc4 are turned on, the switch Sc1, and the switch Sc3 are turned off, the capacitor Cc2 is connected to the negative terminal of the operational amplifier a1 through the switch Sc2, and the first voltage VN2 is generated at the output terminal of the operational amplifier a1 (i.e., the node N2).
When the clock signal is at the second level, for example, CK is low, the switch Sc0, the switch Sc2 and the switch Sc4 are turned off, the switch Sc1 and the switch Sc3 are turned on, the first voltage VN2 at the output end of the integrating circuit is not changed, the voltage-
VCc1 ═ VCc2 ═ t × Ic0/(Cc1+ Cc2) ═ Ic0/[2 × f × (Cc1+ Cc2) ] formula (7)
In the formula (7), Cc1 and Cc2 represent capacitance values of the capacitor Cc1 and the capacitor Cc2, respectively.
When the clock signal CK is high again, the capacitor Cc2 is switched to be connected to the negative terminal of the operational amplifier a1, and the operational amplifier a1 compares the voltage Ic0/[2 × f (Cc1+ Cc2) ] generated by the charge stored in the capacitor Cc2 at the previous time (when CK is low) with the bias voltage Vmid, thereby generating a new first voltage VN2 and current Ic2 as the input current of the
Further, the current-
When the bulk voltages of the input tubes M1 and M2 are equal, that is, VB1 is VB2, the threshold voltage of the input tube M2 is the threshold voltage of the input tube M1. By changing the bulk voltage VB1 of the input tube M1, the current distribution ratio of the input tube of the comparator to the tube is further changed. When the bulk voltage VB1> VB2 and the threshold voltage of the input tube M1 > the threshold voltage of the input tube M2, the current path current > Itail/2 corresponding to the input tube M2 and the current path current < Itail/2 corresponding to the input tube M1 drive the branch of the input tube M2 with more current, so as to accelerate the inversion of the high and low levels of the comparator. When the oscillator frequency f is higher, the detected bulk voltage VB1 of the input tube M1 is higher, the distribution proportion difference of the tail current Itail between the input tube M1 and the
As shown in fig. 4, fig. 4 schematically illustrates an oscillator circuit provided in an embodiment of the present application, where the
The
The
The
In one embodiment, the first input transistor M1 and the second input transistor M2 are both fets, the input terminals of the first input transistor M1 and the second input transistor M2 are connected to a tail current source, and the output terminals of the first input transistor M1 and the second input transistor M2 are grounded through a load circuit.
In an embodiment, the load circuit may be a current mirror load, and the connection manner of the current mirror load is not limited in this embodiment, it is understood that, if the connection manner of the current mirror load is different and the phases are different, the comparator positive terminal signal INP1 and the comparator negative terminal signal INN1 corresponding to the two input tubes are different. For example, the current mirror load may be connected as shown in fig. 5, and the first input tube M1 corresponds to the negative terminal signal INN1 of the comparator, and the second input tube M2 corresponds to the positive terminal signal INP1 of the comparator; for another example, the current mirror load may be connected as shown in fig. 6, but the connection is reversed in this case, and the correspondence relationship shown in fig. 4 is the same. In other embodiments, the load circuit may not be connected as shown in fig. 5 and 6, or may not be a current mirror load, which is not limited in this embodiment.
The
In some embodiments, the
In addition, in some embodiments, the temperature drift characteristics of the
Specifically, the first
In some embodiments, as shown in fig. 8, fig. 8 schematically illustrates a temperature compensation circuit provided in another embodiment of the present application, and in this embodiment, the temperature compensation circuit 400 may include a compensation voltage generation circuit 410 and a voltage superposition circuit 420.
The compensation voltage generating circuit 410 is connected to the current input terminal of the temperature compensation circuit 400, and is configured to obtain the mirror current Ic, compare the mirror current Ic with the preset reference current Iref, and output the first compensation voltage VT1 having the temperature characteristic according to the comparison result.
The voltage superimposing circuit 420 is connected to the compensation voltage generating circuit 410, and is configured to obtain a first compensation voltage VT1, perform superimposing processing on the first compensation voltage VT1 and a preset reference voltage to obtain a second compensation voltage VT2, and output the second compensation voltage VT2 to the substrate end of the second input tube M2, so as to adjust the bulk voltage VB2 of the second input tube M2 according to the second compensation voltage VT 2.
In one embodiment, the compensation voltage generating circuit 410 may include a positive temperature coefficient voltage generating unit 411, a current comparing unit 412, and a weighting unit 413;
wherein the ptc voltage generation unit 411 is configured To generate a voltage K1 × kT/q with a positive temperature coefficient, and in some examples, the ptc voltage generation unit 411 may be a PTAT (Proportional To absolute temperature) current source.
One end of the current comparing unit 412 is connected to the current input end of the temperature compensating circuit 400, and the current comparing unit 412 is configured to compare the preset reference current Iref with the mirror current Ic, and determine the temperature compensation coefficient K0 according to the comparison result.
The weighting unit 413 is connected to the positive temperature coefficient voltage generating unit 411 and the current comparing unit 412, and configured to perform weighting processing on the voltage K1 × kT/q with the positive temperature coefficient according to the temperature compensation coefficient K0 to obtain a first compensation voltage VT1 ═ K0 × K1 × kT/q, and output the first compensation voltage K0 × K1 × kT/q to the voltage superimposing circuit 420.
In an embodiment, the Current comparing unit 412 may further include a reference Current source and a Current quantizing unit (Current Quantizer), the preset reference Current Iref is generated by the reference Current source, and is quantized and compared with the mirror Current Ic input from the Current input terminal of the temperature compensating circuit 400 and the preset reference Current Iref by the Current quantizing unit to generate a quantized parameter dtim, and further the quantized parameter dtim may be used as the temperature compensating coefficient K0, the weighting unit 412 weights the temperature compensating coefficient K0 and the voltage K1 × kT/q with the positive temperature coefficient output by the positive temperature coefficient voltage generating unit 411 to obtain a first compensating voltage K0 × K1 × kT/q, and outputs the first compensating voltage K0 × K1 × kT/q to the voltage superimposing circuit 420.
In another embodiment, in order to improve the compensation accuracy, the current comparing unit 412 may further include a Trimming Network (Trimming Network), and the current quantizing unit generates a quantization parameter dtim, where the quantization parameter dtim may be used to control the Trimming Network to generate a temperature compensation coefficient K0, the temperature compensation coefficient K0 and the voltage K1 × kT/q with the positive temperature coefficient output by the positive temperature coefficient voltage generating unit 411 output a first compensation voltage K0 × K1 × kT/q through the weighting process of the weighting unit 412, and output the first compensation voltage K0 × K1 × kT/q to the voltage superimposing circuit 420.
In some embodiments, the voltage superimposing circuit 420 may include a zero-temperature-drift bandgap Reference voltage source (bandgap voltage Reference) for generating a zero-temperature-drift bias voltage Vbulk, where the bias voltage Vbulk is a voltage input to the second input tube M2 at zero temperature drift, that is, at zero temperature drift, the bulk voltage VB2 of the second input tube M2 is equal to the bias voltage Vbulk. When there is a temperature drift, the second compensation voltage related to the temperature coefficient needs to be superimposed to adjust the bulk voltage VB2 of the second input tube M2, so that the mirror current Ic input at the current input end of the temperature compensation circuit 400 is equal to the reference current Iref. As an embodiment, the voltage superposition circuit 420 may further include another weighting unit, which is connected to the bandgap reference voltage source and configured to multiply the bandgap reference voltage Vbg generated by the bandgap reference voltage source by a coefficient K2 to obtain a bias voltage Vbulk-K2-Vbg. The weighting unit is further connected with an adder, and the adder superposes the bias voltage Vbulk and the first compensation voltage K0K 1 kT/q to generate a second compensation voltage VT2 ═ Vbulk + K0K 1 kT/q.
The principle of reducing the temperature drift of the
Accordingly, the voltage superimposing circuit 420 superimposes the first compensation voltage K0 × K1 × kT/q and the bias voltage Vbulk with zero temperature drift to generate the second compensation voltage Vbulk + K0 × K1 × kT/q with a positive temperature coefficient, and further changes the bulk voltage VB2 of the second input tube M2 to Vbulk + K0 × K1 × kT/q, so that the threshold voltage of the second input tube M2 corresponding to the positive end signal INP1 of the
Therefore, with the temperature compensation circuit 400 provided in the above embodiment, the second compensation voltage Vbulk + K0K 1 kT/q can be generated based on the image current Ic output by the dynamic response circuit and related to the frequency, and compared with the preset reference current Iref in a quantization manner, so as to further control the threshold voltage of the input tube of the
In addition, in some embodiments, the temperature compensation circuit 400 further includes a temperature compensation switch unit connectable between the current input terminals of the first
As shown in fig. 9, fig. 9 also schematically illustrates a dynamic response method provided by an embodiment of the present application, which is applied to an oscillator circuit, where the oscillator circuit includes at least one pair of input pair tubes, and each pair of input pair tubes includes two input tubes symmetrically arranged, and specifically, the method may include:
step S110: in response to the clock signal, a first voltage corresponding to a frequency of the clock signal is obtained.
The capacitor is controlled to carry out charge transfer through the switched capacitor circuit in response to the clock signal, and a first voltage corresponding to the frequency of the clock signal is obtained.
Step S120: and converting the first voltage into a second voltage corresponding to the frequency of the clock signal, and outputting the second voltage to one of the input tubes so as to adjust the threshold voltage of the input tube according to the second voltage.
The obtained first voltage is output to a voltage conversion circuit, a second voltage related to the frequency of the clock signal is output to one input tube through the voltage conversion circuit, the threshold voltage of the input tube is adjusted according to the second voltage, the threshold voltages of the two input tubes in the input tube are different, the distribution proportion of tail currents flowing through the two input tubes in the input tube can be changed, the path current of the input tube with the relatively higher threshold voltage is smaller than that of the input tube with the relatively lower threshold voltage, and therefore when the integral input current of the input tube of the comparator is not changed, the overturning of the high level and the low level of the comparator can be accelerated, the overturning delay is reduced, the dynamic response capability of the comparator is improved, and the frequency characteristic of the oscillator circuit is improved.
The dynamic response method provided by this embodiment controls the capacitor to perform charge transfer by responding to the clock signal through the switched capacitor circuit, obtains the first voltage corresponding to the frequency of the clock signal, and outputs the first voltage to the voltage conversion circuit, outputs the second voltage related to the frequency of the clock signal to one of the input tubes through the voltage conversion circuit, changes the threshold voltage of the input tube, so that the threshold voltages of the two input tubes are different, thereby changing the distribution ratio of the tail currents flowing through the two input tubes in the input pair tube, and making the path current of the input tube with a relatively higher threshold voltage smaller than the input tube with a relatively lower threshold voltage, so that when the magnitude of the input current of the comparator input pair tube is not changed, the inversion of the high and low levels of the comparator can be accelerated, the inversion delay can be reduced, the dynamic response capability of the comparator can be improved, and the frequency characteristics of the oscillator circuit can be improved, and the power consumption of the comparator can be reduced by 50% under the same frequency. Particularly, when the oscillation frequency is high, the threshold voltage of one of the input tubes in the input pair tubes is adjusted through frequency detection, so that the dynamic response of the comparator is accelerated, and the high frequency is reduced.
Embodiments of the present application further provide a chip, where the chip is provided with the dynamic response circuit or the oscillator circuit described in any of the above embodiments, and has the beneficial effects described in the corresponding embodiments, and details are not repeated herein. In some examples, the chip may be an MCU chip, which may be used for various electronic devices.
An embodiment of the present application further provides an electronic device, where the electronic device includes a device main body and the chip, and the chip may include the dynamic response circuit or the oscillator circuit according to any of the embodiments, and has the beneficial effects described in the corresponding embodiments, and details are not repeated herein.
The electronic equipment can be electronic scales such as a weight scale and a body fat scale, or intelligent wearing products such as a bracelet, a watch and intelligent underwear, or household appliances such as a refrigerator, a floor sweeping robot, an air conditioner, a television and an intelligent closestool, or terminal equipment such as a mobile phone, a tablet personal computer, a notebook computer, a desktop computer and an upper computer, or internet of things equipment, or an earphone, an electronic cigarette, a mobile power supply and the like, and the type of the electronic equipment is not limited in the embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
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