阅读说明：本技术 使用边缘堆叠的半导体组合件及其制造方法 (Semiconductor assembly using edge stacking and method of manufacturing the same ) 是由 T·H·金斯利 于 2018-12-03 设计创作，主要内容包括：本文中揭示使用边缘堆叠的半导体组合件及相关联的系统及方法。在一些实施例中,所述半导体组合件包括经堆叠的半导体封装,所述经堆叠的半导体封装包含：基底衬底,其具有基底表面；侧衬底,其具有正交于所述基底表面的侧表面；及裸片堆叠,其经安置于所述基底表面上方且具有拥有正交于所述侧表面的最外表面的最外裸片。所述侧衬底可经由从所述侧衬底的所述侧表面延伸到所述第一衬底的所述第一表面或所述最外裸片的所述第三表面的多个互连件而电耦合到所述裸片堆叠。所述半导体封装可进一步包括在所述侧衬底的外表面处的导电材料,借此允许所述半导体封装经由所述导电材料电耦合到相邻半导体封装。(Semiconductor assemblies using edge stacking and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assembly comprises a stacked semiconductor package, the stacked semiconductor package including: a base substrate having a base surface; a side substrate having a side surface orthogonal to the base surface; and a die stack disposed over the base surface and having an outermost die having an outermost surface orthogonal to the side surface. The side substrate can be electrically coupled to the die stack via a plurality of interconnects extending from the side surface of the side substrate to the first surface of the first substrate or the third surface of the outermost die. The semiconductor package may further include a conductive material at an outer surface of the side substrate, thereby allowing the semiconductor package to be electrically coupled to an adjacent semiconductor package via the conductive material.)

1. A semiconductor package, comprising:

a first substrate having a first surface;

a second substrate having a second surface substantially orthogonal to the first surface;

one or more dies over the first surface, wherein an outermost die of the one or more dies includes a third surface that is substantially orthogonal to the second surface; and

a plurality of wire bonds extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate or (b) the third surface of the outermost die.

2. The semiconductor package of claim 1, wherein the second substrate includes a first side and a second side opposite the first side, wherein the second surface is at the first side, and wherein the second side includes external connection sites having exposed conductive material electrically coupled to an external package.

3. The semiconductor package of claim 2, wherein the conductive material corresponds to an array of contact points.

4. The semiconductor package of claim 1, wherein the first substrate includes a first side and a second side opposite the first side, wherein the first surface is at the first side, and wherein the second side includes external connection sites having exposed conductive material electrically coupled to an external package.

5. The semiconductor package of claim 1, wherein the first substrate is a base substrate and the second substrate is a side substrate attached to and extending vertically away from the base substrate.

6. The semiconductor package of claim 1, wherein the outermost die includes a plurality of first bond pads at the third surface and the second substrate includes a plurality of second bond pads at the second surface, and wherein the wire bonds extend from the first bond pads to the second bond pads.

7. The semiconductor package of claim 1, wherein the first substrate includes a plurality of first bond pads at the first surface and the second substrate includes a plurality of second bond pads at the second surface, and wherein the wire bonds extend from the first bond pads to the second bond pads.

8. The semiconductor package of claim 1, wherein the second substrate includes an outermost edge, the semiconductor package further comprising a mold material disposed over the first substrate and at least partially covering the one or more dies and the wire bonds, wherein the mold material includes a fourth surface that is substantially coplanar with the outermost edge of the second substrate.

9. The semiconductor package of claim 1, wherein the third surface of the outermost die is separated from the first surface of the first substrate by a first distance, and wherein the second substrate includes an outermost edge separated from the first surface of the first substrate by a second distance that is greater than or equal to the first distance.

10. The semiconductor package of claim 1, further comprising:

a third substrate having a third surface;

a fourth substrate having a fourth surface; and

a fifth substrate having a fifth surface,

wherein the third surface, the fourth surface, and the fifth surface are each substantially orthogonal to the first surface.

11. The semiconductor package of claim 10, wherein the second, third, fourth, and fifth substrates are attached to the first substrate via a uniform bonding material over the first surface.

12. A semiconductor package as recited in claim 10, wherein the third, fourth and fifth substrates are attached to one another via a bonding material extending vertically along each of the third, fourth and fifth substrates.

13. The semiconductor package of claim 10, wherein the second, third, fourth, and fifth substrates define an enclosure around the one or more dies.

14. The semiconductor package of claim 13, further comprising a mold material within the enclosure and at least partially covering the one or more dies, first surface, second surface, third surface, fourth surface, fifth surface, and wire bonds.

15. The semiconductor package of claim 10, wherein the wire bond is a first wire bond, the package further comprising:

a plurality of second wire bonds extending from the third surface to at least one of (a) the first surface of the first substrate or (b) the outermost surface of the outermost die;

a plurality of third wire bonds extending from the fourth surface to at least one of (a) the first surface of the first substrate or (b) the outermost surface of the outermost die;

a plurality of fourth wire bonds extending from the fifth surface to at least one of (a) the first surface of the first substrate or (b) the outermost surface of the outermost die.

16. The semiconductor package of claim 10, wherein the first, second, third, fourth, and fifth substrates each include a first side facing the one or more dies and a second side substantially opposite the first side and facing away from the one or more dies, wherein the second side of each of the first, second, third, fourth, and fifth substrates includes external connection sites having exposed conductive material.

17. A semiconductor assembly, comprising:

a plurality of semiconductor packages, wherein each semiconductor package is coupled to one or more adjacent semiconductor packages and includes:

a base substrate having a base surface;

a stack of dies over the substrate surface, wherein an outermost die of the stack of dies includes an outermost surface;

a side substrate over the base substrate, wherein the side substrate includes (a) a side surface orthogonal to the base surface of the base substrate and the outermost surface of the outermost die, and (b) an outer surface opposite the side surface and including a conductive material to be electrically coupled to one of the adjacent semiconductor packages;

a plurality of interconnects extending from the side surface of the side substrate to (a) the base surface of the base substrate or (b) the outermost surface of the outermost die, wherein the interconnects electrically couple the one or more dies to the side substrate; and

a mold material encapsulating the outermost die and the interconnects and covering at least a portion of the side surface.

18. The semiconductor assembly of claim 17, wherein the side substrate is a first side substrate, the assembly further comprising a second side substrate, a third side substrate, and a fourth side substrate, and wherein the first, second, third, and fourth side substrates are attached to the base substrate and form an enclosure therein.

19. The semiconductor assembly of claim 17, wherein the semiconductor assembly includes at least three semiconductor packages arranged in a 1 x 3 arrangement.

20. The semiconductor assembly of claim 17 wherein the adjacent semiconductor packages are directly coupled to each other using a friction fit and/or alignment pins.

21. The semiconductor assembly of claim 17, wherein a Dual Inline Memory Module (DIMM) comprises the semiconductor assembly.

22. The semiconductor assembly of claim 17, wherein the conductive material includes a contact pad or an array of contact pads.

23. A semiconductor package, comprising:

a substrate having a base surface;

a plurality of dies over the substrate and attached to the surface;

a mold material over the substrate and encapsulating the die, wherein the mold material includes a side surface substantially perpendicular to the base surface; and

a plurality of conductive fingers positioned at least partially between individual dies, wherein the conductive fingers extend away from the dies to corresponding side surfaces of the mold material, wherein the conductive fingers each include an end that is at least partially exposed through the mold material.

24. The semiconductor package of claim 23, wherein the individual dies are electrically coupled to each other via interconnects extending between the adjacent dies.

25. The semiconductor package of claim 23, wherein the individual dies are electrically coupled to one another via interconnects that (a) extend from adjacent conductive fingers and (b) extend at least partially through the mold material.

26. The semiconductor package of claim 23, wherein the conductive fingers contact and electrically couple adjacent dies to each other such that the adjacent dies are vertically separated from each other by individual conductive fingers.

27. The semiconductor package of claim 23, wherein the end of each of the conductive fingers is electrically coupled to an external package.

28. The semiconductor package of claim 23, wherein the semiconductor package does not include wire bonds.

29. A method of manufacturing a semiconductor package, the method comprising:

attaching a first substrate to a second substrate, wherein a first surface of the first substrate is substantially orthogonal to a second surface of the second substrate;

disposing a stack of dies over the first surface of the first substrate, wherein the stack of dies is electrically coupled to the first substrate; and

electrically coupling the die stack to the second substrate by forming interconnects that extend from the second surface of the second substrate to (a) the first surface of the first substrate or (b) a third surface of the die stack.

30. The method of claim 29, further comprising attaching third, fourth, and fifth substrates to the first substrate such that the second, third, fourth, and fifth substrates define an enclosure around the stack of dies.

31. The method of claim 29, further comprising at least partially encapsulating the first substrate, the second substrate, and the die stack with a mold material.

32. The method of claim 29, further comprising forming a ball grid array over a third surface of the second substrate, wherein the third surface is opposite the second surface of the second substrate and faces away from the die stack, and wherein the ball grid array is electrically coupled to an adjacent semiconductor package.

33. A method of forming a semiconductor assembly including a plurality of semiconductor packages, the method comprising:

electrically coupling a base substrate to a plurality of dies disposed over a base surface of the base substrate;

electrically coupling a side substrate to the die by providing interconnects extending from side surfaces of the side substrate to (a) the base surface of the base substrate or (b) a die surface of the die, wherein the base surface and the die surface are each orthogonal to the first surface; and

the side substrate is electrically coupled to an adjacent semiconductor package to form a semiconductor assembly.

34. The method of claim 33, wherein:

the side surface is at a first side of the side substrate,

the side substrate includes a second side opposite the first side, an

Electrically coupling the side substrate includes electrically coupling the side substrate to the adjacent semiconductor package via a conductive material at the second side of the side substrate.

35. The method of claim 33, wherein:

the side surface is at a first side of the side substrate,

the side substrate includes a second side opposite the first side and having a first array of solder connections, an

Electrically coupling the side substrate includes electrically coupling the first array of solder connections to a second array of solder connections on the adjacent semiconductor package.

36. The method of claim 35, wherein the first and second arrays of solder connections each comprise a ball grid array, and wherein the first array is arranged in a first pattern and the second array is arranged in a second pattern that is complementary to the first pattern.

37. The method of claim 35, wherein the first and second arrays of solder connections each include a bump and dimple arrangement, and wherein the first array is arranged in a first pattern and the second array is arranged in a second pattern that is complementary to the first pattern.

Technical Field

The present disclosure relates to packaging semiconductor devices, such as memories and processors, and several embodiments relate to semiconductor assemblies using modular edge stacking.

Background

Packaged semiconductor dies, including memory dies, microprocessor dies, and interface dies, typically include a semiconductor die mounted on a substrate and encapsulated in a plastic protective cover. The die includes functional means, such as memory cells, processor circuitry, and interconnect circuitry, and bond pads electrically connected to the functional means. The bond pads are typically electrically connected to external terminals that extend outside the protective covering to allow the die to be connected to a bus, circuit, or other higher-order circuitry.

Semiconductor die manufacturers are facing increasing pressure to continually reduce the size of die packages to fit the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the "footprint" of the package) is to stack multiple semiconductor dies vertically on top of each other in a single package. However, stacking multiple dies increases the vertical profile of the device, requiring the individual dies to be substantially thinned to achieve a vertically compact size. Moreover, the stacking of multiple dies can increase the probability of device failure and result in higher costs associated with longer manufacturing and testing times.

Fig. 1 illustrates a conventional system 10 including a plurality of semiconductor stack assemblies. As shown, the system 10 includes Printed Circuit Boards (PCBs) 15 arranged in dual in-line memory module (DIMM) slots and separated from each other by a given centerline-to-centerline spacing (i.e., -7.6 mm). The semiconductor packages 12 are attached to each of the PCBs 15 in a stacked arrangement. In particular, the bottom portion of each semiconductor package 12 is attached to opposite sides of the PCB 15 via solder balls 13. The conventional system 10 has limited space (i.e., -1 mm) between the semiconductor packages 12 on adjacent DIMM slots, which can limit the airflow between the semiconductor packages 12 required for thermal control and limit the performance of the package. Accordingly, there is a need for other methods of providing semiconductor devices having a smaller footprint while still maintaining sufficient functional capacity to meet operating parameters.

Drawings

Fig. 1 is a schematic side view of a semiconductor device assembly according to the prior art.

Fig. 2A is a schematic top view of a semiconductor device package taken along line 2A-2A of fig. 2B and configured in accordance with an embodiment of the invention.

Figure 2B is a schematic cross-sectional view of the semiconductor device package shown in figure 2A taken along line 2B-2B of figure 2A and configured in accordance with an embodiment of the invention.

Fig. 3A is a schematic top view of a semiconductor device package taken along line 3A-3A of fig. 3B and configured in accordance with an embodiment of the invention.

Figure 3B is a schematic cross-sectional view of the semiconductor device package shown in figure 3A taken along line 3B-3B of figure 3A and configured in accordance with an embodiment of the present invention.

Fig. 4A-4D are schematic diagrams illustrating a method of forming a semiconductor device package configured according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of a semiconductor device package configured in accordance with an embodiment of the invention.

Figures 6A-6C and 7A-7D are schematic diagrams of semiconductor device assemblies configured according to embodiments of the invention.

Figure 8 is a schematic diagram of a system including a semiconductor assembly configured in accordance with an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are discussed to provide a thorough and enabling description of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with semiconductor devices are not shown or described in detail to avoid obscuring other aspects of the invention. In general, it should be understood that various other devices, systems, and methods in addition to the specific embodiments disclosed herein may be within the scope of the invention.

As discussed above, semiconductor packages having smaller footprints while also maintaining sufficient processing power are continually being designed. Accordingly, several embodiments of semiconductor packages according to the present invention may be electrically coupled to one another using modular edge stacking techniques to form high density modules. In some embodiments, each semiconductor package includes a first substrate having a first surface, a second substrate having a second surface orthogonal to the first surface, and one or more dies disposed over the first surface of the first substrate. The semiconductor package further includes one or more interconnects extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate or (b) an outermost surface of the one or more dies. A semiconductor package may be electrically coupled to an adjacent semiconductor package via external connection sites at an outer surface (e.g., edge) of the first substrate and/or the second substrate.

Fig. 2A is a schematic top view of the semiconductor device package 100 ("package 100") taken along line 2A-2A of fig. 2B, and fig. 2B is a schematic cross-sectional view of the semiconductor device assembly 100 taken along line 2B-2B of fig. 2A. Referring to fig. 2A and 2B together, the package 100 includes a base substrate 101 having a base surface 111, a stack of dies 105a (collectively "die stack 105") disposed above the base surface 111, and one or more side substrates 102A-d also disposed above the base surface 111. The base substrate 101 and the side substrates 102 a-d may include redistribution structures, interposers, dielectric spacers, additional semiconductor dies (e.g., logic dies), or other suitable substrates. Each side substrate 102 a-d may include a first end (e.g., bottom portion) attached to base substrate 101 via a first bonding material 120 (e.g., an adhesive paste, an adhesive element, or a die-attach tape/film), and a second end (e.g., side portion) attached to an adjacent side substrate via a second bonding material 117 a-d (e.g., an adhesive paste, an adhesive element, or a die-attach tape/film). The side substrates 102 a-d may at least partially surround and form an enclosure around the die stack 105. The outermost die 105a of the die stack 105 can include an outermost surface 119 facing in a direction generally away from the substrate surface 111. The die stack 105 may be attached to the base surface 111 of the base substrate 101 via an underfill material 124 (e.g., an adhesive paste or an adhesive element). In some embodiments, the die stack 105 may be electrically coupled to the base substrate 101 via circuitry.

Each of the side substrates 102 a-d extends vertically away from the base surface 111 of the base substrate 101 and includes (a) a respective first side 107 a-d facing the die stack 105 and having a respective side surface 103 a-d, (b) a respective second side 108 a-d opposite the first side, and (c) a respective outermost edge 104 a-d. For example, the side substrate 102a includes a first side 107a having a side surface 103a, a second side 108a opposite the first side 107a, and an outermost edge 104 a. In this embodiment, each of the side surfaces 103 a-d of the side substrates 102 a-d are substantially orthogonal to (a) the outermost surface 119 of the die stack 105 and (b) the base surface 111 of the base substrate 101, respectively. As shown in fig. 2B, the die stack 105 may be separated from the substrate surface 111 by a first distance (d)₁) And the outermost edges 104 a-d may be separated from the substrate surface 111 by greater than a first distance (d)₁) Second distance (d)₂)。

Each of the side substrates 102 a-d can be electrically coupled directly to the die stack 105 via a plurality of interconnects 115 a-d (e.g., wire bonds or conductive material) extending from respective bond pads 110 a-d on respective side surfaces 103 a-d of the respective side substrates 102 a-d to respective bond pads 114 a-d on an outermost surface 119 of the outermost die 105 a. For example, a plurality of wire bonds 115a may extend from bond pads 110a on side surface 103a to bond pads 114a on outermost surface 119 of outermost die 105 a. In such embodiments, the die stack 105 is electrically coupled to the side substrates 102 a-d and the base substrate 101. The second sides 108 a-d of the respective side substrates 102A-d may each include a respective conductive material 140 a-d, the conductive materials 140 a-d may include pads (e.g., contact pads) as shown in fig. 2A and 2B, or an array of conductive materials (e.g., a contact point array or a ball grid array). The conductive materials 140 a-d may be respective bond pads 110 a-d electrically coupled to respective first sides 107 a-d of respective side substrates 102 a-d via circuitry, and thus may electrically couple the die stack 105 and/or the base substrate 101 to an external package.

Individual semiconductor dies 105 a-h can include one or more through-substrate vias 122 (TSVs) extending at least partially through the dies 105 a-h, and conductive traces 118 a-b over outermost surfaces of the semiconductor dies 105 a-h. The individual semiconductor dies 105 a-h may be electrically coupled to neighboring dies via one or more interconnects 116. Semiconductor dies 105 a-h may include integrated circuits or components, data storage elements, processing components, and/or other components fabricated on a semiconductor substrate. For example, semiconductor dies 105 a-h may include integrated memory circuits and/or logic circuits, which may include various types of semiconductor components and functional components, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuitry, imaging components, and/or other semiconductor components. In some embodiments, semiconductor dies 105 a-h can be the same (e.g., memory dies are manufactured to have the same design and specifications), but in other embodiments semiconductor dies 105 a-h can be different from one another (e.g., different types of memory dies or combinations of controller, logic, and/or memory dies).

The conductive materials 140 a-d may be formed from one or more of copper, nickel, solder (e.g., SnAg-based solder, solder balls), conductor-filled epoxy, and/or other conductive materials. As shown in fig. 2A and 2B, the conductive material 140 a-d may cover a majority of the surface area at the second sides 108 a-d of the side substrates 102A-d, and may be formed to have a similar or complementary arrangement to corresponding conductive material on other packages. In some embodiments, the side substrates 102 a-d and the respective conductive materials 140 a-d positioned thereon may be homogeneous (i.e., identical), which may help ensure that the package 100 may be electrically coupled to an adjacent package 100. Although the embodiment shown in fig. 2A and 2B includes a layer of conductive material, in some embodiments, the conductive material 140 a-d may comprise a ball grid array or other arrangement.

The package 100 may further include a mold material or molding material 125 over the base substrate 101 and the die stack 105. The mold material 125 may be formed of a resin, an epoxy, a silicone-based material, a polyimide, and/or other suitable resins used or known in the art. As shown in fig. 2A and 2B, the mold material 125 may be formed within an enclosure defined by the side substrates 102A-d, and may at least partially contact the die stack 105, the side substrates 102A-d, the base substrate 101, and the plurality of wire bonds 115 a-d, thereby encapsulating (e.g., sealing) and protecting one or more of such components from contaminants and/or physical damage. The mold material 125 can include an outermost surface 126 that is substantially coplanar with outermost edges 104 a-d of the respective side substrates 102 a-d such that the outermost edges 104 a-d are not covered by the mold material 125. In some embodiments, the outermost surface 126 of mold material 125 may be slightly higher than outermost edges 104 a-d, such that the outermost surface 126 of mold material 125 extends over and covers outermost edges 104 a-d. Further, in some embodiments, the mold material 125 may extend over the second sides 108 a-d of the respective side substrates 102 a-d such that at least a portion of the outer surface at the second sides 108 a-d is covered. In such embodiments, the conductive materials 140 a-d may be exposed through the mold material 125 to remain operable to electrically couple the package 100 to external connection sites and the package.

Fig. 3A is a schematic top view of a semiconductor device package 200 ("package 200") taken along line 3A-3A of fig. 3B, and fig. 3B is a schematic cross-sectional view of the package 200 taken along line 3B-3B of fig. 3A. The package 200 includes components similar to those of the package 100 shown in fig. 2A and 2B, except that in fig. 3A and 3B the side substrates 102A-d are directly electrically coupled to the base substrate 101. In particular, each of the side substrates 102 a-d may be directly electrically coupled to the base substrate 101 via a plurality of respective interconnects 121 a-d extending from the bond pads 131 a-131 d on the respective side surfaces 103 a-d of the respective side substrates 102 a-d to the respective bond pads 130 a-d on the base surface 111 of the base substrate 101. In such embodiments, side substrates 102 a-d may be directly electrically coupled to base substrate 101, and indirectly electrically coupled to die stack 105 via base substrate 101.

Although fig. 2A-3B include four side substrates (e.g., 102A-d) disposed over base substrate 101 to form an enclosed enclosure, in some embodiments, fewer than four side substrates may be included. For example, the package 100 may include only a single side substrate (e.g., side substrate 102a), two side substrates (e.g., side substrates 102a, b or 102a, c), or three side substrates (e.g., side substrates 102a, b, c). In such embodiments, the mold material 125 may form one or more side surfaces of the package 100 or 200.

Fig. 4A-4D are schematic diagrams illustrating a method of forming a semiconductor device package ("package 400") configured according to an embodiment of the invention. Referring first to fig. 4A, the method may include attaching one or more of the side substrates 102 a-d to one another via a second bonding material 117 a-d to form a side substrate assembly 145 having an opening therethrough. The second bonding materials 117a to d may extend over substantially the entire end portion of the corresponding side substrate, or over less than the entire end portion of the corresponding side substrate. As shown in fig. 4A, each side substrate overlaps a portion of the side substrate attached thereto. In other embodiments, the side substrates 102 a-d may be attached to one another such that there is no overlap. Each side substrate 102 a-d may be homogeneous or the same as the other side substrates 102 a-d, or may have different dimensions, depending on the target footprint and/or application required for the package. Fig. 4A further shows the side substrate assembly 145 attached to the base substrate 101 via the first bonding material 120. The first bonding material 120 may be formed over substantially the entire base surface 111 of the base substrate 101, or over only a portion of the base surface 111.

Referring next to fig. 4B, fabrication of the package 400 continues by disposing the die stack 105 over the base substrate 101 and within the enclosure defined by the side substrates 102 a-d. As previously mentioned with reference to fig. 2A-3B, the die stack 105 may be attached to the base substrate 101 via an underfill material 124. Die stack 105 may be formed as a discrete package prior to attachment to base substrate 101, or die stack 105 may be formed by sequentially stacking individual dies 105 a-h within an enclosure. In some embodiments, disposing the die stack 105 over the base substrate 101 can occur after forming the side substrate assembly 145.

Fig. 4C shows the package 400 after the die stack 105 is electrically coupled to one or more of the side substrates 102 a-d via interconnects 115 a-d that extend from bond pads 114 a-d on an outermost die 105a of the die stack 105 to respective bond pads 110 a-d on respective side substrates 102 a-d. As previously mentioned, electrically coupling side substrates 102 a-d to die stack 105 may also indirectly electrically couple side substrates 102 a-d to base substrate 101. For ease of illustration, fig. 4C optionally includes an additional plurality of interconnects 121 a-d (only 121a and 121b are shown) electrically coupling the side substrates 102 a-d to the base substrate 101. In a preferred embodiment, the package 400 will include interconnects 115 a-d or interconnects 121 a-d, but not both.

Fig. 4D shows the package 400 after disposing the mold material 125 on the base surface 111 of the base substrate 101, with the mold material 125 in contact with the die stack 105, the interconnects 115 a-D (or the interconnects 121 a-D), and portions of the side substrates 102 a-D. Once deposited, the mold material 125 may be cured by UV light, chemical hardeners, heat, or other suitable curing methods used or known in the art.

Fig. 5 is a schematic cross-sectional view of a semiconductor device package 500 ("package 500") configured in accordance with an embodiment of the present technique. The package 500 includes features substantially similar to the features of the packages 100 and 200 previously described. For example, package 500 includes base substrate 101, die stack 105 attached to the base substrate via underfill material 124, and mold material 125 encapsulating at least a portion of die stack 105 and base substrate 101. Notably, in this embodiment, the package 500 does not include side substrates (e.g., 102 a-d). Thus, the mold material 125 may form the outermost edge 505 and the outermost surface 526. The package 500 further includes a plurality of conductive layers formed at least partially between individual, adjacent dies 105 a-h of the die stack 105. In some embodiments, as shown on the left side of the package 500, the conductive layer may include conductive fingers 510, the conductive fingers 510 being positioned over individual dies 105 a-h such that individual, adjacent dies 105 a-h are separated from each other by the conductive fingers 510. The conductive fingers 510 may extend horizontally from the die stack 105 through the mold material 125 such that ends 511 of the conductive fingers 510 are exposed at the outermost edges 505. The ends 511 of the conductive fingers 510 may be electrically coupled to external connection sites. In other embodiments, as shown on the right side of the package 500, the conductive layer may include conductive fingers 515, the conductive fingers 515 being positioned over the individual dies 105 a-h and extending horizontally from the die stack 105 through the mold material 125 such that ends 516 of the conductive fingers 515 are exposed through the side surfaces 505 a. The ends 516 of the conductive fingers 515 may be electrically coupled to external connection sites. Individual, adjacent dies can be electrically coupled to each other via interconnects 520 that extend vertically through the mold material 125 and from a first semiconductor die (individual die 105a) to an adjacent semiconductor die (e.g., individual die 105 b). In the embodiment shown in fig. 5, the package 500 does not include wire bonds. However, in other embodiments, the package 500 may include wire bonds extending from the die stack 105 and/or the individual dies 105 a-h to an external package, for example.

Fig. 6A-6C are schematic diagrams of semiconductor device packages and assemblies. More particularly, fig. 6A corresponds to one individual semiconductor package 600 ("package 600") formed in accordance with the previously described embodiments (e.g., packages 100, 200, and/or 500), fig. 6B corresponds to a plurality of semiconductor device assemblies 620 ("assemblies 620") arranged as stacked, modularly configured packages 600 in DIMM slots, and fig. 6C corresponds to semiconductor device assemblies ("assemblies 640") arranged as stacked, modularly configured packages 600. The invention is not intended to be limited to the embodiments and details (e.g., dimensions) shown in fig. 6A-6C. Rather, such embodiments and details are intended only to enhance an understanding of the present invention by one of ordinary skill in the relevant art.

As shown in fig. 6A, the package 600 includes a base substrate 101 attached to one or more of the side substrates 102 a-d, wherein the side substrates 102 a-d each include a conductive material 610 (e.g., conductive material 140 a-d or conductive fingers 510, 515) on an outer surface of the side substrates 102 a-d. In the embodiment shown in fig. 6A, the package 600 includes a height of 10mm, a width of 11mm, and a thickness of 2 mm. However, other embodiments may include different dimensions to form packages and/or assemblies suitable for the desired application.

Fig. 6B illustrates a plurality of assemblies 620 of stacked packages 600 arranged adjacently and separated from each other. The assembly 620 may include a protective cover layer 602 surrounding the assembly 620 to protect it from physical damage. The protective cover 602 may also serve as a heat spreader to better (e.g., more evenly) distribute heat in the individual packages 600. Fig. 6B helps illustrate several advantages of the present invention over conventional techniques. For example, in the embodiment shown, each assembly 620 may itself be positioned into a DIMM slot without first being attached to a PCB that is then inserted into the DIMM slot. As such, and assuming a spacing of approximately 7.6mm between adjacent slots consistent with conventional techniques, the present invention may allow for a greater spacing (e.g., -4.5 mm) between adjacent assemblies 620, allowing for greater airflow between assemblies 620 than conventional techniques, and thereby cooling (e.g., via convection) assemblies 620 at a faster rate. Another advantage of the present invention is the reduced time and cost associated with manufacturing the assembly to be installed in the DIMM slot. For example, the present invention removes at least one manufacturing processing step from conventional methods for forming packages (e.g., attaching a package to a PCB prior to inserting the PCB into a DIMM slot).

Fig. 6C illustrates an assembly 640 of individual packages 600 in a different arrangement. As shown, the assembly 640 includes a 2 x 4 arrangement of individual packages 600. In other embodiments, the assembly 640 may include different arrangements (e.g., 1 × 3, 1 × 6, 3 × 3, 3 × 6, etc.) depending on the desired application.

Fig. 7A-7C illustrate schematic diagrams of semiconductor device packages attached and electrically coupled to each other. As previously mentioned with reference to fig. 2A-6, an individual package (e.g., packages 100, 200, 500, and/or 600) may include conductive material (e.g., conductive material 140 a-d or conductive fingers 510, 515) at an outer surface of a substrate (e.g., base substrate 101 or side substrates 102A-d) of the package. The conductive material may electrically couple the individual packages to one another. Fig. 7A-7C show embodiments of arrangements of conductive material that can be used to electrically couple individual packages to one another. As shown in fig. 7A, a bump 705 (e.g., solder pin) and dimple (divot)706 (e.g., pad) arrangement may be used, where an array of bumps 705 on a first package 700 is configured to be placed in contact with corresponding dimples 706 on a second package 700. The bumps 705 and dimples 706 may protrude from the outer surface of the respective packages and create an electrical connection therebetween when the packages are moved toward each other and the bumps 705 and dimples 706 are in contact with each other. In some embodiments, the dimples 706 can be mechanically coupled to springs or spring-like elements that allow any positional offset between the bumps 705 and the dimples 706 to be absorbed by the dimples 706. The assembly may further include one or more locking or alignment pins 710 that mechanically couple the packages 700 to one another using a friction fit.

Fig. 7B-7D include functionality similar to that described for fig. 7A, but utilize different mechanical coupling arrangements. For example, fig. 7B utilizes a tab 712 and slot 715 arrangement, where the tab on the first package is shaped such that it is complementary to the corresponding slot 715 on the second package. The conductive material exposed at portions (e.g., side portions) of the tab 712 is positioned to contact the conductive material at corresponding portions of the slot 715 to create an electrical connection therebetween. In some embodiments, the conductive material exposed at the tab 712 and slot 715 may correspond to the conductive fingers 510, 515 previously described with reference to fig. 5.

Fig. 7C utilizes yet another arrangement for creating a lap joint 720 between a first package and a second package. In this arrangement, the overhang portion 721b from the first package can form an electrical connection with the extended lip portion 721a from the second package. Each of the overhang portion 721b and the lip portion 721a may include a ball grid array or similar arrangement of conductive material to ensure robust electrical connection. In addition to bonding individual packages to one another, the lap joint 720 and overhang-lip arrangement can be used to bond packages to DIMM slots or sockets 730. As shown in fig. 7D, the slot or receptacle 730 may include an engagement portion 725 that is complementary to the lip portion 721a (or overhang portion 721b) of the package, thereby allowing the assembly of the package 700 to be directly connected to a motherboard or backplane. Once connected, the package may be further secured to the motherboard with additional latches.

Any of the semiconductor devices described above with reference to fig. 2A-7C may be incorporated into any of a large number of larger and/or more complex systems, a representative example of which is the system 890 schematically shown in fig. 8. The system 890 may include a semiconductor device 800 ("device 800") (e.g., a semiconductor package or assembly), a power supply 892, a driver 894, a processor 896, and/or other subsystems or components 898. The device 800 may include means substantially similar to the devices described above. The resulting system 890 may perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Thus, a representative system 890 may include (but is not limited to): handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of system 890 may be housed in a single unit or distributed across multiple interconnected units (e.g., over a communication network). The components of system 890 may also include remote devices and any of a wide variety of computer-readable media.

It is not intended to be exhaustive or to limit the invention to the precise form disclosed herein. As one of ordinary skill in the relevant art will recognize, although specific embodiments are disclosed herein for purposes of illustration, various equivalent modifications are possible without departing from the invention. In some instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Although the steps of a method may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, particular aspects of the disclosure disclosed in the context of particular embodiments may be combined or eliminated in other embodiments. Moreover, while advantages associated with particular embodiments of the invention may be disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the invention. Accordingly, the present disclosure and associated techniques may encompass other embodiments not explicitly shown or described herein, and the disclosure is not limited, except as by the appended claims.

Throughout this disclosure, the singular terms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. Similarly, unless the word "or" is expressly limited to mean only a single item to the exclusion of other items in respect of a list of two or more items, the use of "or" in this list should be construed as including: (a) any single item in the list; (b) all items in the list; or (c) any combination of items in the list. Moreover, the terms "comprising," "including," and "having" are used throughout to mean including at least the recited means, such that any greater number of the same means and/or additional types of other means is not excluded. Reference herein to "one embodiment," "an embodiment," "some embodiments," or similar expressions means that a particular feature, structure, operation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, the various particular components, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.