阅读说明：本技术 一种tft基板的连接孔制作方法及tft基板 (TFT substrate connecting hole manufacturing method and TFT substrate ) 是由 张攀 陈飞 王金宝 程军 王磊 于 2020-06-12 设计创作，主要内容包括：本发明公开了一种TFT基板的连接孔制作方法,包括如下步骤：步骤1：在衬底基板上依次制作栅图案层、栅绝缘层、硅岛图案层、源漏图案层和钝化层；步骤2：依次对所述钝化层和栅绝缘层进行刻蚀,以使所述钝化层形成连接孔,所述连接孔部分位于所述源漏图案层的漏极上方,以将所述漏极露出,部分位于所述漏极外围,以将位于所述漏极外围处的栅绝缘层露出,以及使所述栅绝缘层在所述漏极外围处形成有与所述连接孔连通的凹槽。该方法可在制作完所述TFT基板的连接孔后,避免后续制程中的环境水汽沉积而与漏极相接触,可防止漏极被水汽腐蚀。本发明还公开了一种TFT基板。(The invention discloses a method for manufacturing a connecting hole of a TFT substrate, which comprises the following steps: step 1: sequentially manufacturing a gate pattern layer, a gate insulating layer, a silicon island pattern layer, a source drain pattern layer and a passivation layer on a substrate; step 2: and sequentially etching the passivation layer and the gate insulating layer to form a connecting hole in the passivation layer, wherein the connecting hole is partially positioned above the drain electrode of the source/drain pattern layer to expose the drain electrode, partially positioned on the periphery of the drain electrode to expose the gate insulating layer positioned on the periphery of the drain electrode, and a groove communicated with the connecting hole is formed in the periphery of the drain electrode in the gate insulating layer. The method can prevent the drain electrode from being contacted with the drain electrode due to the deposition of the environmental vapor in the subsequent processing after the connecting hole of the TFT substrate is manufactured, and can prevent the drain electrode from being corroded by the vapor. The invention also discloses a TFT substrate.)

1. A method for manufacturing a connecting hole of a TFT substrate is characterized by comprising the following steps:

step 1: sequentially manufacturing a gate pattern layer, a gate insulating layer, a silicon island pattern layer, a source drain pattern layer and a passivation layer on a substrate;

step 2: and sequentially etching the passivation layer and the gate insulating layer to form a connecting hole in the passivation layer, wherein the connecting hole is partially positioned above the drain electrode of the source/drain pattern layer to expose the drain electrode, partially positioned on the periphery of the drain electrode to expose the gate insulating layer positioned on the periphery of the drain electrode, and a groove communicated with the connecting hole is formed in the periphery of the drain electrode in the gate insulating layer.

2. The method for forming a connection hole of a TFT substrate as set forth in claim 1, wherein the step 2 comprises the steps of:

step 2.1: manufacturing a layer of photoresist on the passivation layer, and exposing and developing the photoresist to enable the photoresist to form a hollowed-out region, wherein the hollowed-out region is partially positioned above the drain electrode to expose a part of the passivation layer positioned above the drain electrode, and is partially positioned above the periphery of the drain electrode to expose a part of the passivation layer positioned at the periphery of the drain electrode;

step 2.2: etching the passivation layer exposed from the hollow area to form the connecting hole on the passivation layer, and exposing the gate insulating layer positioned below the periphery of the drain electrode from the connecting hole;

step 2.3: etching the gate insulating layer exposed from the connecting hole to form a groove on the gate insulating layer, wherein the groove is communicated with the connecting hole at the periphery of the drain electrode;

step 2.4: the remaining photoresist is stripped.

3. The method of claim 1 or 2, wherein the portion of the connection hole above the drain electrode is 1/2-3/4 of the total area of the connection hole, and the portion of the connection hole at the periphery of the drain electrode is 1/4-1/2 of the total area of the connection hole.

4. The method for forming a connection hole of a TFT substrate as set forth in claim 1 or 2, further comprising, after the step 2, the steps of:

and step 3: and manufacturing a pixel pattern layer on the passivation layer, wherein the pixel pattern layer is connected with the drain electrode at the connecting hole.

5. The method for forming a connection hole of a TFT substrate as claimed in claim 2, wherein the gate insulating layer and the passivation layer are removed by the same etching solution.

6. The method for forming a connection hole in a TFT substrate according to claim 5, wherein the gate insulating layer and the passivation layer are made of the same material or the same material.

7. The method for forming a connection hole in a TFT substrate according to claim 6, wherein the gate insulating layer and the passivation layer are formed of a non-metal oxide, a non-metal nitride or a non-metal oxynitride.

8. A TFT base plate comprises a substrate base plate, and a grid pattern layer, a grid insulating layer, a silicon island pattern layer, a source drain pattern layer and a passivation layer which are sequentially manufactured on the substrate base plate, and is characterized in that a connecting hole is formed in the passivation layer, the connecting hole is partially positioned above a drain electrode of the source drain pattern layer so as to expose the drain electrode, and the connecting hole is partially positioned on the periphery of the drain electrode; and the grid insulating layer is provided with a groove communicated with the connecting hole at the periphery of the drain electrode.

9. The TFT substrate according to claim 8, wherein the portion of the connection hole located above the drain occupies 1/2-3/4 of the total area of the connection hole, and the portion of the connection hole located at the periphery of the drain occupies 1/4-1/2 of the total area of the connection hole.

10. The TFT substrate of claim 8 or 9, further comprising a pixel pattern layer formed on the passivation layer, the pixel pattern layer being connected to the drain electrode at the connection hole.

Technical Field

The invention relates to a TFT (thin film transistor) process, in particular to a method for manufacturing a connecting hole of a TFT substrate and the TFT substrate.

Background

As shown in fig. 1 and 2, in the conventional TFT substrate, a connection hole 21 ' needs to be formed in a passivation layer 2 ' to expose a drain electrode 1 ' of a source/drain pattern layer from the connection hole 21 ', and then a pixel pattern layer located on the passivation layer 2 ' is connected to the drain electrode 1 ' at the connection hole 21 '. However, after the connection hole 21 'is formed, the ambient moisture in the subsequent process is deposited in the connection hole 21' and contacts the drain electrode 1 ', so that the drain electrode 1' is corroded by the moisture, and the product stability is affected.

Disclosure of Invention

In order to solve the above-mentioned defects of the prior art, the present invention provides a method for fabricating a connection hole of a TFT substrate, which can prevent the connection hole of the TFT substrate from contacting a drain electrode due to deposition of ambient water vapor in a subsequent process, and can prevent the drain electrode from being corroded by the water vapor.

The technical problem to be solved by the invention is realized by the following technical scheme:

a method for manufacturing a connecting hole of a TFT substrate comprises the following steps:

step 1: sequentially manufacturing a gate pattern layer, a gate insulating layer, a silicon island pattern layer, a source drain pattern layer and a passivation layer on a substrate;

step 2: and sequentially etching the passivation layer and the gate insulating layer to form a connecting hole in the passivation layer, wherein the connecting hole is partially positioned above the drain electrode of the source/drain pattern layer to expose the drain electrode, partially positioned on the periphery of the drain electrode to expose the gate insulating layer positioned on the periphery of the drain electrode, and a groove communicated with the connecting hole is formed in the periphery of the drain electrode in the gate insulating layer.

Further, step 2 comprises the following steps:

step 2.1: manufacturing a layer of photoresist on the passivation layer, and exposing and developing the photoresist to enable the photoresist to form a hollowed-out region, wherein the hollowed-out region is partially positioned above the drain electrode to expose a part of the passivation layer positioned above the drain electrode, and is partially positioned above the periphery of the drain electrode to expose a part of the passivation layer positioned at the periphery of the drain electrode;

step 2.2: etching the passivation layer exposed from the hollow area to form the connecting hole on the passivation layer, and exposing the gate insulating layer positioned below the periphery of the drain electrode from the connecting hole;

step 2.3: etching the gate insulating layer exposed from the connecting hole to form a groove on the gate insulating layer, wherein the groove is communicated with the connecting hole at the periphery of the drain electrode;

step 2.4: the remaining photoresist is stripped.

Further, the part of the connection hole above the drain electrode accounts for 1/2-3/4 of the total area of the connection hole, and the part of the connection hole at the periphery of the drain electrode accounts for 1/4-1/2 of the total area of the connection hole.

Further, after the step 2, the following steps are also included:

and step 3: and manufacturing a pixel pattern layer on the passivation layer, wherein the pixel pattern layer is connected with the drain electrode at the connecting hole.

Further, the gate insulating layer and the passivation layer may be removed by the same etching solution.

Further, the gate insulating layer and the passivation layer are made of the same material or the same material.

Further, the gate insulating layer and the passivation layer are made of non-metal oxide, non-metal nitride or non-metal oxynitride.

A TFT substrate comprises a substrate, and a gate pattern layer, a gate insulating layer, a silicon island pattern layer, a source drain pattern layer and a passivation layer which are sequentially manufactured on the substrate, wherein a connecting hole is formed in the passivation layer, the connecting hole is partially positioned above a drain electrode of the source drain pattern layer so as to expose the drain electrode, and the connecting hole is partially positioned on the periphery of the drain electrode; and the grid insulating layer is provided with a groove communicated with the connecting hole at the periphery of the drain electrode.

Further, the part of the connection hole above the drain electrode accounts for 1/2-3/4 of the total area of the connection hole, and the part of the connection hole at the periphery of the drain electrode accounts for 1/4-1/2 of the total area of the connection hole.

Further, the pixel structure also comprises a pixel pattern layer which is manufactured on the passivation layer and is connected with the drain electrode at the connecting hole.

The invention has the following beneficial effects: according to the method, the connecting hole of the passivation layer is partially formed in the periphery of the drain electrode, the gate insulating layer is continuously etched downwards after the connecting hole is etched, so that a groove communicated with the connecting hole is formed in the gate insulating layer, environmental water vapor in subsequent processes can be deposited in the groove through the connecting hole, the groove is located below the periphery of the drain electrode, the water vapor deposited in the groove cannot be in contact with the drain electrode, and the drain electrode can be prevented from being corroded by the water vapor.

Drawings

FIG. 1 is a schematic view of a conventional connection hole on a TFT substrate;

FIG. 2 is a schematic view of a conventional TFT substrate;

FIG. 3 is a block diagram illustrating the steps of a method for forming a connection hole according to the present invention;

FIG. 4 is a block diagram of a substep of step 2 of the connection hole making method shown in FIG. 3;

FIG. 5 is a schematic view of a TFT substrate provided in the present invention after photoresist exposure and development;

FIG. 6 is a schematic view of the TFT substrate provided by the present invention after the connection holes are formed;

fig. 7 is a schematic view of a TFT substrate provided in the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and examples.