阅读说明：本技术 一种延迟电路、时钟控制电路以及控制方法 (Delay circuit, clock control circuit and control method ) 是由 曲勃 陈金福 江立新 于 2019-03-18 设计创作，主要内容包括：本申请公开了一种延迟电路、时钟控制电路以及控制方法,延迟电路,包括藕接成一链的N级延迟单元,每级延迟单元包括四态门电路和反相电路,每级的四态门电路和反相电路的输入端相连,反相电路的另一输入端与下一级反相电路的输出相连；输入信号连接至第一级四态门电路、反相电路的输入端,并逐级通过四态门电路、反相电路延迟一定时间输出。(The application discloses a delay circuit, a clock control circuit and a control method, wherein the delay circuit comprises N stages of delay units which are coupled into a chain, each stage of delay unit comprises a four-state gate circuit and an inverter circuit, the four-state gate circuit of each stage is connected with the input end of the inverter circuit, and the other input end of the inverter circuit is connected with the output of the next stage of inverter circuit; the input signal is connected to the input ends of the first-stage four-state gate circuit and the inverting circuit and is output after being delayed for a certain time by the four-state gate circuit and the inverting circuit step by step.)

1. A kind of delay circuit, including coupling into N stages of delay units of a chain, each stage of delay units include four-state gate circuit and inverter circuit, the four-state gate circuit of each stage couples to input end of the inverter circuit, another input end of the inverter circuit couples to carry-out terminal of the next stage of inverter circuit; the input signal is connected to the input ends of the first-stage four-state gate circuit and the inverting circuit and is output after being delayed for a certain time by the four-state gate circuit and the inverting circuit step by step.

2. The delay circuit of claim 1, wherein the four-state gate circuit comprises an inverting unit, a pull-up unit, and a pull-down unit, and output terminals of the inverting unit, the pull-up unit, and the pull-down unit are connected and connected to an input terminal of an inverting unit of a next stage.

3. The delay circuit of claim 2, wherein the inverting unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor;

the grid electrodes of the first PMOS and the first NMOS transistor are connected to the output end of the last-stage inverting unit, and the drain electrodes of the first PMOS and the first NMOS transistor are connected to the input end of the next-stage inverting unit;

the source electrode of the first PMOS transistor is connected with the drain electrode of the second PMOS transistor, the source electrode of the second PMOS transistor is connected with the power supply, and the grid electrode of the second PMOS transistor is connected with the first control instruction;

and the source electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor, the source electrode of the second NMOS transistor is grounded, and the grid electrode of the second NMOS transistor is connected with a second control command.

4. The delay circuit of claim 2, wherein the pull-up unit comprises a third PMOS transistor having a gate connected to the third control command, a source connected to the power supply, and a drain connected to the input terminal of the next stage inverting unit.

5. The delay circuit of claim 2, wherein the pull-down unit comprises a third NMOS transistor having a gate connected to the fourth control command, a source connected to ground, and a drain connected to the input of the next stage inverting unit.

6. The delay circuit of claim 1, wherein the inverting circuit comprises a first inverter and a second inverter, the output ends of the first inverter and the second inverter are connected, the input end of the first inverter is connected with the input end of the same stage of four-state gate circuit, and the input end of the second inverter is connected with the output end of the next stage of second inverter; the first inverter is connected with the first control instruction, and the second inverter is connected with the second control instruction.

7. A clock control circuit using the delay circuit according to any one of claims 1 to 6, a clock signal and a mask signal being connected to an input terminal of the delay circuit through a logic gate; and the output end of the delay circuit is connected with the logic circuit module.

8. The clock control circuit of claim 7 wherein the clock signal is coupled to an input of an AND logic gate, the mask signal is coupled to the input of the AND logic gate through an inverter, and an output of the AND logic gate is coupled to the input of the delay circuit.

9. The clock control circuit of claim 7 wherein the clock signal and the mask signal are coupled to two inputs of an OR logic gate, respectively, an output of the OR logic gate being coupled to an input of the delay circuit.

10. A clock control method, comprising:

controlling the 0 th-M-1 th-level inverting unit to be opened, the pull-up unit and the pull-down unit to be closed, and controlling the M-level inverting unit to be closed;

controlling a first inverter of the 0 th to M-1 th stages to be closed and a second inverter to be opened, and controlling a first inverter of the M th stage to be opened and a second inverter to be closed;

the clock signal is sequentially output through the 0 th-M-1 stage inverting unit, the Mth stage first inverter and the M-1 th-0 th stage second inverter.

11. The clock control method of claim 10, wherein the mask signal is turned off, the pull-up unit and the pull-down unit of the mth stage are turned off, and the clock signal delays the output.

12. The clock control method of claim 10, wherein the mask signal is turned on, the pull-up unit of the mth stage is turned on, the pull-down unit is turned off, and the clock signal output is locked to the first level.

13. The clock control method of claim 10, wherein the mask signal is turned on, the pull-up unit of the mth stage is turned off, the pull-down unit is turned on, and the clock signal output is locked to the second level.

Technical Field

The present application relates to an integrated circuit, and more particularly but not exclusively to a delay circuit, a clock control circuit and a control method.

Background

Delay elements are building blocks of clock distribution networks in some integrated circuits and systems. Delay elements are used to define the time reference for the transmission (move) of data within these systems. Variable delay elements are inverter-based circuits used for fine, precise, and accurate pulse delay (or phase) control in high-speed digital integrated circuits. To achieve a wide range of delays or phase adjustments, the variable delay elements are implemented as inverter chains. The inverter chain is called a delay line. In many integrated circuits, delay lines are used in systems such as DLLs (delay locked loops), TDCs (time-to-digital converters), VCOs (voltage controlled oscillators), Pulse Width Control Loops (PWCLs), etc. In these applications, variable delay elements are used for accurate and precise pulse time references.

The existing delay line circuit structure has the following defects: generating glitches when the delay control signal is switched; the duty ratio loss of the output signal increases along with the increase of the number of the delay line stages; the input load increases linearly as the number of stages of the delay line increases.

Content of application

The application adopts a simple and feasible delay unit, avoids burrs when control signals are switched, and does not lose duty ratio.

In one embodiment, the application provides a delay circuit, which comprises N stages of delay units coupled into a chain, wherein each stage of delay unit comprises a four-state gate circuit and an inverter circuit, the four-state gate circuit of each stage is connected with an input end of the inverter circuit, and the other input end of the inverter circuit is connected with an output of the next stage of inverter circuit; the input signal is connected to the input ends of the first-stage four-state gate circuit and the inverting circuit and is output after being delayed for a certain time by the four-state gate circuit and the inverting circuit step by step.

In another embodiment, the present application provides a clock control circuit comprising the delay circuit of the above embodiment, a clock signal and a mask signal are connected to an input terminal of the delay circuit through a logic gate; and the output end of the delay circuit is connected with the logic circuit module.

In another embodiment, the present application provides a clock control method comprising: controlling the 0 th-M-1 th-level inverting unit to be opened, the pull-up unit and the pull-down unit to be closed, and controlling the M-level inverting unit to be closed; controlling a first inverter of the 0 th to M-1 th stages to be closed and a second inverter to be opened, and controlling a first inverter of the M th stage to be opened and a second inverter to be closed; the clock input signal is sequentially output through the 0 th-M-1 stage inverting unit, the Mth stage first inverter and the M-1 th-0 th stage second inverter.

Compared with the prior art, the application has at least the following beneficial effects:

1) each stage of delay unit is completely the same, so that the duty ratio loss of each stage of inverting circuit caused by process, voltage and temperature deviation can be completely compensated by the next stage of inverting circuit, and thus, no duty ratio loss exists.

2) The internal node voltage of the delay circuit becomes stable high-low level alternate distribution, no matter the control signal is switched to any one stage to be switched on or switched off, the internal node voltage of the delay line still becomes stable high-low level alternate distribution, and no burr signal is generated during switching.

Drawings

The present application is illustrated by way of example in the accompanying drawings. The drawings are to be regarded as illustrative in nature, and not as restrictive, and the scope of the application is defined by the appended claims.

Fig. 1 is a block diagram illustrating an embodiment of a delay circuit.

Figure 2 is a block diagram illustrating an embodiment of a four-state gate circuit.

FIG. 3 is a diagram illustrating an embodiment of a four-state gate.

Fig. 4 is a diagram showing an embodiment of a delay unit.

Fig. 5 is a diagram showing an embodiment of a clock control circuit.

Fig. 6 is a diagram showing another embodiment of the clock control circuit.

FIG. 7 is a flow diagram illustrating a method of clock control in one embodiment.

FIG. 8 is a flow chart illustrating a clock control method according to another embodiment.

FIG. 9 is a flow chart illustrating a clock control method according to another embodiment.

Detailed Description

Referring to fig. 1, the delay circuit includes N stages of delay units 10 coupled IN a chain, each stage of delay unit 10 includes four-state gate circuits 11 and an inverter circuit 12, the four-state gate circuit 11 of each stage is connected to an input terminal of the inverter circuit 12, another input terminal of the inverter circuit 12 is connected to an output terminal of the inverter circuit 12 of the next stage, an input signal IN is connected to the input terminals of the four-state gate circuit 11 and the inverter circuit 12 of the first stage, and an OUT is output by delaying for a certain time through the four-state gate circuits 11 and the inverter circuit 12 step by step.

Referring to fig. 2, the four-state gate 11 includes an inverting unit 111, a pull-up unit 112, and a pull-down unit 113, and outputs of the inverting unit 111, the pull-up unit 112, and the pull-down unit 113 are connected to an input of the inverting unit 111 of the next stage.

Referring to fig. 3, the inverting unit 111 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2;

the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to the output of the previous stage inverting unit 111, and the drains thereof are connected to the input of the next stage inverting unit 111;

the source of the first PMOS transistor P1 is connected with the drain of the second PMOS transistor P2, the source of the second PMOS transistor P2 is connected with the power supply, and the gate of the second PMOS transistor P2 is connected with the first control command enb;

the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is grounded, and the gate thereof is connected to a second control command en, wherein the first control command enb and the second control command en are a pair of inverted control signals.

The pull-up unit 112 includes a third PMOS transistor P3, the gate of which is connected to the third control command pu, the source of which is connected to the power supply, and the drain of which is connected to the input of the next stage inverting unit 111, and the third PMOS transistor P3 is turned on by the third control command pu, so as to pull up the output terminal of the four-state gate circuit 10 to a high level and stabilize it to the high level.

The pull-down unit 113 includes a third NMOS transistor N3, which has a gate connected to the fourth control command pd, a source grounded, and a drain connected to the input of the next stage inverting unit 111, and turns on the third NMOS transistor N3 according to the fourth control command pd, so as to pull down the output terminal of the four-state gate circuit 10 to a low level and stabilize the output terminal to a low level.

The four-state gate circuit 11 has at least three operating modes, which are respectively: the inverting unit 111 is opened, the pull-up unit 112 and the pull-down unit 113 are closed, and the output end signal is inverted; the inverting unit 111 and the pull-up unit 112 are opened, the pull-down unit 113 is closed, and the output end is constantly at a high level; the inversion unit 111 and the pull-down unit 113 are turned on, the pull-up unit 112 is turned off, and the output terminal is constantly at a low level. In the four-state gate circuit 11 of the present application, when the inverting unit 111, the pull-up unit 112, and the pull-down unit 113 are all turned off, the four-state gate circuit is in a high-impedance state, and has a high-impedance operation mode.

Referring to fig. 4, the inverter circuit 12 includes a first inverter 121 and a second inverter 122, output ends of the first inverter 121 and the second inverter 122 are connected, an input end of the first inverter 121 is connected to an input end of the same-stage inverting unit 111, an output end of the next-stage second inverter 122 is connected to an input end of the next-stage second inverter 122, the first inverter 121 is connected to a first control instruction enb, and the second inverter 122 is connected to a second control instruction en. The first inverter 121 and the second inverter 122 are respectively in an open state or a closed state (for example, the first inverter 121 is open, the second inverter 122 is closed, or the first inverter 121 is closed and the second inverter 122 is open), so that the signal of the four-state gate circuit 10 is selectively output through the inverter circuit 12.

IN another embodiment, referring to fig. 5, the present application further provides a clock control circuit 20, which includes the delay circuit 21 IN the above embodiment, the clock signal clk _ IN and the mask signal gate _ en are connected to the input terminal IN of the delay circuit 21 through an and logic gate 23, and the mask signal gate _ en is connected to the input terminal of the and logic gate 23 through an inverter 24; the output end OUT of the delay circuit 21 is connected with the logic circuit module 22. The delay circuit 21 further includes an input signal Vinit connected to an input terminal of the nth stage second inverting unit 122 and a control signal Code, as shown in fig. 4. The control signal Code is used to control the delay circuit 21 to output the lock time.

IN another embodiment, referring to fig. 6, the present application further provides a clock control circuit 30, which includes the delay circuit 21 IN the above embodiment, wherein the clock signal clk _ IN and the mask signal gate _ en are connected to the input terminal IN of the delay circuit 31 through an or logic gate 33; the output terminal OUT of the delay circuit 21 is connected to the logic circuit block 32. The delay circuit 31 further includes an input signal Vinit connected to an input terminal of the nth stage second inverting unit 122 and a control signal Code. The control signal Code is used to control the delay circuit 31 to output the lock time.

In another embodiment, with reference to fig. 4 and 7, the present application further provides a clock control method, including:

s110, controlling the 0 th-M-1 th-level inverting unit 111 to be opened, the pull-up unit 112 and the pull-down unit 113 to be closed, and controlling the Mth-level inverting unit 111, the pull-up unit 112 and the pull-down unit 113 to be closed, wherein the four-state gate circuit 11 inverts the input signal at the moment;

s120, controlling the first inverter 121 of the 0 th to M-1 th stages to be closed, the second inverter 122 to be opened, the first inverter 121 of the M th stage to be opened and the second inverter 122 to be closed, so that the input signal of the delay circuit sequentially passes through the M-1 stage four-state gate circuit and sequentially passes through the M-1 stage first inverter and the M-1 th to 0 th stage second inverter 122 to be output;

and S130, closing the shielding signal gate _ en, and delaying the clock signal for a certain time to output. The mask signal gate _ en is at a low level, the clock signal clk _ IN is input to the input terminal IN of the delay circuit, and the clock signal sequentially passes through the 0 th to M-1 stage inversion unit 111, the M th stage first inverter 121, and the M-1 th to 0 th stage second inverter 122 to be delayed for a certain time and output, so that M-stage delay of the clock signal is realized.

In this embodiment, each stage of the inverter circuit is completely the same, so that the duty cycle loss of each stage of the inverter circuit caused by the process, voltage and temperature offsets is also completely compensated by the next stage of the inverter circuit, and thus, no duty cycle loss exists.

Referring to fig. 4, 5, and 8, in another embodiment, a clock control method according to the present application includes:

s210, controlling the 0 th-M-1 th-level inverting unit 111 to be opened, the pull-up unit 112 and the pull-down unit 113 to be closed, closing the Mth-level inverting unit 111 and the pull-down unit 113, and opening the Mth-level pull-up unit 112, wherein the output end of the Mth-level four-state gate circuit 11 is pulled up to a high level and is kept at the high level, and M is a natural number between 0 and N;

s220, controlling the first inverter 121 of the 0 th to M-1 st stage to be closed and the second inverter 122 to be opened, and controlling the first inverter 121 of the M th stage to be opened and the second inverter 122 to be closed;

s230, the mask signal gate _ en is turned on, and the clock signal output OUT is locked to the first level. The mask signal gate _ en is at a high level, the input terminal IN of the delay circuit is kept at a low level through the inverter 24 and the and logic gate 23, and the clock signal output OUT is locked at a low level. In addition, in this embodiment, an inverter may be externally connected to the output terminal of the delay circuit, so that the clock signal output OUT is locked to a high level.

In the working process of the delay circuit, the turned-off odd-level four-state gate circuit 11 outputs logic high, and the turned-off even-level four-state gate circuit 11 outputs logic low. The internal node voltage of the delay circuit becomes stable high-low (1/0) level alternate distribution, and no matter the control signal is switched to any stage to be switched on or switched off, the internal node voltage of the delay line still becomes stable high-low level alternate distribution, and no glitch signal is generated during switching.

Referring to fig. 4, 6, and 9, in another embodiment, a clock control method of the present application includes:

s310, controlling the 0 th-M-1 th-level inverting unit 111 to be opened, the pull-up unit 112 and the pull-down unit to be closed 113, closing the Mth-level inverting unit 111 and the pull-up unit 121, and opening the Mth-level pull-down unit 113, wherein the output end of the Mth-level four-state gate circuit 11 is pulled down to be at a low level and is kept at the low level;

s320, controlling the first inverter 121 of the 0 th to M-1 st stage to be closed and the second inverter 122 to be opened, and controlling the first inverter 121 of the M th stage to be opened and the second inverter 122 to be closed;

s330, the mask signal gate _ en is turned on, and the clock signal output OUT is locked to the second level. The mask signal gate _ en is at a high level, the input terminal IN of the delay circuit is kept at a low level by the or logic gate 33, and the clock signal output OUT is locked at a high level. In addition, in this embodiment, an inverter may be externally connected to the output terminal of the delay circuit, so that the clock signal output OUT is locked to a low level.

It should be noted that all or any of the embodiments described above may be combined with each other, unless stated otherwise or such embodiments may be functionally and/or architecturally mutually exclusive.

Although the present application has been described in connection with the particular example embodiments referenced, the present application is not limited to the embodiments described herein, but may be embodied with modification and alteration within the spirit and scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the application is not limited except as by the appended claims.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. Even if specific features are recited in different dependent claims, the application relates to embodiments having these features in common. Any reference signs in the claims shall not be construed as limiting the scope.

Features and aspects of different embodiments may be integrated into further embodiments, and embodiments shown in this document may be practiced without all of the illustrated or described features or aspects. Those skilled in the art will note that while specific examples and embodiments of the present systems and methods are described for illustrative purposes, various modifications can be made without departing from the spirit and scope of the application. Furthermore, features of one embodiment may be incorporated into another embodiment even if the features are not described together in a single embodiment in this document. Accordingly, the present application is described by the appended claims.