阅读说明：本技术 基于盲分离与卡尔曼滤波器的忆阻器窄带干扰处理系统及方法 (Memristor narrow-band interference processing system and method based on blind separation and Kalman filter ) 是由 张红伟 梁洪弋 杨善华 马雪迪 刘晨 王传旭 于 2020-06-09 设计创作，主要内容包括：本发明公开了基于盲分离与卡尔曼滤波器的忆阻器窄带干扰处理系统及方法,包括盲分离方法和干扰处理方法,本发明涉及电子技术领域,步骤1：找出问题,并进行研究工作；步骤2：窄带干扰噪声信号设计；窄带干扰抑制方法与研究现状,窄带干扰模型BLGN构型设计,步骤3：RRAM忆阻器网络阵列；忆阻器神经网络研究现状,RRAM共享权重技术,忆阻器仿真模型,模型改进方案,步骤4：盲分离编程电压噪声信号处理；盲分离技术研究现状,ICA窄带干扰盲分离,基于卡尔曼滤波的窄带信号消除与缺陷节点确认,步骤5:结论,可进行干扰处理,提高忆阻器NPU的精度和鲁棒性,对于每层神经网络进行优化处理,能够对损坏节点进行定位。(The invention discloses a memristor narrow-band interference processing system and method based on blind separation and a Kalman filter, and the system comprises a blind separation method and an interference processing method, and relates to the technical field of electronics, wherein the method comprises the following steps: finding out problems and carrying out research work; step 2: designing a narrow-band interference noise signal; narrow-band interference suppression method and current research situation, narrow-band interference model BLGN configuration design, step 3: an RRAM memristor network array; the method comprises the following steps of (1) researching the current situation of a memristor neural network, using an RRAM (resistive random access memory) shared weight technology, using a memristor simulation model, using a model improvement scheme, and carrying out the step 4: blind separation programming voltage noise signal processing; and 5, concluding that interference processing can be performed, the precision and the robustness of the memristor NPU are improved, optimization processing is performed on each layer of neural network, and the damaged node can be positioned.)

1. Memristor narrowband interference processing system based on blind separation and Kalman filter, including blind separation system and interference processing system, its characterized in that: the blind separation system comprises an external data source module, wherein the output end of the external data source module is electrically connected with a signal whitening module, the output end of the signal whitening module is sequentially and electrically connected with a first memristor network module and a blind signal processing module, the output end of the first memristor network module is electrically connected with a second memristor network module, the output end of the blind signal processing module is electrically connected with a sparse signal processing module, the output end of the sparse signal processing module is electrically connected with an automatic detection algorithm module, the automatic detection algorithm module is electrically connected with the first memristor network module, the output end of the second memristor network module is electrically connected with the automatic detection algorithm module, and the automatic detection algorithm module is electrically connected with the automatic detection algorithm module.

2. The method of claim 1 for memristor narrow-band jamming processing based on blind separation and Kalman filter, characterized in that: the interference processing method comprises the following steps:

step 1: finding out problems and carrying out research work;

step 2: designing a narrow-band interference noise signal;

firstly, a narrow-band interference suppression method and the current research situation;

secondly, designing a BLGN configuration of a narrow-band interference model;

and step 3: an RRAM memristor network array;

the method comprises the following steps of (I), researching the current situation of a memristor neural network;

(II) RRAM sharing weight technology;

(III) a memristor simulation model;

the update formula of the memristor is as follows:

i(t)＝G(y,v)v(t)

where G (y, v) is the conductance of a given memristor state y, and F (y, v) describes the dynamic evolution of that state, a time-dependent measurement v.

The conductance formula results as:

where Gm, a, and b are constants in all states and histories for a particular device and depend on the material properties within the conduction channel.

The open switching equation for the model is:

the updating is done in such a way that the relevant weights are scaled to the relevant pins when the voltage is above or below a certain value.

(IV) a model improvement scheme;

(1) the noise is added to the BLGN, and then,

the hierarchy is noised with BLGN.

v(t)＝v₁(t)+N(t)

N(t_n)＝x₁cos(2πf_lt_n)-x₂sin(2πf_lt_n)

tn is the sampling point of t.

(2) A model diagram is shown, wherein the model diagram is shown,

and 4, step 4: blind separation programming voltage noise signal processing;

the method comprises the following steps of (I), blind separation technical research current situation;

secondly, carrying out ICA narrow-band interference blind separation;

thirdly, narrow-band signal elimination and defect node confirmation based on Kalman filtering;

(1) estimating a voltage signal and eliminating noise;

the prediction formula is as follows:

X_kp＝A_Xk-1+B_uk+w_k

P_kp＝A_Pk-1A_T+Q_k

a: state transition matrix, B: control matrix, Wk: predicted noise, Qk: state transition noise

(2) Evaluating a model;

(3) and the defect nodes are avoided, and the node is prevented,

and 5, concluding.

3. The method of claim 2 for memristor narrow-band jamming processing based on blind separation and Kalman filter, characterized in that: the content of the research work is as follows:

(1) designing simulation of hardware noise on the basis of the existing simulator and NPU CNN architecture, simulating a real environment and increasing model reliability;

(2) the algorithm for processing the noise by adopting the blind source separation technology is specifically to extract systematic interference by utilizing a blind separation method, reconstruct narrow-band interference and impulse noise based on a greedy algorithm SPA-SAMP compressed sensing and eliminate hardware noise under the condition of ensuring accuracy.

4. The method of claim 2 for memristor narrow-band jamming processing based on blind separation and Kalman filter, characterized in that: the content of the narrow-band interference model BLGN configuration design is as follows:

(1) noise model configuration principle;

(2) and researching the feasibility of improving the memristor neural network.

5. The method of claim 2 for memristor narrow-band jamming processing based on blind separation and Kalman filter, characterized in that: the content of ICA narrow-band interference blind separation is as follows:

(1) ICA programming voltage blind separation;

(2) and obtaining a filtering support set.

Technical Field

The invention relates to the technical field of electronics, in particular to a memristor narrow-band interference processing system and method based on blind separation and a Kalman filter.

Background

With increasing manufacturing costs and increasing fundamental physical limitations, device scaling alone cannot bridge the expected performance gap between the latest CMOS based chips and the requirements of future neural networks. RRAM equipment formed by a memristor Neural Processing Unit (NPU) gradually enters a practical scene, and the memristor is a special device with resistance changed along with current and has the characteristic of switching between high and low resistance values, so that the memristor becomes an ideal neural network hardware element. RRAM is proposed as a new type of memory, and is expected to be a breakthrough of Moore's law, and the biggest problems in the current stage are temperature fluctuation, difficulty in automatic test, reading speed and the like. Different from general neural network processing, the hardware implementation method can achieve energy efficiency of more than two orders of magnitude of the existing processing method. However, in the process of hardware construction, hardware noise and material properties of the memristor cause mutual interference, the memristor becomes one of experimental error factors due to the property that the resistance is changed by temperature and voltage, and such errors are gradually accumulated and worsen or cannot obtain better efficiency at a certain stage based on the characteristics of the neural network. The practical application is further complicated by the inherent device and cross-point array deficiencies.

The search for an anti-interference method is an important subject in communication system research, and when a useful signal and noise are mixed together, it is very important to separate out a valid signal, and in RRAM equipment, systematic noise is processed, and automatic testing and other technical processes are performed. The PCMA is widely concerned as one of the existing satellite signal processing technologies, VIASAT company has been concerned after the technology is provided, and becomes a technology of the key attention of the Chinese military. The blind separation technology and the array signal processing are novel technologies and are worth paying attention, and a method for processing memristor array noise through the blind separation technology is provided in consideration of the ideality of the conventional memristor simulation. At present, the existing technology has poor interference performance, poor precision and robustness of a memristor NPU, and cannot optimize each layer of neural network and position a damaged node.

Disclosure of Invention

Technical problem to be solved

Aiming at the defects of the prior art, the invention provides a memristor narrow-band interference processing system and method based on blind separation and a Kalman filter, and solves the problems that the interference performance is poor, the precision and the robustness of a memristor NPU are poor, each layer of neural network cannot be optimized, and a damaged node cannot be positioned.

(II) technical scheme

In order to achieve the purpose, the invention is realized by the following technical scheme: a memristor narrow-band interference processing system based on blind separation and a Kalman filter comprises a blind separation system and an interference processing system, the blind separation system comprises an external data source module, the output end of the external data source module is electrically connected with a signal whitening module, the output end of the signal whitening module is electrically connected with a first memristor network module and a blind signal processing module in sequence, the output end of the first memristor network module is electrically connected with a second memristor network module, the output end of the blind signal processing module is electrically connected with a sparse signal processing module, the output end of the sparse signal processing module is electrically connected with an automatic detection algorithm module, the automatic detection algorithm module is electrically connected with the first memristor network module, the output end of the second memristor network module is electrically connected with the automatic detection algorithm module, and the automatic detection algorithm module is electrically connected with the automatic detection algorithm module.

Preferably, the method for processing interference includes the following steps:

step 1: finding out problems and carrying out research work;

step 2: designing a narrow-band interference noise signal;

firstly, a narrow-band interference suppression method and the current research situation;

secondly, designing a BLGN configuration of a narrow-band interference model;

and step 3: an RRAM memristor network array;

the method comprises the following steps of (I), researching the current situation of a memristor neural network;

(II) RRAM sharing weight technology;

(III) a memristor simulation model;

the update formula of the memristor is as follows:

i(t)＝G(y,v)v(t)

where G (y, v) is the conductance of a given memristor state y, and F (y, v) describes the dynamic evolution of that state, a time-dependent measurement v.

The conductance formula results as:

where Gm, a, and b are constants in all states and histories for a particular device and depend on the material properties within the conduction channel.

The open switching equation for the model is:

the updating is done in such a way that the relevant weights are scaled to the relevant pins when the voltage is above or below a certain value.

(IV) a model improvement scheme;

(1) the noise is added to the BLGN, and then,

the hierarchy is noised with BLGN.

v(t)＝v₁(t)+N(t)

N(t_n)＝x₁cos(2πf_lt_n)-x₂sin(2πf_lt_n)

tn is the sampling point of t.

(2) A model diagram is shown, wherein the model diagram is shown,

and 4, step 4: blind separation programming voltage noise signal processing;

the method comprises the following steps of (I), blind separation technical research current situation;

secondly, carrying out ICA narrow-band interference blind separation;

thirdly, narrow-band signal elimination and defect node confirmation based on Kalman filtering;

(1) estimating a voltage signal and eliminating noise;

the prediction formula is as follows:

X_kp＝A_Xk-1+B_uk+w_k

P_kp＝A_Pk-1A_T+Q_k

a: state transition matrix, B: control matrix, Wk: predicted noise, Qk: state transition noise

(2) Evaluating a model;

(3) and the defect nodes are avoided, and the node is prevented,

and 5, concluding.

Preferably, the content of the research work is as follows:

(1) designing simulation of hardware noise on the basis of the existing simulator and NPUCNN architecture, simulating a real environment and increasing model reliability;

(2) the algorithm for processing the noise by adopting the blind source separation technology is specifically to extract systematic interference by utilizing a blind separation method, reconstruct narrow-band interference and impulse noise based on a greedy algorithm SPA-SAMP compressed sensing and eliminate hardware noise under the condition of ensuring accuracy.

Preferably, the content of the narrow-band interference model BLGN configuration design is as follows:

(1) noise model configuration principle;

(2) and researching the feasibility of improving the memristor neural network.

Preferably, the content of the ICA narrowband interference blind separation is as follows:

(1) ICA programming voltage blind separation;

(2) and obtaining a filtering support set.

(III) advantageous effects

The invention provides a memristor narrow-band interference processing system and method based on blind separation and a Kalman filter. Has the following beneficial effects:

(1) the memristor narrow-band interference processing system and method based on blind separation and Kalman filter comprises the following steps: finding out problems and carrying out research work; step 2: designing a narrow-band interference noise signal; and step 3: an RRAM memristor network array; and 4, step 4: blind separation programming voltage noise signal processing; interference processing can be carried out, the precision and the robustness of the memristor NPU are improved, optimization processing is carried out on each layer of neural network, and damaged nodes can be located.

Drawings

Fig. 1 is a flow chart of a blind separation method.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a memristor narrow-band interference processing system and method based on blind separation and a Kalman filter comprise a blind separation system and an interference processing system, the blind separation method comprises an external data source module, the output end of the external data source module is electrically connected with a signal whitening module, the output end of the signal whitening module is sequentially and electrically connected with a first memristor network module, the output end of the first memristor network module is electrically connected with a second memristor network module, the output end of the blind signal processing module is electrically connected with a sparse signal processing module, the output end of the sparse signal processing module is electrically connected with an automatic detection algorithm module, the automatic detection algorithm module is electrically connected with the first memristor network module, the output end of the second memristor network module is electrically connected with the automatic detection algorithm module, and the automatic detection algorithm module is electrically connected with the automatic detection algorithm module;

the interference processing method comprises the following steps:

step 1: finding out problems and carrying out research work; the content of the research work is as follows:

(1) designing simulation of hardware noise on the basis of an existing simulator and an NPUCNN framework, simulating a real environment, and increasing model reliability, specifically, randomly adding a frequency domain sparse multi-band limited Gaussian interference source superposition model (BLGN) to each network layer and a memristor unit by a sparse reconstruction method, approaching to a semiconductor memristor component under an actual condition as much as possible, simulating the temperature drift characteristic of the memristor, and then changing an RRAM simulation model which is more practical in entering and exiting;

(2) the algorithm for processing the noise by adopting the blind source separation technology is characterized in that systematic interference is extracted by utilizing a blind separation method, narrow-band interference and impulse noise are reconstructed based on a greedy algorithm SPA-SAMP compressed sensing, hardware noise is eliminated under the condition of ensuring accuracy, a better learning library is provided for a method for providing memristor component accuracy at the present stage, the using time and error superposition deterioration are inevitable in actual use, the network stability and accuracy can be improved as much as possible by effective testing and elimination algorithms, and meanwhile, the damaged node positioning capability is possessed.

Step 2: designing a narrow-band interference noise signal;

firstly, a narrow-band interference suppression method and the current research situation; the interference signal mainly comes from an unwanted signal caused by a signal source outside the system, enters the communication system through a medium, and overlaps with the wanted signal, and part of the interference signal may also come from the inside of the system. Among them, electromagnetic interference (EMI) of electromagnetic radiation, cross modulation interference, etc. are common in electronic components, and narrowband interference and impulse noise are important interference factors in the components, and in the NPU, the interference suffered by each memristor unit causes resistance change per se and overall output disorder. Most importantly, no matter the narrow-band interference or the impulse noise interference, the traditional AWGN model and theory can not be used for simple analysis, the narrow-band interference does not have the white characteristic, the statistical distribution of the impulse noise is non-Gaussian, and the combined distribution of the narrow-band interference and the impulse noise does not accord with the combined Gaussian distribution. An existing noise model such as a narrow-band interference band-limited Gaussian noise model (BLGN) is only that the amplitude of a single signal symbol accords with single-variable Gaussian distribution, a Gaussian mixture model pulse non-zero element of impulse noise accords with Poisson distribution, and the model does not belong to a traditional AWGN model, the power spectrum of general narrow-band interference and impulse noise generally exceeds 15-16 dB or even 50dB, and effective simulation is not performed on the actual scene by the existing memristor network design, so that an improvement of noise simulation is provided based on practical application schemes such as OFDM and MIMO.

Secondly, designing a BLGN configuration of a narrow-band interference model; the content of the narrow-band interference model BLGN configuration design is as follows:

(1) noise model configuration principle; in practical application, there are various narrowband interference models, such as a narrowband band-limited random power spectral density model, a spatial random distribution narrowband interference generation source attenuation model, a frequency domain sparse multi-band-limited gaussian interference source superposition model, and the like. According to practical application, a frequency domain sparse multiband limited Gaussian interference source superposition model (BLGN) is selected, belongs to a statistical model, and is defined as superposition of BLGN interference sources at any position, wherein each interference source is generated by a Gaussian white noise source through a band-pass filter with the bandwidth limited within a broadband interference bandwidth and is converted to a certain central frequency position. With efficient design, the bandwidth of the model can be made small enough to make the interference model sparse. Since memristor network signal processing is closer to digital signal processing, for example, narrow-band density statistical models are not suitable for eliminating and estimating noise. The proper BLGN configuration can accurately depict the sparse feature of the narrow-band interference frequency domain and is in accordance with the statistical feature in practice. Particularly, the model is adopted to depict the strong adaptability in systems such as OFDM and the like.

For general OFDM, the OFDM is classified into CP-OFDM, TDS-OFDM and the like according to different structures, and the difference basically depends on the coding form adopted by the guard interval of the OFDM.

(2) The feasibility research of memristor neural network improvement is that, taking CNN neural network memristor configuration as an example, at present, a memristor network formed by pure hardware is realized [1], and because the hierarchy of the neural network is related to learning precision, the more reliable the processed data is due to the appropriate hierarchy

And step 3: an RRAM memristor network array;

the method comprises the following steps of (I), researching the current situation of a memristor neural network;

the memristor switch consists of two vertical nanowire layers, acting as a top selection saddle and a bottom electrode, respectively. The mold parting material is positioned between the two nanowire layers; thus, a cosmetic device is formed at each intersection.

The memristor switch is suitable for large-scale neural network implementation. First, it is high density because the crossbars can be stacked vertically and each intersection is a beautician. In addition, the U.S. is non-volatile, nanoscale, and multi-state. Second, it is low power consumption, the array switch allows memory and computation integration, and the memory is a non-volatile device, operating voltage is low. These advantages of memristor arrays make this architecture applicable to a wide range of neural networks.

A neuromorphic computing system using memristors provides a fast and energy-saving approach, a convolutional neural network is one of the most important models for image recognition, and for RRAM devices formed by memristor devices, the intersection points are an array of intersection points, and each intersection point has one memristor unit.

From the CNN perspective, the model and associated methods are optimized based on existing improvements. Convolutional neural networks, which greatly reduces the number of free parameters. The most advanced micro-architectures typically rely on weight sharing techniques, but still suffer from von neumann bottlenecks based on the transistor platform. On the basis, later researchers construct a neural network formed by a memristor network, related efficiency is greatly improved, and compared with the traditional equipment, the efficiency of more than two orders of magnitude can be achieved according to the existing results.

However, problems that have to be solved, such as conductance drift, temperature drift, nonlinearity and other characteristics of the memristor itself, still spread around the RRAM. The RRAM is also prone to partial memristor damage caused by manufacturing reasons, and the problems to be solved currently exist.

A typical calculation process from CNN involves a number of sliding convolution operations. In this respect, a calculation unit supporting parallel product calculation is highly required. This demand has led to redesign of conventional systems to run higher performance, lower power CNNs, however, further improvements in computational efficiency will ultimately be constrained by the von neumann architecture of these systems, where the physical separation of memory and processing units results in significant energy consumption, as well as significant data delay between units. In contrast, RRAM provides a promising non-von neumann computing mode in which data is stored, thereby eliminating the cost of data transfer. By directly using ohm's law for multiplication and kirchhoff's law for accumulation, the memory array can realize parallel memory product accumulation operation, thereby realizing analog memory calculation and greatly improving speed and energy efficiency.

(II) RRAM sharing weight technology;

the development of RRAM inevitably applies to the idea of neural networks, and weight sharing is a common function of the most advanced neural networks, and the number of available parameters required for executing element extraction can be greatly reduced compared to densely connected networks. Inspired by human eye observation of images in physiology, the method not only reduces the preprocessing of translation and local distortion of processing input to the maximum extent, but also extracts and classifies local spatial correlation. CNN is now the main framework for analyzing visual images, and weight sharing can also exploit spatial and temporal transition invariance of patterns. Has wide application prospect.

Most implementations of the shared weight structure rely on a graphics processing unit. However, these weight-sharing networks suffer from large inference delays and high power consumption when implemented in conventional digital hardware. These problems become less economical if the calculations are made at the edge of the internet of things era. An asic with an optimized multiplying unit makes it possible to increase the energy efficiency. However, the von neumann bottleneck and transistor expansion of this architecture limit the ultimate efficiency. Therefore, fundamental changes in computing platforms and their building blocks are critical to meet the ever-increasing demand for computing power.

Memristors are emerging as two-terminal electronic devices with analog conductance, fast switching, excellent scalability, long retention, and long durability. Memristor arrays naturally parallelize multiply-accumulate operations. This analog memory computation directly uses the intrinsic physical laws to avoid the large energy and time overhead created by frequent data interactions in von neumann systems. This enables the memristor array to physically embody a fully connected layer of the network and enhance energy efficiency. However, practical computing systems are always bounded in terms of computing power and memory. Furthermore, typical datasets have spatial or temporal correlation. Given the number of memory particles, or the number of trainable parameters of the system, multi-tier sensors are often less functional than weight-sharing networks, limiting their practical application.

Since memristors are most efficiently assembled in crossbar matrices, which are different from the microstructure of weight-shared artificial neural networks, it is necessary to efficiently map the highly-dimensional trainable parameters of the weight-shared network to the 2D memristor array. Furthermore, such a mapping should meet more stringent requirements on weight representation accuracy, since the architecture of weight sharing is more susceptible to hardware non-idealities than a fully connected network. Due to the random behavior of memristors, memristors may not react well to synaptic weights, which are related to ion mobility, but are improved by iterative correction, at the expense of time and efficiency. This makes training of the weight sharing architecture a difficult task. Thus, memristors are only used for fully connected networks, while temporal weight sharing has recently been demonstrated in recursive structures. Theoretical studies have been made on how convolutional layers map to binary weighted memristor crossbar switches and memristors CNNs, which were experimentally validated on memristors. Recently, the multiply-accumulate operation for 2-bit input and 3-bit weight convolution has been demonstrated on a megabit binary state resistance switch matrix with 65nm and 55nm cmos logic processing. However, absent in-situ training of the memristor's spatially shared weight architecture, this is the case for simultaneous spatiotemporal weight sharing on the memristor array.

Training in situ to directly store and update weights in the memristor array, and performing calculation at the original position of the neural network parameter storage; this avoids the need to implement duplicate systems in a computer, thereby increasing the area/energy efficiency of the system. More importantly, the in-situ training back propagation can self-adaptively adjust network parameters to minimize the inevitable non-idealities of hardware, such as wire resistance, analog peripheral asymmetry, unresponsive memristors, conductance drift and conductance programming variation, and improve the shared weight network.

The university of Massachusetts topic group shows that the hardware non-ideality of a single transistor single memristor (1T1R) array can be improved by in-situ training of shared weight neural network work and mapping a simple convolution kernel to a memristor crossbar. The MNIST handwriting numbers are classified by using only 1000 weights, and the accuracy rate reaches 92.13%, namely one fourth of the number of memristor multilayer bootstrap networks with similar performance. Furthermore, we demonstrate that the advantages of weight sharing can be extended by cascading convolution kernels with the intrinsic 3D input in the network, thereby determining the spatial and temporal dependencies of the input into states and state-to-state transitions. Experiments demonstrate that trainable parameters are reduced to 850 through section-temporal memristor weight sharing, which is an effective way to implement advanced network topologies for edge computation using memristor-based hardware.

Optical micrographs of a 1T1R memristor array are shown, including analog programming capability, long data multiplexing, and greater endurance, with these neurons being non-chip popped by conventional transistor circuitry. Rather than using 1T1R arrays for different neural network layers, the partitioning of a single large array essentially shares presynaptic euros between different layers of the same network, thereby maximizing the utility of the peripheral circuitry and benefiting from edge applications.

The realization of the convolution operation based on particles needs to use

The various cores perform each form slide operation. The memristor array is efficient in realizing parallel product accumulation operation under the shared input of different cores. A typical convolution example of a particular sliding step is shown, showing the associated d event in the lTlR memristor array. The input value is encoded in pulses according to its quantization bit number. The symbolic kernel weights map to differential conduction of a pair of memristors. Thus, all weights of the kernel map to two electrical conductive rows: one row for positive pulse inputs and the other row for negative weights, with an equivalent negative pulse input. After the coded pulses are input to the bit lines, the output currents through the two differential source lines are detected and accumulated. The differential current is a weighted sum of the pair of input patches and the selected core. Different kernels with different weights are mapped to different differential row pairs, and the whole memristor array operates product column addition operation in parallel under the same input. All required weighted sum results are obtained simultaneously.

In typical CNN training, it is necessary to respect the "inverse" of the target derivative with the final output to determine all weight updates. This task requires a highly complex operation in order to apply the encoded read pulses to the source line from back to front and layer by layer. Training a complex memristor network is challenging due to non-ideal device characteristics, such as non-linear and asymmetric conductance tuning. Unlike pure in-situ training solutions, the in-situ training method is a shortcut that utilizes existing high performance parameters. However, unavoidable hardware defects, such as defective devices, parasitic line resistance and capacitance, can obscure weight and degrade system performance.

(III) a memristor simulation model;

the series resistance of a circuit containing a memristor is negligible when compared to the on-state of the device. However, this may not be the case when measurements are made on the device. When memristors and series resistors are comparable, the voltage division can have a significant effect on the dynamic measurement results, and careful consideration must be given to data analysis, and the sneak current is a significant source of error.

The update formula of the memristor is as follows:

i(t)＝G(y,v)v(t)

where G (y, v) is the conductance of a given memristor state y, and F (y, v) describes the dynamic evolution of that state, a time-dependent measurement v.

The conductance formula results as:

where Gm, a, and b are constants in all states and histories for a particular device and depend on the material properties within the conduction channel. When the metal phase fills the entire channel, y is 1. It is also described that Frenkel-Poole migration occurs when the more oxidized phase fills the entire channel, so y is 0. Depending on the actual structure, formation of memristors can be roughly divided into dynamic structural models as well as static structural models.

According to the journal conclusion, the static equation ignores the temperature fluctuation.

From journal observations, significant ringing behavior-an initial phase of slow conductance change followed by a fast switch that saturates indefinitely.

Because the saturation term is required due to the maximum resistance of the channel when the end is oxidized. Finally, to match the time dependence of any individual switching curve, power p needs to be used to reduce the switching speed. The open switching equation for this model is:

the updating is done in such a way that the relevant weights are scaled to the relevant pins when the voltage is above or below a certain value. This is also a relatively simple solution for memristor emulation at present. Further, the actual values may be further simulated according to different materials.

Obviously, the scheme is rough, and according to the idea, the designed memristor can only ensure that the value can be maintained to be stable when the use environment is stable. In the simulation mode based on the characteristics, the dynamic temperature influence and the change of the external environment are ignored, and according to the actual situation, the reasonable setting of the noise is necessary, in the cited figures in the related documents, the final result deterioration caused by the influence of the noise is non-serious, and in certain cases, the system operation is even broken down.

(IV) a model improvement scheme; the contents of the model improvement scheme are as follows:

(1) the noise is added to the BLGN, and then,

in addition to models of problem groups such as ma province and Qing Hua, an interference model using BLGN as a main noise source is added to simulate the actual situation, and the BLGN as an effective noise simulation scheme in an OFDM model can effectively simulate the correlated noise in the OFDM system. In view of the similarity of the OFDM block and the block structure of the neural network, the distribution noise distribution in the memristor is narrow-band interference, the distribution noise in the memristor has a large influence on the error accumulation of the neural network, and in order to fully fit the narrow-band noise, a BLGN model with sparsity processing is selected, and the model is widely applied in actual production, such as radars and the like.

The hierarchy is noised with BLGN.

v(t)＝v₁(t)+N(t)

N(t_n)＝x₁cos(2πf_lt_n)-x₂sin(2πf_lt_n)

tn is the sampling point of t.

According to the research result of Massachusetts university, an algorithm is improved on the correlation result, and since the random function is only quantitatively simulated on a memristor part and correlation operation is not carried out between neural networks, the method also puts relevant noise between the neural network layers.

The random noise based on the BLGN model is provided, the model has the characteristics of sparsity and good randomness, and due to the fact that in an actual scene, the OFDM model and the neural network have similarity in structure, related concepts can be directly cited. The BLGN model is a sparsity model and meets the characteristic that useful signals are most in practical scenes.

And adding a BLGN noise source to the corresponding level according to the hierarchical relation.

MATLAB is used as a main tool. Simulations will be performed with relevant data added between the individual levels according to experimental requirements.

(2) A model diagram is shown, wherein the model diagram is shown,

according to the experimental results, after comparison with the relevant data sets, the simulation results are as follows.

Firstly, obtaining the values of different intersections of current flowing through the ideal state and the actual state:

further, noise is applied to the ideal data:

the ideal matrix subtracted from the actual matrix results:

and (3) subtracting the actual matrix from the ideal matrix after noise addition:

calculate the mean square error and output the result:

the result proves that the noise adding effect is more fit with the actual model.

According to the comparison of general experimental data, the noise rule has Gaussian property, and the real device operation condition can be better reflected.

And 4, step 4: blind separation programming voltage noise signal processing;

the method comprises the following steps of (I), blind separation technical research current situation;

blind separation technology is a relatively mature technology and is widely used in various production environments. Among them, independent component analysis is an effective algorithm. Because the independent component analysis algorithm can effectively extract potential information, signals such as narrow-band signals, impulse noise and the like can be effectively extracted by preprocessing noise and other signals. In an orthogonal frequency division multiplexing system, because impulse noise has great interference to a frequency spectrum, truncation is generally carried out, and a narrow-band signal is relatively easy to extract. However, independent component analysis enables correct detection of narrowband signals in practical verification. A set of supports can be obtained that can be extracted and preprocessed. Independent component analysis is a new technology that has evolved to address the problem of blind source separation. The "sound source" in blind source separation refers to an independent component, i.e., the speech signal of the speaker at the "cocktail party". Independent component analysis reproduces non-observable source signal components from the mixed signal using easily fulfilled preconditions. In many documents, the source signals are independent of each other, independent component analysis and blind source separation have the same or similar models, or two parallel methods, which are solved by the same or similar algorithms. There is no deliberate distinction between BSS and ICA. For topical use, such mixed use is, under normal circumstances, hardly effective.

Secondly, carrying out ICA narrow-band interference blind separation; the content of ICA narrow-band interference blind separation is as follows:

(1) ICA programming voltage blind separation;

from a theoretical or mathematical point of view, independent component analysis is a signal analysis technique. The purpose is to determine a specific transformation to ensure that the transformation of each component of the output signal is independent of each other. In many cases, independent component analysis uses higher order statistics, so blind source separation implementations do not completely overlap independent component analysis. These functions may also be used to isolate the source signal, for example, time-dependent, non-stationary characteristics of the signal, if the source signal has some other function.

(2) And obtaining a filtering support set to obtain a filtering support set,

according to practical situations, narrow-band noise can be effectively separated in addition to the result that impulse noise is relatively difficult to separate.

Thirdly, narrow-band signal elimination and defect node confirmation based on Kalman filtering; the narrow-band signal elimination and defect node confirmation based on Kalman filtering comprises the following contents:

(1) estimating a voltage signal and eliminating noise;

the prediction formula is as follows:

X_kp＝A_Xk-1+B_uk+w_k

P_kp＝A_Pk-1A_T+Q_k

a: state transition matrix, B: control matrix, Wk: predicted noise, Qk: state transition noise

(2) Evaluating a model;

(3) and the defect nodes are avoided, and the node is prevented,

further, in an actual scene, due to the fact that memristor detection is generally carried out through the meter, after defect node avoidance is carried out, unnecessary energy consumption can be reduced, and device efficiency is improved.

Step 5-conclusion

According to the simulation result, the established model can basically accord with the actual working model, and the efficiency of product design is optimized. The ICA algorithm is provided with a scheme for extracting a memristor noise support set, filtering is carried out by using a Kalman filter, and a defect node is confirmed to avoid, so that the cost can be reduced in actual production, and the development progress is accelerated.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation. The use of the phrase "comprising one of the elements does not exclude the presence of other like elements in the process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.