Semiconductor device and method of forming the same
阅读说明:本技术 半导体装置及其形成方法 (Semiconductor device and method of forming the same ) 是由 郑志昌 朱馥钰 柳瑞兴 于 2019-06-13 设计创作,主要内容包括:在一些实施例中,提供一种半导体装置。所述半导体装置包括隔离结构,所述隔离结构设置在半导体衬底中,其中所述隔离结构的内周界划定出所述半导体衬底的装置区。栅极设置在所述装置区之上,其中所述栅极的外周界设置在所述隔离结构的所述内周界内。第一源极/漏极区设置在所述装置区中及所述栅极的第一侧上。第二源极/漏极区设置在所述装置区中及所述栅极的与所述第一侧相对的第二侧上。硅化物阻挡结构局部地覆盖所述栅极、局部地覆盖所述第一源极/漏极区且局部地覆盖所述隔离结构,其中所述硅化物阻挡结构的第一侧壁设置在所述栅极的第一相对侧壁之间。(In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.)
1. A semiconductor device, comprising:
an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure delimits a device region of the semiconductor substrate;
a gate disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure;
a first source/drain region disposed in the device region and on a first side of the gate;
a second source/drain region disposed in the device region and on a second side of the gate opposite the first side; and
a silicide block structure locally overlying the gate, locally overlying the first source/drain region, and locally overlying the isolation structure, wherein a first sidewall of the silicide block structure is disposed between first opposing sidewalls of the gate.
2. The semiconductor device of claim 1, wherein the silicide-block structure contacts an upper surface of the gate, an upper surface of the first source/drain region, and an upper surface of the isolation structure.
3. The semiconductor device according to claim 1, wherein:
the first side of the gate is spaced apart from the second side of the gate in a first lateral direction; and is
The first opposing sidewalls of the gate are spaced apart in a second lateral direction that is perpendicular to the first lateral direction.
4. The semiconductor device of claim 3, wherein a second sidewall of the silicide-block structure is disposed outside the inner perimeter of the isolation structure, and wherein the second sidewall of the silicide-block structure is opposite the first sidewall.
5. The semiconductor device of claim 4, wherein a third sidewall of the silicide-block structure is disposed between a second opposing sidewall of the gate, and wherein the second opposing sidewall of the gate is spaced apart in the first lateral direction.
6. The semiconductor device of claim 4, wherein the silicide-block structure extends continuously from a third sidewall of the silicide-block structure to a fourth sidewall of the silicide-block structure, the fourth sidewall being opposite the third sidewall, wherein the third sidewall is spaced apart from the fourth sidewall in the first lateral direction, and both the third sidewall and the fourth sidewall are disposed outside the inner perimeter of the isolation structure.
7. A semiconductor device, comprising:
an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a plurality of sides of a device region of the semiconductor substrate;
first and second source/drain regions disposed in the device region and spaced apart in a first lateral direction;
a gate disposed over the device region and between the first and second source/drain regions, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure;
a first silicide blocking structure covering a first portion of the gate, a first portion of the first source/drain region, and a first portion of the isolation structure; and
a second silicide-block structure overlying a second portion of the gate, a second portion of the first source/drain region, and a second portion of the isolation structure, wherein the second silicide-block structure is spaced apart from the first silicide-block structure in a second lateral direction that is perpendicular to the first lateral direction.
8. The semiconductor device according to claim 7, further comprising:
a first conductive contact electrically coupled to the first source/drain region, wherein the first conductive contact is disposed between the first silicide blocking structure and the second silicide blocking structure and between the gate and the isolation structure.
9. The semiconductor device according to claim 8, further comprising:
a first pickup region and a second pickup region disposed in the device region between the first source/drain region and the second source/drain region, wherein:
the first pickup region is spaced apart from the second pickup region in the second lateral direction and disposed on opposite sides of the gate;
the first pickup region comprises a different doping type than the first source/drain region; and is
The first silicide blocking structure is disposed between the first pickup region and the first conductive contact.
10. A method of forming a semiconductor device, the method comprising:
forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure delimits a device region of the semiconductor substrate;
forming a gate over the device region and within the inner perimeter of the isolation structure;
forming first and second source/drain regions in the device region and on first opposing sides of the gate, wherein the first opposing sides of the gate are spaced apart in a first lateral direction;
forming a first silicide blocking structure that partially covers the first source/drain region, that partially covers the gate, and that partially covers the isolation structure;
forming a second silicide-block structure spaced apart from the first silicide-block structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide-block structure partially covers the first source/drain region, partially covers the gate, and partially covers the isolation structure; and
performing a silicide process to form a first silicide layer on the first source/drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure.
Technical Field
Embodiments of the invention relate to a semiconductor device and a method of forming the same.
Background
Semiconductor devices are electronic components that utilize the electronic properties of semiconductor materials to affect an electric field or its associated fields. One type of semiconductor device that is widely used is a field-effect transistor (FET). The FET includes a pair of source/drain regions, a selectively conductive channel, and a gate electrode. FETs are general-purpose devices that can be used in switches, amplifiers, memories, and the like. Examples of FETs include metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction gate field-effect transistors (JFETs).
Disclosure of Invention
According to an embodiment of the present invention, a semiconductor device includes an isolation structure, a gate, a first source/drain region, a second source/drain region, and a silicide blocking structure. An isolation structure is disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.
According to an embodiment of the present invention, a semiconductor device includes: the semiconductor device comprises an isolation structure, a first source/drain region, a second source/drain region, a grid, a first silicide blocking structure and a second silicide blocking structure. Isolation structures are disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structures defines multiple sides of a device region of the semiconductor substrate. First and second source/drain regions are disposed in the device region and spaced apart in a first lateral direction. A gate is disposed over the device region and between the first and second source/drain regions, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first silicide blocking structure covers a first portion of the gate, a first portion of the first source/drain region, and a first portion of the isolation structure. A second silicide-block structure overlies a second portion of the gate, a second portion of the first source/drain region, and a second portion of the isolation structure, wherein the second silicide-block structure is spaced apart from the first silicide-block structure in a second lateral direction that is perpendicular to the first lateral direction.
According to an embodiment of the present invention, a method of forming a semiconductor device includes: forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure delimits a device region of the semiconductor substrate; forming a gate over the device region and within the inner perimeter of the isolation structure; forming first and second source/drain regions in the device region and on first opposing sides of the gate, wherein the first opposing sides of the gate are spaced apart in a first lateral direction; forming a first silicide blocking structure that partially covers the first source/drain region, that partially covers the gate, and that partially covers the isolation structure; forming a second silicide-block structure spaced apart from the first silicide-block structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide-block structure partially covers the first source/drain region, partially covers the gate, and partially covers the isolation structure; and performing a silicide process to form a first silicide layer on the first source/drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1C illustrate various perspective views of some embodiments of Field Effect Transistors (FETs) with low flicker noise (flicker noise) and low Random Telegraph Noise (RTN).
Fig. 2 illustrates a perspective view of some other embodiments of the FET shown in fig. 1A-1C.
Fig. 3A-3D illustrate various views of various more detailed embodiments of the FETs shown in fig. 1A-1C.
Fig. 4A-4D illustrate various diagrams of various more detailed embodiments of the FET shown in fig. 2.
Fig. 5A-5D illustrate various views of other embodiments of the FET shown in fig. 3A-3D.
Fig. 6A-6D illustrate various views of other embodiments of the FET shown in fig. 4A-4D.
Fig. 7A-7D-16A-16D illustrate a series of diagrams of some embodiments of methods of forming FETs with low flicker noise and low RTN.
Fig. 17 illustrates a flow diagram of some embodiments of a method of forming a FET with low flicker noise and low RTN.
[ description of symbols ]
100: a Field Effect Transistor (FET);
102: a semiconductor substrate;
104: a first well;
106: a well pickup region;
108: a first silicide layer;
110: an isolation structure;
110 p: an inner perimeter;
112: a device region;
114 a: a first source/drain region;
114 b: a second source/drain region;
116: a selective conductive channel;
118: a second silicide layer;
120: a gate electrode;
122: a gate electrode;
124: a gate dielectric;
126: a third silicide layer;
127: isolating the corner;
128a, 128b, 128c, 128 d: a silicide blocking structure;
302: a sidewall spacer;
304: an interconnect structure;
306: a conductive contact;
308: an interlayer dielectric (ILD) layer;
310 a: a first side wall;
310 b: a second side wall;
312a, 312b, 312 c: a doped region;
502: a second well;
504: a third well;
1002a, 1002 b: lightly doped source/drain extensions;
1700: a flow chart;
1702. 1704, 1706, 1708, 1710, 1712, 1714, 1716, 1718, 1720, 1722, 1724: an action;
A-A ', B-B ', C-C ': a wire;
D1: a first distance;
D2: a second distance;
D3: a third distance.
Detailed Description
The present invention will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not drawn to scale. It should be understood that this detailed description and the corresponding drawings do not limit the scope of the disclosure in any way, and that they provide only a few examples to illustrate some ways in which the inventive concepts may be manifested.
The present invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of illustration, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Some Field Effect Transistors (FETs) include a semiconductor substrate and a Shallow Trench Isolation (STI) structure. STI structures are disposed in a semiconductor substrate and delineate device regions of the semiconductor substrate. In addition, the FET includes a pair of source/drain regions, a selectively conductive channel, a gate dielectric, and a gate electrode. Source/drain regions are disposed in the device region and spaced laterally apart. A selective conductive channel is disposed in the device region and extends from one of the source/drain regions to the other of the source/drain regions. A gate dielectric overlies the selectively conductive channel and a gate electrode overlies the gate dielectric layer.
The challenges faced by the above FETs are flicker noise and Random Telegraph Noise (RTN). One of the sources of flicker noise and RTN is due to the presence of defect states at a pair of STI corners (horns). STI corners are top cutaway corners of a semiconductor substrate that are located in the device region and interface with STI structures. Further, STI corners are respectively located on opposite sides of the selective conduction channel and each extend laterally along a length of the selective conduction channel from one of the plurality of source/drain regions to another of the plurality of source/drain regions. STI corners have a large number of defect states because they have high mechanical stress and are not defined by a perfectly flat surface. Furthermore, since the STI corners have a small radius of curvature, the electric field at the STI corners is strong. Thus, as current flows through the selectively conductive channel, charge carriers are trapped (trap) and de-trapped (de-trap) due to the defect state, thereby generating flicker noise and RTN.
Part of the solution to the challenge is to use the gate electrode as a mask to move the source/drain regions away from the STI corners. For example, gate electrodes are formed over the device regions and over the STI corners. The gate electrode is formed with a pair of source/drain openings that overlap the device region and are spaced apart from the STI corners. With the gate electrode in place, an ion implantation process is performed to form source/drain regions in the semiconductor substrate spaced apart from the STI corners. By spacing the source/drain regions from the STI corners, current flowing along the STI corners may be reduced, reducing flicker noise and RTN generated at the STI corners. However, despite the source/drain regions being spaced from the STI corners, when a voltage is applied to the gate to cause current to flow through the selective conduction channel, charge carriers may still be trapped and de-trapped due to defective states at the STI corners because the gate electrode overlaps the STI corners (e.g., such that inversion regions are formed near/along the STI corners). In addition, by using the gate electrode to move the source/drain regions away from the STI corners, a subsequent silicide formation process (e.g., a salicide process) may form a silicide layer that shorts the FETs (e.g., a silicide layer that couples the source/drain regions together).
Various embodiments of the present application relate to a semiconductor device having low flicker noise and low RTN. For example, the semiconductor device may include an isolation structure (e.g., an STI structure) disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, and an outer perimeter of the gate is disposed within an inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed on a second side of the gate in the device region, the second side being opposite the first side. The silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure.
Since the perimeter of the gate is disposed within the inner perimeter of the isolation structure, the gate does not overlap the STI corners. Accordingly, during operation of the semiconductor device (e.g., when a voltage is applied to the gate causing current to flow through the selectively conductive channel), charge carriers may not be trapped and de-trapped due to defective states at the STI corners, thereby reducing flicker noise and RTN. In addition, since the silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, the silicide blocking structure may prevent the silicide process from forming a silicide layer that shorts out the semiconductor device.
Fig. 1A-1C illustrate various perspective views of some embodiments of a Field Effect Transistor (FET)100 with low flicker noise and low Random Telegraph Noise (RTN). Fig. 1A is an exploded perspective view of the FET shown in fig. 1B to 1C. Fig. 1B is an exploded perspective view of the FET shown in fig. 1A and 1C. Fig. 1C is a configuration perspective view of the FET shown in fig. 1A to 1B.
Fig. 1A is "deconstructed" in that the
As shown in fig. 1A to 1C, the
In some embodiments, a pair of well pickup (pickup)
An
A first source/
In some embodiments, a pair of second silicide layers 118 are disposed on/in the first and second source/
A
In some embodiments, the outer perimeter of the
Since the
In addition, a plurality of silicide blocking structures 128 a-128 d are disposed over the
In some embodiments, the first
Thus, the first
In some embodiments, the second silicide-
Thus, the second silicide-
It should be appreciated that in some embodiments, the third
Fig. 2 illustrates a perspective view of some other embodiments of the
As shown in fig. 2, the first
In some embodiments, the second
Fig. 3A-3D illustrate various views of various more detailed embodiments of the FETs shown in fig. 1A-1C. Fig. 3A is a top layout view of some embodiments of the FETs of fig. 3B-3D with
As shown in fig. 3A-3D,
An
A
The
In some embodiments, the one of the first opposing sidewalls of the
Since the
Fig. 4A-4D illustrate various diagrams of various more detailed embodiments of the FET shown in fig. 2. Fig. 4A is a top layout view of some embodiments of the FETs of fig. 4B-4D with
As shown in fig. 4A-4D, in some embodiments, the
Since the
Fig. 5A-5D illustrate various views of other embodiments of the FET shown in fig. 3A-3D. Fig. 5A is a top layout view of some embodiments of the FETs of fig. 5B-5D with
As shown in fig. 5A-5D, in some embodiments, a
In some embodiments, a
Fig. 6A-6D illustrate various views of other embodiments of the FET shown in fig. 4A-4D. Fig. 6A is a top layout view of some embodiments of the FETs shown in fig. 6B-6D with
As shown in fig. 6A to 6D, the
Fig. 7A-7D-16A-16D illustrate a series of diagrams of some embodiments of methods of forming FETs with low flicker noise and low RTN. The figure with the suffix "a" (e.g., fig. 7A) is a top view of the FET during various steps of the formation method. The figure with the suffix "B" (e.g., fig. 7B) is a sectional view of the FET taken along the line a-a' in the figure with the suffix "a", respectively. The figure with the suffix "C" (e.g., fig. 7C) is a sectional view of the FET taken along the line B-B' in the figure with the suffix "a", respectively. The figure with the suffix "D" (e.g., fig. 7D) is a cross-sectional view of the FET taken along line C-C' in the figure with the suffix "a", respectively. The FET may, for example, be substantially similar to the FET shown in fig. 3A-3D.
As shown in fig. 7A to 7D, an
As shown in fig. 8A to 8D, the
As shown in fig. 9A to 9D, a
In some embodiments, the process of forming the
Thereafter, a process layer (not shown) is formed on the dielectric layer. In some embodiments, the process layer may be, for example, polysilicon. In other embodiments, the process layer may be doped polysilicon, metal, or some other conductor. In still other embodiments, the process layer may be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process.
After forming the process layer on the dielectric layer, the process layer and the dielectric layer are patterned into the
As shown in fig. 10A-10D, a pair of lightly doped source/drain extensions 1002 a-1002 b are formed in the
As shown in fig. 11A-11D,
As shown in fig. 12A to 12D, a pair of
In addition, a first
In some embodiments, the well pick-up
As shown in fig. 13A-13D, first and second source/
In addition, a
In some embodiments, the first source/
As shown in fig. 14A-14D, a plurality of silicide block structures 128 a-128D are formed on the
In some embodiments, the second
In some embodiments, the process of forming the plurality of silicide block structures 128 a-128 d includes depositing or growing a silicide block layer (e.g., a resist protection oxide (PRO) layer) on the
As shown in fig. 15A to 15D, a pair of first silicide layers 108 is formed on/in the
In some embodiments, the process of forming the
As shown in fig. 16A to 16D, an
In some embodiments, the process of forming the
As shown in fig. 17, a flow diagram 1700 of some embodiments of a method of forming a FET with low flicker noise and low RTN is provided. Although the flowchart 1700 shown in fig. 17 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts illustrated herein may be performed in one or more separate acts and/or phases.
At act 1702, an isolation structure is formed in a semiconductor substrate, wherein an inner perimeter of the isolation structure delimits a device region of the semiconductor substrate. Fig. 7A-7D illustrate various diagrams of some embodiments corresponding to act 1702.
At act 1704, a well is formed in the device region. Fig. 8A-8D illustrate various diagrams of some embodiments corresponding to act 1704.
At act 1706, a gate is formed over the device region and within the inner perimeter of the isolation structure, wherein the gate includes a gate electrode disposed on the gate dielectric. Fig. 9A-9D illustrate various diagrams of some embodiments corresponding to act 1706.
At act 1708, a pair of lightly doped source/drain extensions are formed in the device region and on opposite sides of the gate. Fig. 10A-10D illustrate various diagrams of some embodiments corresponding to act 1708.
Sidewall spacers are formed over the device region and along the sides of the gate at act 1710. Fig. 11A-11D illustrate various diagrams of some embodiments corresponding to act 1710.
At act 1712, a pair of well pickup regions are formed in the device region. Fig. 12A-12D illustrate various diagrams of some embodiments corresponding to act 1712.
At act 1714, a first doped region and a second doped region are formed in the gate electrode. Fig. 12A-12D illustrate various diagrams of some embodiments corresponding to act 1714.
At act 1716, first and second source/drain regions are formed in the device region and on opposite sides of the gate. Fig. 13A-13D illustrate various diagrams of some embodiments corresponding to act 1716.
At act 1718, a third doped region is formed in the gate electrode. Fig. 13A-13D illustrate various diagrams of some embodiments corresponding to act 1718.
At act 1720, a plurality of silicide blocking structures are formed that partially cover the device region, the gate, and the isolation structure. Fig. 14A-14D illustrate various diagrams of some embodiments corresponding with act 1720.
At act 1722, a silicide layer is formed on/in the semiconductor substrate and the gate electrode. Fig. 15A-15D illustrate various diagrams of some embodiments corresponding to act 1722.
At act 1724, an interconnect structure is formed over the semiconductor substrate, the gate, and the isolation structure. Fig. 16A-16D illustrate various diagrams of some embodiments corresponding to act 1724.
In some embodiments, the present application provides a semiconductor device. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a device region of the semiconductor substrate. A gate is disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposing sidewalls of the gate.
In an embodiment, the silicide-block structure contacts an upper surface of the gate, an upper surface of the first source/drain region, and an upper surface of the isolation structure. In an embodiment, the first side of the gate is spaced apart from the second side of the gate in a first lateral direction; and the first opposing sidewalls of the gate are spaced apart in a second lateral direction that is perpendicular to the first lateral direction. In an embodiment, a second sidewall of the silicide-block structure is disposed outside the inner perimeter of the isolation structure, and wherein the second sidewall of the silicide-block structure is opposite the first sidewall. In an embodiment, a third sidewall of the silicide-block structure is disposed between second opposing sidewalls of the gate, and wherein the second opposing sidewalls of the gate are spaced apart in the first lateral direction. In an embodiment, the silicide block structure extends continuously from the third sidewall to a fourth sidewall of the silicide block structure, the fourth sidewall being opposite the third sidewall, and wherein the fourth sidewall is disposed outside the inner perimeter of the isolation structure. In an embodiment, the second sidewall is disposed between the inner perimeter of the isolation structure and an outer perimeter of the isolation structure. In an embodiment, a shortest distance between the inner perimeter of the isolation structure and one of a plurality of the first opposing sidewalls in the second lateral direction is less than or equal to about 1 micron. In an embodiment, a shortest distance between the one of the plurality of side walls in the first opposing side wall and the first side wall in the second lateral direction is less than or equal to about 1 micron. In an embodiment, a shortest distance between the second sidewall and the inner perimeter of the isolation structure in the second lateral direction is less than or equal to about 1 micron. In an embodiment, the silicide blocking structure extends continuously from a third sidewall of the silicide blocking structure to a fourth sidewall of the silicide blocking structure, the fourth sidewall being opposite the third sidewall, wherein the third sidewall is spaced apart from the fourth sidewall in the first lateral direction, and both the third sidewall and the fourth sidewall are disposed outside the inner perimeter of the isolation structure.
In other embodiments, the present application provides a semiconductor device. The semiconductor device includes: an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure defines a plurality of sides of a device region of the semiconductor substrate. First and second source/drain regions are disposed in the device region and spaced apart in a first lateral direction. A gate is disposed over the device region and between the first and second source/drain regions, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first silicide blocking structure covers a first portion of the gate, a first portion of the first source/drain region, and a first portion of the isolation structure. A second silicide-block structure overlies a second portion of the gate, a second portion of the first source/drain region, and a second portion of the isolation structure, wherein the second silicide-block structure is spaced apart from the first silicide-block structure in a second lateral direction that is perpendicular to the first lateral direction.
In an embodiment, the semiconductor device further comprises a first conductive contact electrically coupled to the first source/drain region, wherein the first conductive contact is disposed between the first silicide-block structure and the second silicide-block structure and between the gate and the isolation structure. In an embodiment, the semiconductor device further comprises a first pickup region and a second pickup region disposed in the device region between the first source/drain region and the second source/drain region, wherein: the first pickup region is spaced apart from the second pickup region in the second lateral direction and disposed on opposite sides of the gate; the first pickup region comprises a different doping type than the first source/drain region; and the first silicide blocking structure is disposed between the first pickup region and the first conductive contact. In an embodiment, the first silicide blocking structure at least partially covers the first pickup region; and the second silicide-block structure at least partially covers the second pickup region. In an embodiment, the semiconductor device further comprises a third silicide blocking structure and a fourth silicide blocking structure. A third silicide-blocking structure covers a third portion of the gate, a first portion of the second source/drain region, and a third portion of the isolation structure. A fourth silicide-block structure overlying a fourth portion of the gate, a second portion of the second source/drain region, and a fourth portion of the isolation structure, wherein: the third silicide blocking structure is spaced apart from the fourth silicide blocking structure in the second lateral direction; and the third silicide-block structure and the fourth silicide-block structure are both spaced apart from the first silicide-block structure and the second silicide-block structure in the first lateral direction. In an embodiment, the semiconductor device further comprises a second conductive contact, a first silicide layer, and a second silicide layer. A second conductive contact is electrically coupled to the first pickup region, wherein the second conductive contact is disposed between the first silicide blocking structure and the third silicide blocking structure. A first silicide layer is disposed between the first conductive contact and the first source/drain region, wherein the first silicide layer covers a portion of the first source/drain region between the first silicide-blocking structure and the second silicide-blocking structure and between the gate and the isolation structure. A second silicide layer is disposed between the second conductive contact and the first pickup region, wherein the second silicide layer covers a portion of the first pickup region that is between the first silicide-blocking structure and the third silicide-blocking structure and between the gate and the isolation structure. In an embodiment, the first silicide-block structure covers a first portion of the second source/drain region; opposing sidewalls of the first silicide-block structure are spaced apart in the first lateral direction and disposed outside the inner perimeter of the isolation structure; the second silicide-block structure covers a second portion of the second source/drain region; and opposing sidewalls of the second silicide-block structure are spaced apart in the first lateral direction and disposed outside the inner perimeter of the isolation structure.
In yet other embodiments, the present application provides a method of forming a semiconductor device. The method includes forming an isolation structure in a semiconductor substrate, wherein an inner perimeter of the isolation structure delimits a device region of the semiconductor substrate. A gate is formed over the device region and within the inner perimeter of the isolation structure. First and second source/drain regions are formed in the device region and on first opposing sides of the gate, wherein the first opposing sides of the gate are spaced apart in a first lateral direction. Forming a first silicide blocking structure that partially covers the first source/drain region, that partially covers the gate, and that partially covers the isolation structure. Forming a second silicide-block structure spaced apart from the first silicide-block structure in a second lateral direction perpendicular to the first lateral direction, wherein the second silicide-block structure partially covers the first source/drain region, partially covers the gate, and partially covers the isolation structure. Performing a silicide process to form a first silicide layer on the first source/drain region, wherein the first silicide layer is disposed between the first silicide blocking structure and the second silicide blocking structure.
In an embodiment, the method further comprises: forming a first pickup region and a second pickup region in the device region and on a second opposing side of the gate, wherein the second opposing side of the gate is spaced apart in the second lateral direction, wherein the silicide process forms a second silicide layer on the first pickup region, and wherein the first silicide blocking structure is disposed between the second silicide layer and the first silicide layer.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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