阅读说明：本技术 一种高速低功耗比较电路、转换器和电子设备 (High-speed low-power consumption comparison circuit, converter and electronic equipment ) 是由 苏杰 朱勇 徐祎喆 于 2021-07-21 设计创作，主要内容包括：本发明公开了一种高速低功耗比较电路,属于无线通讯和电路设计技术领域。本发明主要包括包括前置放大器和锁存器,锁存器包括复位晶体管对、锁存输入晶体管对以及反相器对；其中,复位晶体管对包括第一晶体管和第二晶体管；锁存输入晶体管对包括第三晶体管和第四晶体管；反相器对包括第五晶体管、第六晶体管、第七晶体管和第八晶体管。本发明能够在保持比较器低功耗的条件下,减小前置放大器输出节点的节点内部寄生电容并实现更高的采样率。(The invention discloses a high-speed low-power-consumption comparison circuit, and belongs to the technical field of wireless communication and circuit design. The invention mainly comprises a preamplifier and a latch, wherein the latch comprises a reset transistor pair, a latch input transistor pair and a phase inverter pair; wherein the reset transistor pair includes a first transistor and a second transistor; the latch input transistor pair includes a third transistor and a fourth transistor; the inverter pair includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The invention can reduce the internal parasitic capacitance of the output node of the preamplifier and realize higher sampling rate under the condition of keeping the low power consumption of the comparator.)

1. A high-speed low-power comparison circuit comprising a preamplifier and a latch,

the latch comprises a reset transistor pair, a latch input transistor pair and an inverter pair;

wherein the reset transistor pair includes a first transistor and a second transistor;

the latch input transistor pair includes a third transistor and a fourth transistor;

the inverter pair includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a source of the first transistor is connected with a power supply, a gate of the first transistor is connected with a first clock signal, and a drain of the first transistor is connected with drains of the third transistor and the fifth transistor and gates of the sixth transistor and the eighth transistor;

the source electrode of the second transistor is connected with the power supply, the grid electrode of the second transistor is connected with the first clock signal, and the drain electrode of the second transistor is connected with the grid electrodes of the fifth transistor and the seventh transistor and the drain electrodes of the sixth transistor and the fourth transistor;

the source electrode of the third transistor is connected with the drain electrode of the seventh transistor, the grid electrode of the third transistor is connected with the non-inverting output node of the preamplifier, and the drain electrode of the third transistor is connected with the drain electrode of the first transistor;

a source of the fourth transistor is connected to a drain of the eighth transistor, a gate of the fourth transistor is connected to the inverted output node of the preamplifier, and a drain of the fourth transistor is connected to a drain of the second transistor;

the source electrode of the fifth transistor is connected with the power supply, the grid electrode of the fifth transistor is connected with the drain electrode of the second transistor, and the drain electrode of the fifth transistor is connected with the drain electrode of the first transistor;

the source electrode of the sixth transistor is connected with the power supply, the grid electrode of the sixth transistor is connected with the drain electrode of the first transistor, and the drain electrode of the sixth transistor is connected with the drain electrode of the second transistor;

the source electrode of the seventh transistor is grounded, the grid electrode of the seventh transistor is connected with the drain electrode of the second transistor, and the drain electrode of the seventh transistor is connected with the source electrode of the third transistor;

the source of the eighth transistor is grounded, the gate of the eighth transistor is connected to the drain of the first transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.

2. A high speed, low power consumption comparison circuit as claimed in claim 1,

the first transistor, the second transistor, the fifth transistor and the sixth transistor in the latch are PMOS transistors, and the third transistor, the fourth transistor, the seventh transistor and the eighth transistor in the latch are NMOS transistors.

3. A high speed, low power consumption comparison circuit as recited in claim 1, further comprising,

the inverted output nodes of the latch are the drains of the first transistor, the fifth transistor and the third transistor and the gates of the sixth transistor and the eighth transistor;

a non-inverting output node of the latch is drains of the second transistor, the sixth transistor, and the fourth transistor and gates of the fifth transistor and the seventh transistor.

4. A high speed, low power consumption comparison circuit as claimed in claim 1,

the preamplifier comprises a twelfth transistor, a thirteenth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein the twelfth transistor and the thirteenth transistor are PMOS tubes, the ninth transistor, the tenth transistor and the eleventh transistor are NMOS tubes;

wherein a drain of the twelfth transistor and a drain of the tenth transistor are a non-inverting output node of the preamplifier, and a drain of the thirteenth transistor and a drain of the eleventh transistor are an inverting output node of the preamplifier.

5. A high speed, low power consumption comparison circuit as claimed in claim 4,

a source of the twelfth transistor is connected with the power supply, a gate of the twelfth transistor is connected with a second clock signal, and a drain of the twelfth transistor is connected with a drain of the tenth transistor;

a source of the thirteenth transistor is connected to the power supply, a gate of the thirteenth transistor is connected to the second clock signal, and a drain of the thirteenth transistor is connected to a drain of the eleventh transistor;

a source of the tenth transistor is connected to a drain of the ninth transistor and a source of the eleventh transistor, a gate of the tenth transistor is connected to the non-inverting input node of the preamplifier, and a drain of the tenth transistor is connected to a drain of the twelfth transistor;

a source of the eleventh transistor is connected to a drain of the ninth transistor and a source of the tenth transistor, a gate of the eleventh transistor is connected to the inverting input node of the preamplifier, and a drain of the eleventh transistor is connected to a drain of the thirteenth transistor;

the source of the ninth transistor is grounded, the gate of the ninth transistor is connected with the second clock signal, and the drain of the ninth transistor is connected with the sources of the tenth transistor and the eleventh transistor.

6. A high speed, low power consumption comparison circuit as recited in claim 1, further comprising,

and the SR latch is positioned behind the preamplifier and the latch and is used for avoiding the influence of the current output result of the preamplifier and the latch on the next output result.

7. A high speed low power analog to digital converter comprising a high speed low power comparison circuit as claimed in any one of claims 1 to 6.

8. An electronic device characterized in that it comprises a high-speed low-power analog-to-digital converter according to claim 7.

Technical Field

The invention relates to the technical field of wireless communication and circuit design, in particular to a high-speed low-power-consumption comparison circuit, a converter and electronic equipment.

Background

With the development of microelectronic circuits, many devices are beginning to be applied in mobile systems for the purpose of acquiring data in real time and being portable. This results in a need for a circuit that can operate at low supply voltages and that maintains low power consumption when designing the circuit. The data transmission is not independent of the digital-to-analog converter, and the design of the comparator which is an important module in the digital-to-analog converter is also important.

In the prior art, the comparison is accomplished using a strong arm latching comparator. The presence of stacked transistors in a strong arm latch comparator makes it necessary to have a high voltage margin and, in addition, the offset and speed of the strong arm latch comparator are very sensitive to any common mode variations. In the two-tailed architecture and modified two-tailed comparator, the output of the comparator is directly connected to the latch node, making it unsuitable for low power applications during the amplification stage.

Disclosure of Invention

Aiming at the problems in the prior art, the invention mainly provides a high-speed low-power-consumption comparison circuit, a converter and electronic equipment.

In order to achieve the above purpose, the invention adopts a technical scheme that: provided is a high-speed low-power comparison circuit, including: a latch and a preamplifier, the latch comprising a reset transistor pair, a latch input transistor pair and an inverter pair; wherein the reset transistor pair includes a first transistor and a second transistor; the latch input transistor pair includes a third transistor and a fourth transistor; the inverter pair includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the source electrode of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a first clock signal, and the drain electrode of the first transistor is connected with the drain electrodes of the third transistor and the fifth transistor and the grid electrodes of the sixth transistor and the eighth transistor; the source electrode of the second transistor is connected with a power supply, the grid electrode of the second transistor is connected with the first clock signal, and the drain electrode of the second transistor is connected with the grid electrodes of the fifth transistor and the seventh transistor and the drain electrodes of the sixth transistor and the fourth transistor; the source electrode of the third transistor is connected with the drain electrode of the seventh transistor, the grid electrode of the third transistor is connected with the positive phase output node of the preamplifier, and the drain electrode of the third transistor is connected with the drain electrode of the first transistor; the source electrode of the fourth transistor is connected with the drain electrode of the eighth transistor, the grid electrode of the fourth transistor is connected with the inverted output node of the preamplifier, and the drain electrode of the fourth transistor is connected with the drain electrode of the second transistor; the source electrode of the fifth transistor is connected with the power supply, the grid electrode of the fifth transistor is connected with the drain electrode of the second transistor, and the drain electrode of the fifth transistor is connected with the drain electrode of the first transistor; the source electrode of the sixth transistor is connected with the power supply, the grid electrode of the sixth transistor is connected with the drain electrode of the first transistor, and the drain electrode of the sixth transistor is connected with the drain electrode of the second transistor; the source electrode of the seventh transistor is grounded, the grid electrode of the seventh transistor is connected with the drain electrode of the second transistor, and the drain electrode of the seventh transistor is connected with the source electrode of the third transistor; the source of the eighth transistor is grounded, the gate of the eighth transistor is connected to the drain of the first transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.

The invention adopts another technical scheme that: a high-speed low-power analog-to-digital converter is provided, which comprises the high-speed low-power comparison circuit according to the first scheme.

The invention adopts another technical scheme that: an electronic device is provided, which comprises the high-speed low-power consumption analog-to-digital converter according to the second scheme.

The technical scheme of the invention can achieve the following beneficial effects: the invention designs a high-speed low-power consumption comparison circuit, a converter and electronic equipment. The invention has higher sampling rate, lower energy consumption, better response to common mode change and stronger stability.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of one embodiment of a high speed low power comparison circuit of the present invention;

FIG. 2 is a schematic diagram of one embodiment of a high speed low power comparison circuit of the present invention;

the components in figures 1 and 2 are numbered as follows: m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; m8-an eighth transistor; m9 — ninth transistor; m10-tenth transistor M11-eleventh transistor; m12 — twelfth transistor; m13-thirteenth transistor; OP-positive phase output node of the preamplifier; ON-the inverting output node of the preamplifier; INP-positive input node of the preamplifier; INN-the inverting input node of the preamplifier; VOUT (volatile organic compound)₊-a non-inverting output node of the latch; VOUT (volatile organic compound)_--an inverting output node of the latch; VDD-power supply; latch_-B-a first clock signal; latch — second clock signal.

Embodiments of the present invention have been illustrated by the above-described drawings and will be described in more detail hereinafter. The drawings and the description are not intended to limit the scope of the inventive concept in any way, but rather to illustrate it by those skilled in the art with reference to specific embodiments.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 shows an embodiment of a high-speed low-power comparison circuit according to the present invention.

In this embodiment, a high speed low power comparison circuit generally comprises a latch and a preamplifier, the latch comprising a reset transistor pair, a latch input transistor pair, and an inverter pair; wherein the reset transistor pair includes a first transistor and a second transistor; the latch input transistor pair includes a third transistor and a fourth transistor; the inverter pair includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the source electrode of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a first clock signal, and the drain electrode of the first transistor is connected with the drain electrodes of the third transistor and the fifth transistor and the grid electrodes of the sixth transistor and the eighth transistor; the source electrode of the second transistor is connected with a power supply, the grid electrode of the second transistor is connected with the first clock signal, and the drain electrode of the second transistor is connected with the grid electrodes of the fifth transistor and the seventh transistor and the drain electrodes of the sixth transistor and the fourth transistor; the source electrode of the third transistor is connected with the drain electrode of the seventh transistor, the grid electrode of the third transistor is connected with the positive phase output node of the preamplifier, and the drain electrode of the third transistor is connected with the drain electrode of the first transistor; the source electrode of the fourth transistor is connected with the drain electrode of the eighth transistor, the grid electrode of the fourth transistor is connected with the inverted output node of the preamplifier, and the drain electrode of the fourth transistor is connected with the drain electrode of the second transistor; the source electrode of the fifth transistor is connected with the power supply, the grid electrode of the fifth transistor is connected with the drain electrode of the second transistor, and the drain electrode of the fifth transistor is connected with the drain electrode of the first transistor; the source electrode of the sixth transistor is connected with the power supply, the grid electrode of the sixth transistor is connected with the drain electrode of the first transistor, and the drain electrode of the sixth transistor is connected with the drain electrode of the second transistor; the source electrode of the seventh transistor is grounded, the grid electrode of the seventh transistor is connected with the drain electrode of the second transistor, and the drain electrode of the seventh transistor is connected with the source electrode of the third transistor; the source of the eighth transistor is grounded, the gate of the eighth transistor is connected to the drain of the first transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.

In a specific embodiment of the present invention, a high-speed low-power comparison circuit is composed of a preamplifier and a latch, an input signal to be compared is input into the high-speed low-power comparison circuit through a positive input node of the preamplifier and an inverted input node of the preamplifier, the preamplifier performs a first-stage amplification on the input signal and then transmits the amplified signal to the latch, the latch temporarily stores the amplified signal and performs a second-stage amplification on the amplified signal, and the amplified signal is transmitted to a subsequent circuit. The working process of the high-speed low-power-consumption comparison circuit comprises a regeneration stage and a reset stage, wherein in the reset stage, the levels of a positive phase output node of the latch and an inverse phase output node of the latch are pulled to be high, no signal is transmitted to the positive phase input node of the preamplifier, the positive phase output node of the preamplifier, the inverse phase input node of the preamplifier and the inverse phase output node of the preamplifier, and the high-speed low-power-consumption comparison circuit is restored to an initial working state.

In the regeneration stage, after the levels of a positive phase output node of the latch and an inverted phase output node of the latch are pulled high, the preamplifier transmits the amplified signals to the latch, the latch performs secondary amplification to obtain a comparison result, and the high-speed low-power comparison circuit transmits the comparison result to a subsequent circuit from the positive phase output node of the latch and the inverted phase output node of the latch.

In the specific embodiment, the circuit structure of the latch is changed, so that the high-speed low-power comparison circuit is suitable for a use environment with higher sampling rate, lower energy consumption, better response to common-mode change and stronger stability requirement.

In a specific embodiment of the present invention, the first transistor, the second transistor, the fifth transistor and the sixth transistor of the latch are PMOS transistors, and the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are NMOS transistors.

In one embodiment of the present invention, the latch includes that the inverted output nodes of the latch are drains of the first transistor, the fifth transistor and the third transistor and gates of the sixth transistor and the eighth transistor; the non-inverting output node of the latch is the drains of the second, sixth, and fourth transistors and the gates of the fifth and seventh transistors.

In one embodiment of the invention, as shown in fig. 2, in the high-speed low-power comparison circuit, the source of M1 is connected to VDD, the gate of M1 is connected to Latch-B, the drain of M1 is connected to the drains of M3 and M5 and the gates of M8 and M6; the source of M5 is connected to VDD, the gate of M5 is connected to the gate of M6 and the drains of M4, M6 and M2, and the drain of M5 is connected to the drain of M1; the source of M6 is connected with VDD, the gate of M6 is connected with the drain of M1, and the drain of M6 is connected with the gate of M5; the source of M2 is connected with VDD, the gate of M2 is connected with Latch-B, and the drain of M2 is connected with the gate of M5; the source of M3 is connected with the drain of M6, the gate of M3 is connected with OP, and the drain of M3 is connected with the drain of M1; the source of M6 is connected with GND, the gate of M6 is connected with the gate of M5, and the drain of M6 is connected with the source of M3; the source of M4 is connected with the drain of M8, the gate of M4 is connected with ON, and the drain of M4 is connected with the gate of M5; the source of M8 is grounded, the gate of M8 is connected with the drain of M1, and the drain of M8 is connected with the source of M4; wherein OP is obtained by using the positive phase output node of the preamplifier, and ON is obtained by using the negative phase output node of the preamplifier.

According to the specific embodiment, the MOS tube in the latch is reasonably arranged, so that the latch consumes less energy in working, and the high-speed low-power comparison circuit is more suitable for a low-power environment.

In a specific embodiment of the present invention, the preamplifier includes PMOS transistors of a twelfth transistor and a thirteenth transistor, and NMOS transistors of a ninth transistor, a tenth transistor and an eleventh transistor; wherein a drain of the twelfth transistor and a drain of the tenth transistor are a non-inverting output node of the preamplifier, and a drain of the thirteenth transistor and a drain of the eleventh transistor are an inverting output node of the preamplifier.

In one embodiment of the invention, the sizes of the PMOS transistor and the NMOS transistor in the preamplifier and the latch are adjusted according to the circuit simulation result of the preamplifier and the latch.

According to the specific embodiment, the size of the transistor is reasonably selected, so that the internal node parasitic capacitance of the output end of the preamplifier is reduced, and the high-speed low-power-consumption comparison circuit can have higher sampling speed.

In a specific embodiment of the present invention, a source of the twelfth transistor is connected to the power supply, a gate of the twelfth transistor is connected to the second clock signal, and a drain of the twelfth transistor is connected to the drain of the tenth transistor; a source electrode of the thirteenth transistor is connected with the power supply, a grid electrode of the thirteenth transistor is connected with the second clock signal, and a drain electrode of the thirteenth transistor is connected with a drain electrode of the eleventh transistor; a source of the tenth transistor is connected to the drain of the ninth transistor and the source of the eleventh transistor, a gate of the tenth transistor is connected to the non-inverting input node of the preamplifier, and a drain of the tenth transistor is connected to the drain of the twelfth transistor; a source of the eleventh transistor is connected to a drain of the ninth transistor and a source of the tenth transistor, a gate of the eleventh transistor is connected to the inverting input node of the preamplifier, and a drain of the eleventh transistor is connected to a drain of the thirteenth transistor; the source of the ninth transistor is grounded, the gate of the ninth transistor is connected to the second clock signal, and the drain of the ninth transistor is connected to the sources of the tenth transistor and the eleventh transistor.

In one embodiment of the present invention, as shown in fig. 2, the source of M12 is connected to VDD, the gate of M12 is connected to Latch, and the drain of M12 is connected to the drain of M10; the source of M13 is connected to VDD, the gate of M13 is connected to Latch, and the drain of M13 is connected to the drain of M11; the source of M10 is connected with the drain of M1 and the source of M11, the gate of M10 is connected with the non-inverting input node of the preamplifier, and the drain of M10 is connected with the drain of M12; the source of M11 is connected with the drain of M1 and the source of M10, the gate of M11 is connected with the inverting input node of the preamplifier, and the drain of M11 is connected with the drain of M13; the source of M9 is grounded, the gate of M9 is connected to Latch, and the drain of M9 is connected to the sources of M10 and M11.

According to the specific embodiment, the pre-amplifier can better amplify signals by reasonably arranging the MOS tube.

In one embodiment of the present invention, when the preamplifier is in the reset phase, M12 and M13 are turned on, and M9, M10 and M11 are turned off; when the front amplifier is in the regeneration phase, M12 and M13 are turned off, and M9, M10 and M11 are turned on.

In one embodiment of the present invention, during the reset phase, M12 and M13 are turned ON, M9, M10 and M11 are turned off, OP and ON are pulled up to high level, and there is no signal input and output in the preamplifier.

In the regeneration phase, the preamplifier receives an input signal needing to be compared by using transistors M10 and M11, performs one-stage amplification ON the input signal needing to be compared by using M11, and transmits the one-stage amplification result to the latch through OP and ON.

In the specific embodiment, the preamplifier is used for carrying out primary amplification on the input signals to be compared, so that a foundation is laid for further amplification and comparison of a subsequent latch.

In an embodiment of the present invention, the high-speed low-power comparison circuit further includes an SR latch, and the SR latch is located after the preamplifier and the latch, and is used for avoiding an influence of a current output result of the preamplifier and the latch on a next output result.

In this embodiment, after the comparison circuit completes the current comparison and outputs the comparison result, the next comparison result will affect the current comparison result, and the SR latch can be used to latch the current comparison output result, thereby reducing the effect of the subsequent comparison result on the current comparison output result.

In one embodiment of the present invention, in the regeneration phase, when the second clock signal is high and the input signal to be compared flows into the ninth transistor, the first stage amplification is started by the ninth transistor. And transmitting the signal after finishing the first-stage amplification to the latch, and when the signal after finishing the first-stage amplification reaches a threshold value higher than gnd, turning on a third transistor and a fourth transistor in the latch, and starting to perform second-stage amplification on a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor by using the input signal to be compared. When the voltages of the non-inverting output node in the latch and the inverting output node of the latch approach a common-mode value, a rail-to-rail voltage is output on the non-inverting output node in the latch and the inverting output node of the latch. Before the regeneration phase is finished, due to the fact that the grid voltages of the third transistor and the fourth transistor are different, the non-inverting output node in the latch and the inverting output node of the latch are pulled to be high to a positive level VDD at one end and pulled to be ground at the other end. By comparing the discharging speed of the non-inverting output node of the latch and the inverting output node of the latch, a comparison result of the input signals needing to be compared is obtained. At the end of the regeneration phase, the input signals to be compared are tracked and sampled.

In the reset phase, when the first clock signal is low, the inverting output node of the latch and the non-inverting output node of the latch are precharged to the positive level VDD, and the history data in the latch is reset. When the second clock signal is at a low level, the twelfth transistor and the thirteenth transistor in the preamplifier are turned on, the positive phase output node of the preamplifier and the negative phase output node of the preamplifier are pulled up to a high level VDD, and the high-speed low-power comparison circuit is reset.

According to the specific embodiment, the high-speed low-power-consumption comparison circuit can better cope with common-mode changes through the coordination work between the latch and the preamplifier, and the stability is stronger.

In another embodiment of the invention, a high speed low power analog to digital converter includes, for example, a high speed low power comparison circuit, the high speed low power analog to digital converter being operative to perform functions as in the high speed low power comparison circuit.

In another embodiment of the invention, an electronic device includes a high speed low power analog to digital converter that is operative to perform functions as in a high speed low power comparison circuit.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.