阅读说明：本技术 一种面向多元信号产生和检测的控制系统及控制方法 (Control system and control method for multi-element signal generation and detection ) 是由 唐雷雷 张晓琳 徐丹妮 于 2020-06-19 设计创作，主要内容包括：本发明公开了一种面向多元信号产生和检测的控制系统及控制方法,系统包括总线接口模块,所述总线接口模块上双向连接有2～3个控制模块,所述每个控制模块用于完成32路可配置输入信号和输出信号的控制；所述控制模块包括寄存器控制模块、输入信号滤波模块、方波和脉冲产生控制模块以及方波和脉冲检测控制模块,所述寄存器控制模块与总线接口模块、输入信号滤波模块以及方波和脉冲产生控制模块双向连接；所述输入信号滤波模块和方波和脉冲检测控制模块双向连接；本发明设置2-3组控制模块,分别控制完成一组32路可配置输入、输出信号的控制,通过参数配置的方式实现至少64路输入信号检测和64路输出信号产生的功能。(The invention discloses a control system and a control method for multi-element signal generation and detection, wherein the system comprises a bus interface module, 2-3 control modules are connected to the bus interface module in a bidirectional mode, and each control module is used for controlling 32 configurable input signals and output signals; the control module comprises a register control module, an input signal filtering module, a square wave and pulse generation control module and a square wave and pulse detection control module, and the register control module is bidirectionally connected with the bus interface module, the input signal filtering module and the square wave and pulse generation control module; the input signal filtering module is bidirectionally connected with the square wave and pulse detection control module; the invention is provided with 2-3 groups of control modules which respectively control and complete the control of a group of 32 configurable input and output signals, and realizes the functions of at least 64-path input signal detection and 64-path output signal generation in a parameter configuration mode.)

1. A control system for multi-element signal generation and detection is characterized by comprising a bus interface module (101), wherein 2-3 control modules are connected to the bus interface module (101) in a bidirectional mode, and each control module is used for controlling 32 configurable input signals and output signals;

the control module comprises a register control module, an input signal filtering module, a square wave and pulse generation control module and a square wave and pulse detection control module, and the register control module is bidirectionally connected with the bus interface module (101), the input signal filtering module, the square wave and pulse detection control module and the square wave and pulse generation control module; the input signal filtering module is bidirectionally connected with the square wave and pulse detection control module;

the register control module is used for configuring the filtering parameters of the input signal filtering module, configuring the control parameters of the square wave and pulse detection control module and the square wave and pulse generation control module, and comprises an input signal filtering time register, an input signal filtering shielding register, a square wave measuring factor register, a common level output signal control register, a pulse output type register, an output control register, 32 square wave frequency measurement and pulse width measurement high level registers, 32 square wave frequency measurement and pulse width measurement low level registers, 32 square wave and pulse output high level registers, 32 square wave and pulse output low level registers and 32 square wave and pulse output number registers;

the input signal filtering module is used for filtering 32 paths of input signals;

the square wave and pulse detection control module is used for measuring the frequency and the width of the square wave and the pulse of the 32-path input signals;

the square wave and pulse generation control module is used for controlling 32 paths of square wave or pulse output signals.

2. The control system for multivariate signal generation and detection according to claim 1, wherein the input signal filtering time register is used for configuring filtering time parameters; the input signal filtering and shielding register is used for shielding or opening a filtering function; the square wave measuring factor register is used for measuring the number of continuous square wave periods when square wave frequency measurement is configured and is used for averaging; when the channel corresponding to the output control register is configured to output the ordinary level signal, the corresponding bit of the register writes '0', the corresponding channel outputs low level, the corresponding bit writes '1', and the corresponding channel outputs high level; the pulse output type register is used for configuring the type of pulse output; the output control register is used for controlling the type of the output signal; the square wave frequency measurement and pulse width measurement high-level register is used for recording the width and the overtime state of the high level of the input signal; the square wave frequency measurement and pulse width measurement low-level register is used for recording the width and the overtime state of the low level of the input signal; the square wave and pulse output high-level register is used for configuring the width of a high level; the square wave and pulse output low-level register is used for configuring the width of a low level; and the square wave and pulse output number register is used for configuring the number of output pulses, configuring whether the output is a square wave or a pulse and starting the square wave or pulse output.

3. The control system for multivariate signal generation and detection according to claim 1, wherein the register control module further comprises an input signal rising edge count register, an input signal falling edge count register, an output signal rising edge count register, and an output signal falling edge count register; the input signal rising edge counting register is used for recording the number of rising edges of the input signal; the input signal falling edge counting register is used for recording the number of times of falling edges of the input signals; the output signal rising edge counting register is used for recording the number of times of the rising edge of the output signal; the output signal falling edge counting register is used for recording the number of times of the falling edge of the output signal.

4. The control system for multivariate signal generation and detection according to claim 1, wherein the register control module further comprises an input signal rising edge interrupt enable register, an input signal falling edge interrupt enable register, an input signal rising edge interrupt status register, and an input signal falling edge interrupt status register; the input signal rising edge interrupt enabling register is used for enabling rising edge interrupt, and when the input signal changes along a rising edge, an interrupt signal is generated; the input signal falling edge interrupt enabling register is used for enabling falling edge interrupt, and when the input signal has falling edge change, an interrupt signal is generated; the input signal rising edge interrupt state register is used for recording a rising edge interrupt state, and when the processor detects an interrupt, the value of the interrupt state register is read to determine which path of input signal generates the interrupt; the input signal falling edge interrupt state register is used for recording the falling edge interrupt state, and when the processor detects an interrupt, the value of the interrupt state register is read to determine which path of input signal generates the interrupt.

5. The control system for multivariate signal generation and detection according to claim 1, wherein the register control module further comprises an input signal status register for recording a high level or a low level status of the input signal.

6. The control system for multivariate signal generation and detection according to claim 1, wherein the register control module further comprises a soft reset register for resetting the values of all registers.

7. The control system for multivariate signal generation and detection according to claim 1, wherein the register control module further comprises an input-output self-loop enable register for configuring input signals and output signal internal self-loops.

8. A filtering method with adjustable filtering width based on the control system of claim 1, which is characterized by comprising the following steps:

step A1, configuring an input signal filtering shielding register, when the corresponding bit of the input signal filtering shielding register is '1', not filtering the corresponding input channel signal, and when the corresponding bit is '0', filtering the corresponding input channel signal;

step A2, configuring a filtering parameter of an input signal filtering time register according to the filtering time of an input signal, wherein the filtering parameter is the filtering time/the clock signal period used by the filtering function;

step A3, a timer is arranged in the input signal filtering module, when the continuous sampling results of the input signal are the same, the timer is added with 1, when the continuous sampling results of the input signal are different, the timer is set to 1, when the value of the timer reaches the value of the filtering parameter configured in the step A2, the input signal is considered to be valid, otherwise, the input signal is considered to be invalid, and then invalid signals are filtered.

9. A square wave frequency measurement and pulse width measurement control method based on the control system of claim 1, characterized by comprising the following steps:

step B1, configuring the square wave measurement factor configuration register as N;

step B2, start two timers in the square wave and pulse detection control modules:

when the square wave frequency measurement is carried out, the first timer is used for recording the time T1 of the high level of the continuous N square wave periodic signals, and the second timer is used for recording the time T2 of the low level of the continuous N square wave periodic signals; latching the time T1 of the first timer in a square wave frequency measurement and pulse width measurement high-level register at the falling edge of the Nth square wave periodic signal; latching the time T2 of the second timer in a square wave frequency measurement and pulse width measurement low-level register at the rising edge of the Nth square wave periodic signal;

when the pulse width is measured, the first timer is used for recording the time of the high level of the latest positive pulse signal, and the second timer is used for recording the time of the low level of the latest 1 negative pulse signal; latching the time T1 of a first timer in a square wave frequency measurement and pulse width measurement high-level register at the falling edge of a positive pulse signal; at the rising edge of the negative pulse signal, the time T2 of the second timer is latched in a square wave frequency measurement and pulse width measurement low-level register;

step B3, when the tested signal has no rising edge and falling edge change within the set time, returning to the overtime state, and under the overtime state, the square wave frequency measurement or pulse width measurement is invalid;

b4, acquiring a value T1 of a square wave frequency measurement and pulse width measurement high level register and a value T2 of a square wave frequency measurement and pulse width measurement low level register; when square wave frequency measurement is carried out, if the bit 31 of T1 is '0' and the bit 31 of T2 is '0', the square wave frequency measurement is considered to be effective; when the pulse width is measured, if the bit 31 of the T1 is '0', the positive pulse width is considered to be effective, and if the bit 31 of the T2 is '0', the negative pulse width is considered to be effective;

step B5, when measuring the frequency of the square wave, the square wave period is (number of high level clocks + number of low level clocks)/N × clock period, the square wave duty ratio is number of high level clocks/(number of high level clocks + number of low level clocks), and the frequency of the square wave is 1/square wave period; when the pulse width is measured, the positive pulse width is equal to the number of high-level clocks and the negative pulse width is equal to the number of low-level clocks and the clock period.

10. A method of controlling square wave and pulse generation based on the control system of claim 1, comprising the steps of:

step C1, configuring an output control register, and writing '1' in a certain bit to indicate that a square wave or pulse is to be output by a corresponding output channel;

step C2, configuring a square wave and pulse output high-level register and a square wave and pulse output low-level register, wherein the registers are filled with clock numbers, and the clock period is marked as T;

step C3, if a square wave is to be output, calculating a square wave period, and then calculating a square wave high level width and a square wave low level width, where the square wave period is 1/square wave frequency, the square wave high level width is a square wave period duty ratio, the square wave low level width is a square wave period-square wave high level width, the values of the square wave and pulse output high level registers are square wave high level widths/T, and the values of the square wave and pulse output low level registers are square wave low level widths/T;

step C4, if the pulse is to be output, the pulse width and the pulse interval are converted into the number of clocks, if the positive pulse is output, the square wave and pulse output high level register fills the number of clocks with the positive pulse width, and the square wave and pulse output low level register fills the number of clocks with the pulse interval; if the negative pulse is output, the square wave and pulse output low-level register fills in the number of clocks with low pulse width, and the square wave and pulse output high-level register fills in the number of clocks with pulse interval;

step C5, configuring a square wave and pulse output number register, wherein a bit 31 of the square wave and pulse output number register is '1' to indicate that square wave or pulse output is started, a bit 31 of the square wave and pulse output number register is '0' to indicate that square wave or pulse output is stopped, a bit 30 of the square wave and pulse output number register is '1' to indicate that the type of an output signal is square wave, a bit 30 of the square wave and pulse output number register is '0' to indicate that the type of the output signal is pulse, and bits 29 to 0 are output;

step C6, if square waves are to be output, configuring the bit 31 of the square wave and pulse output number register as '1', the bit 30 as '1', the bits 29 to 0 as 0, and simultaneously starting a timer, wherein the timer adds 1 on each clock rising edge; when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the output square wave signal is changed from low level to high level, and the timer is set to 1; when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the output square wave signal is changed from high level to low level, and the timer is set to be 1 at the same time, so that the required square wave signal can be generated after the circulation operation;

if the pulse is to be output, a bit 31 of a register for configuring the number of square waves and pulse outputs is '1', a bit 30 is '0', bits 29 to 0 are the number of pulses N, and simultaneously, a timer is started, and the timer is added with 1 on each clock rising edge; when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the output square wave signal is changed from low level to high level, and the timer is set to 1; when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the output square wave signal is changed from high level to low level, the timer is set to 1, and a counter is started at the same time, if the positive pulse is output currently, the counter adds 1 at the pulse falling edge moment, which indicates that a positive pulse is generated successfully; if the negative pulse is output currently, the counter adds 1 at the moment of the rising edge of the pulse to indicate that the negative pulse is generated once successfully, and when the value of the counter is equal to the number N of the pulses, the pulse generation is stopped.

Technical Field

The invention belongs to the technical field of signal detection, and particularly relates to a control system and a control method for multi-element signal generation and detection.

Background

In the existing signal generation and detection field, the design method of the traditional signal generation and detection control system is that a specific design scheme is adopted aiming at specific types of signals, and generally only the generation and detection of a single signal can be met, so that the application range is limited, and the portability is not high; if the external signal type changes, the control system needs to be redesigned, the redesign period is long, and the design efficiency is low.

The design method of the traditional signal generation and detection control system has certain defects, can only meet the generation and detection of a single signal, and is difficult to meet the application requirements of the generation and detection of complex multi-element signals. The disadvantages of this method are: (1) the signal control method is single, and only single signal generation and detection are supported; (2) fixed, non-configurable single signal types; (3) the universality is not strong, the functions are not perfect, the redesign period is long, the efficiency is low, and the cost is high.

Disclosure of Invention

Aiming at the universality of the use of level signals, pulse signals and square wave signals in various application fields and the diversity of application scenes, the invention provides a control system and a control method for generating and detecting multivariate signals, which support the comprehensive management and control of the generation and detection of the level signals, the pulse signals and the square wave signals and can cover the application requirements of various scenes.

In order to achieve the purpose, the control system for generating and detecting the multi-element signal comprises a bus interface module, wherein 2-3 control modules are connected to the bus interface module in a bidirectional mode, and each control module is used for controlling 32 configurable input signals and output signals;

the control module comprises a register control module, an input signal filtering module, a square wave and pulse generation control module and a square wave and pulse detection control module, and the register control module is bidirectionally connected with the bus interface module, the input signal filtering module, the square wave and pulse detection control module and the square wave and pulse generation control module; the input signal filtering module is bidirectionally connected with the square wave and pulse detection control module;

the register control module is used for configuring the filtering parameters of the input signal filtering module, configuring the control parameters of the square wave and pulse detection control module and the square wave and pulse generation control module, and comprises an input signal filtering time register, an input signal filtering shielding register, a square wave measuring factor register, a common level output signal control register, a pulse output type register, an output control register, 32 square wave frequency measurement and pulse width measurement high level registers, 32 square wave frequency measurement and pulse width measurement low level registers, 32 square wave and pulse output high level registers, 32 square wave and pulse output low level registers and 32 square wave and pulse output number registers;

the input signal filtering module is used for filtering 32 paths of input signals; the square wave and pulse detection control module is used for measuring the frequency and the width of the square wave and the pulse of the 32 paths of input signals; the square wave and pulse generation control module is used for controlling 32 paths of square wave or pulse output signals.

Further, the input signal filtering time register is used for configuring a filtering time parameter; the input signal filtering and shielding register is used for shielding or opening a filtering function; the square wave measuring factor register is used for measuring the number of continuous square wave periods when square wave frequency measurement is configured and is used for averaging; when the channel corresponding to the output control register is configured to output the ordinary level signal, the corresponding bit of the register writes '0', the corresponding channel outputs low level, the corresponding bit writes '1', and the corresponding channel outputs high level; the pulse output type register is used for configuring the type of pulse output; the output control register is used for controlling the type of the output signal; the square wave frequency measurement and pulse width measurement high-level register is used for recording the width and the overtime state of the high level of the input signal; the square wave frequency measurement and pulse width measurement low-level register is used for recording the width and the overtime state of the low level of the input signal; the square wave and pulse output high-level register is used for configuring the width of a high level; the square wave and pulse output low-level register is used for configuring the width of a low level; and the square wave and pulse output number register is used for configuring the number of output pulses, configuring whether the output is a square wave or a pulse and starting the square wave or pulse output.

Furthermore, the register control module also comprises an input signal rising edge counting register, an input signal falling edge counting register, an output signal rising edge counting register and an output signal falling edge counting register; the input signal rising edge counting register is used for recording the number of rising edges of the input signal; the input signal falling edge counting register is used for recording the number of times of the falling edge of the input signal; the output signal rising edge counting register is used for recording the number of times of the rising edge of the output signal; the output signal falling edge counting register is used for recording the number of times of the falling edge of the output signal.

Furthermore, the register control module also comprises an input signal rising edge interrupt enabling register, an input signal falling edge interrupt enabling register, an input signal rising edge interrupt state register and an input signal falling edge interrupt state register; the input signal rising edge interrupt enabling register is used for enabling rising edge interrupt, and when the input signal changes along a rising edge, an interrupt signal is generated; the input signal falling edge interrupt enabling register is used for enabling falling edge interrupt, and when the input signal has falling edge change, an interrupt signal is generated; the interrupt state register of the rising edge of the input signal, is used for recording the interrupt state of the rising edge, when the processor detects the interrupt, read the value of the interrupt state register, interrupt used for confirming which input signal produces; the input signal falling edge interrupt state register is used for recording the falling edge interrupt state, and when the processor detects the interrupt, the value of the interrupt state register is read to determine which input signal generates the interrupt.

Further, the register control module further comprises an input signal state register, and the input signal state register is used for recording the high level or low level state of the input signal.

Furthermore, the register control module further comprises a soft reset register, and the soft reset register is used for resetting the values of all the registers.

Furthermore, the register control module further comprises an input and output self-loop enable register, and the input and output self-loop enable register is used for configuring the input signal and the output signal internal self-loop.

A filtering method with adjustable filtering width based on the control system comprises the following steps:

step A1, configuring an input signal filtering shielding register, when the corresponding bit of the input signal filtering shielding register is '1', not filtering the corresponding input channel signal, and when the corresponding bit is '0', filtering the corresponding input channel signal;

step A2, configuring a filtering parameter of an input signal filtering time register according to the filtering time of the input signal, wherein the filtering parameter is the filtering time/the clock signal period used by the filtering function;

step A3, a timer is arranged in the input signal filtering module, when the continuous two sampling results of the input signal are the same, the timer is added with 1, when the continuous two sampling results are different, the timer is set to be 1, when the value of the timer reaches the value of the filtering parameter configured in the step A2, the input signal is considered to be valid, otherwise, the input signal is considered to be invalid, and then invalid signals are filtered.

A square wave frequency measurement and pulse width measurement control method based on the control system comprises the following steps:

step B1, configuring the square wave measurement factor configuration register as N;

step B2, start two timers in the square wave and pulse detection control modules:

when the square wave frequency measurement is carried out, the first timer is used for recording the time T1 of the high level of the continuous N square wave periodic signals, and the second timer is used for recording the time T2 of the low level of the continuous N square wave periodic signals; latching the time T1 of the first timer in a square wave frequency measurement and pulse width measurement high-level register at the falling edge of the Nth square wave periodic signal; latching the time T2 of the second timer in a square wave frequency measurement and pulse width measurement low-level register at the rising edge of the Nth square wave periodic signal;

when the pulse width is measured, the first timer is used for recording the time of the high level of the latest positive pulse signal, and the second timer is used for recording the time of the low level of the latest 1 negative pulse signal; latching the time T1 of a first timer in a square wave frequency measurement and pulse width measurement high-level register at the falling edge of a positive pulse signal; at the rising edge of the negative pulse signal, the time T2 of the second timer is latched in a square wave frequency measurement and pulse width measurement low-level register;

step B3, when the tested signal has no rising edge and falling edge change within the set time, returning to the overtime state, and under the overtime state, the square wave frequency measurement or pulse width measurement is invalid;

b4, acquiring a value T1 of a square wave frequency measurement and pulse width measurement high level register and a value T2 of a square wave frequency measurement and pulse width measurement low level register; when square wave frequency measurement is carried out, if the bit 31 of T1 is '0' and the bit 31 of T2 is '0', the square wave frequency measurement is considered to be effective; when the pulse width is measured, if the bit 31 of the T1 is '0', the positive pulse width is considered to be effective, and if the bit 31 of the T2 is '0', the negative pulse width is considered to be effective;

step B5, when measuring the frequency of the square wave, the square wave period is (number of high level clocks + number of low level clocks)/N × clock period, the square wave duty ratio is number of high level clocks/(number of high level clocks + number of low level clocks), and the frequency of the square wave is 1/square wave period; when the pulse width is measured, the positive pulse width is equal to the number of high-level clocks and the negative pulse width is equal to the number of low-level clocks and the clock period.

A control method for generating square waves and pulses based on the control system comprises the following steps:

step C1, configuring an output control register, and writing '1' in a certain bit to indicate that a square wave or pulse is to be output by a corresponding output channel;

step C2, configuring a square wave and pulse output high-level register and a square wave and pulse output low-level register, wherein the registers are filled with clock numbers, and the clock period is marked as T;

step C3, if a square wave is to be output, calculating a square wave period, and then calculating a square wave high level width and a square wave low level width, where the square wave period is 1/square wave frequency, the square wave high level width is a square wave period duty ratio, the square wave low level width is a square wave period-square wave high level width, the values of the square wave and pulse output high level registers are square wave high level widths/T, and the values of the square wave and pulse output low level registers are square wave low level widths/T;

step C4, if the pulse is to be output, the pulse width and the pulse interval are converted into the number of clocks, if the positive pulse is output, the square wave and pulse output high level register fills the number of clocks with the positive pulse width, and the square wave and pulse output low level register fills the number of clocks with the pulse interval; if the negative pulse is output, the square wave and pulse output low-level register fills in the number of clocks with low pulse width, and the square wave and pulse output high-level register fills in the number of clocks with pulse interval;

step C5, configuring a square wave and pulse output number register, wherein the condition that the square wave or pulse output is started when the bit 31 of the square wave and pulse output number register is '1', the condition that the square wave or pulse output is stopped when the bit 31 is '0', the condition that the output signal type is a square wave when the bit 30 is '1', the condition that the output signal type is a pulse when the bit 30 is '0', and the condition that the number of pulses are output from bit 29 to bit 0;

step C6, if square waves are to be output, configuring the bit 31 of the square wave and pulse output number register as '1', the bit 30 as '1', the bits 29 to 0 as 0, and simultaneously starting a timer, wherein the timer adds 1 on each clock rising edge; when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the output square wave signal is changed from low level to high level, and the timer is set to 1; when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the output square wave signal is changed from high level to low level, and the timer is set to be 1 at the same time, so that the required square wave signal can be generated after the circulation operation;

if the pulse is to be output, a bit 31 of a register for configuring the number of square waves and pulse outputs is '1', a bit 30 is '0', bits 29 to 0 are the number of pulses N, and simultaneously, a timer is started, and the timer is added with 1 on each clock rising edge; when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the output square wave signal is changed from low level to high level, and the timer is set to 1; when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the output square wave signal is changed from high level to low level, the timer is set to 1, and a counter is started at the same time, if the positive pulse is output currently, the counter adds 1 at the pulse falling edge moment, which indicates that a positive pulse is generated successfully; if the negative pulse is output currently, the counter adds 1 at the moment of the rising edge of the pulse to indicate that the negative pulse is generated once successfully, and when the value of the counter is equal to the number N of the pulses, the pulse generation is stopped.

Compared with the prior art, the invention has at least the following beneficial technical effects:

the invention is provided with 2-3 groups of control modules which respectively control and complete the control of a group of 32 configurable input and output signals, and realize the functions of at least 64-path input signal detection and at least 64-path output signal generation in a parameter configuration mode; the square wave measuring factor register is matched with the square wave frequency measuring and pulse width measuring high-level register to realize the square wave input frequency measuring function; the number of high-level clocks and the number of low-level clocks collected by the square wave frequency measurement and pulse width measurement high-level register and the square wave frequency measurement and pulse width measurement low-level register can be used for calculating the duty ratio and the pulse input signal width measurement. And the filtering function with configurable filtering width is realized by configuring the filtering parameters in the input signal filtering module. The output signal type configurable function is realized by configuring the numerical value of the corresponding bit in the output control register, and the output signal type configurable function can be configured into level output, square wave output or pulse output. The system supports the detection and the generation of multi-element signals, and has rich functions and wide application range.

Furthermore, the register control module comprises an input signal rising edge counting register, an input signal falling edge counting register, an output signal rising edge counting register and an output signal falling edge counting register, and supports the input signal edge counting function and the output signal edge counting function.

Furthermore, the register control module comprises an input signal rising edge interrupt enabling register, an input signal falling edge interrupt enabling register, an input signal rising edge interrupt state register and an input signal falling edge interrupt state register, and supports an edge interrupt triggering function.

Furthermore, the register control module further comprises an input signal state register, and the input signal state register is used for recording the high and low level states of the input signal after filtering (or without filtering) and supporting level input state detection.

Furthermore, the register control module further comprises an input/output self-loop enable register, and the input/output self-loop enable register is used for configuring the internal self-loop of the input signal and the output signal and is used for the self-checking function.

A filtering method with adjustable filtering width is to configure parameters of an input signal filtering shielding register and an input signal filtering time register in a register control module to realize the filtering function with adjustable filtering width, the number of sampling points of filtering is increased along with the increase of the filtering width, sampling is carried out on the rising edge of each clock, once the level change of a signal is found, the filtering time is re-timed, and the level signal is considered to be effective until the level of all sampling points in the filtering time is consistent, so the filtering method is very strict.

The square wave frequency measurement and pulse width measurement control method is characterized in that parameters of a square wave measurement factor register, a square wave frequency measurement register and a pulse width measurement high-level register are configured, so that the square wave frequency measurement and pulse width measurement are realized, the operation is convenient, the measurement real-time performance is high, the precision is high (nanosecond level), and the measurement pattern is wide (0.5 Hz-50 MHz).

A control method for generating square waves and pulses is characterized in that parameters of an output control register, a square wave and pulse output high-level register and a square wave and pulse output low-level register are configured to generate required square waves and pulses, and the operation is simple and convenient; the square wave period and the duty ratio are adjustable, the positive and negative polarities of the pulses are configurable, the pulse width is configurable, the number of the pulses is configurable, and the precision is high (nanosecond level).

The invention also has the function of self-checking input and output signals, namely, the square wave or pulse signal generated by a control method for generating the square wave and the pulse is connected to the input end through the internal self-loop arrangement, the square wave frequency measurement and the pulse width measurement are carried out by a control method for measuring the frequency and the pulse width of the square wave, and the rising edge and the falling edge of the input signal are counted, thus achieving the function of self-checking.

Drawings

FIG. 1 is a block diagram of a control system for multivariate signal generation and detection;

FIG. 2 is a schematic diagram of an exemplary application of a control system for multivariate signal generation and detection;

fig. 3 is a diagram of the effect of the filtering function.

In the drawings: 101. the device comprises a bus interface module, a 102a, a first register control module, a 102b, a second register control module, a 103a, a first input signal filtering module, a 103b, a second input signal filtering module, a 104a, a first square wave and pulse detection control module, a 104b, a second square wave and pulse detection control module, a 105a, a first square wave and pulse generation control module, and a 105b, a second square wave and pulse generation control module.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

A control system and a control method for multi-element signal generation and detection are provided, which comprises the following steps: (1) the self-defined on-chip bus interface can configure related parameters; (2) realizing a filtering method with adjustable width by a parameter configuration mode; (3) the functions of square wave frequency measurement and pulse width measurement of up to 64 paths of input signals are supported, and each path of input signal can be configured with a required function according to the requirement; (4) and up to 64 configurable output signals are supported, and each output signal can be configured into level output, square wave output and pulse output.

Referring to fig. 1, a control system for multi-element signal generation and detection mainly comprises 9 basic modules, and specifically comprises: the device comprises a bus interface module 101, a first register control module 102a, a second register control module 102b, a first input signal filtering module 103a, a second input signal filtering module 103b, a first square wave and pulse detection control module 104a, a second square wave and pulse detection control module 104b, a first square wave and pulse generation control module 105a and a second square wave and pulse generation control module 105 b. Because the on-chip bus interface is a 32-bit data bus, only a 32-bit register can be accessed each time, and in order to design up to 64 configurable input and output signal controls, two groups of same control modules are designed, wherein one group of control modules consists of a first register control module 102a, a first input signal filtering module 103a, a first square wave and pulse detection control module 104a and a first square wave and pulse generation control module 105a, and the control of one group of 32 configurable input and output signals is completed; and the other group is composed of a second register control module 102b, a second input signal filtering module 103b, a second square wave and pulse detection control module 104b and a second square wave and pulse generation control module 105b, and the control of the other group of 32-path configurable input and output signals is completed. The design has the advantage of convenient expansion, the control of the current 64 configurable input and output signals can meet most requirements, and if more channels need to be expanded, one or more groups of control modules can be added.

Wherein: the first register control module 102a is bidirectionally connected with the bus interface module 101, the first input signal filtering module 103a, the first square wave and pulse detection control module 104a and the first square wave and pulse generation control module 105a, and the first input signal filtering module 103a is bidirectionally connected with the first square wave and pulse detection control module 104 a; the second register control module 102b is bidirectionally connected to the bus interface module 101, the second input signal filtering module 103b, the second square wave and pulse detection control module 104b, and the second square wave and pulse generation control module 105b, and the second input signal filtering module 103b is bidirectionally connected to the second square wave and pulse detection control module 104 b.

The bus interface module 101 uses a custom on-chip bus through which the processor can configure the relevant parameters in the system.

The first register control module 102a and the second register control module 102b are multiplexed for 2 times, the first register control module 102a and the second register control module 102b have the same structure, each register control module comprises an input signal state register, an input signal filtering time register, an input signal filtering shielding register, an input and output self-loop enable register, an input signal rising edge interrupt enable register, an input signal falling edge interrupt enable register, an input signal rising edge interrupt state register, an input signal falling edge interrupt state register, a square wave measurement factor register, a common level output signal control register, a pulse output type register, an output control register, a soft reset register, 32 input signal rising edge count registers, 32 input signal falling edge count registers, 32 square wave frequency measurement and pulse width measurement high level registers, 32 square wave frequency measurement and pulse width measurement low-level registers, 32 output signal rising edge counting registers, 32 output signal falling edge counting registers, 32 square wave and pulse output high-level registers, 32 square wave and pulse output low-level registers and 32 square wave and pulse output number registers, and 301 registers are provided in total for each module.

The input signal state register is used for recording high and low level states of an input signal after filtering (or not filtering); the input signal filtering time register is used for configuring filtering time parameters; the input signal filtering and shielding register is used for shielding or opening a filtering function; the input/output self-loop enable register is used for configuring an input signal and an output signal internal self-loop and is used for self-checking function; the input signal rising edge interrupt enabling register is used for enabling rising edge interrupt, and when the input signal changes along a rising edge, an interrupt signal can be generated; the input signal falling edge interrupt enabling register is used for enabling falling edge interrupt, and when the input signal has falling edge change, an interrupt signal can be generated; the interrupt state register of rising edge of the input signal, is used for recording the interrupt state of rising edge, when the processor detects the interrupt, will read the value of the interrupt state register, is used for confirming which one input signal produces the interrupt, the state is cleared after reading, when all interrupt states are cleared, the interrupt signal will cancel too; the input signal falling edge interrupt state register is used for recording the falling edge interrupt state, when the processor detects the interrupt, the value of the interrupt state register is read to determine which path of input signal generates the interrupt, the state is read and then cleared, and when all interrupt states are cleared, the interrupt signal is also cancelled; the square wave measurement factor register is used for measuring the number of continuous square wave periods when square wave frequency measurement is configured, and is used for averaging to improve the measurement precision; when the channel corresponding to the output control register is configured to output the ordinary level signal, the corresponding bit of the register writes '0', the corresponding channel outputs low level, the corresponding bit writes '1', and the corresponding channel outputs high level; the pulse output type register is used for configuring the type of pulse output, the corresponding bit is written with '0' to indicate that the corresponding channel output is a positive pulse, the invalid state is a low level, the corresponding bit is written with '1' to indicate that the corresponding channel output is a negative pulse, and the invalid state is a high level; the output control register is used for writing '0' to a corresponding bit to indicate that the corresponding output channel outputs a common level signal, and writing '1' to the corresponding bit to indicate that the corresponding output channel outputs a square wave or pulse signal; a soft reset register for resetting the values of all registers; the input signal rising edge counting register is used for recording the number of times of the rising edge of the input signal, and when the rising edge change of the input signal is detected, the register is added with 1; the input signal falling edge counting register is used for recording the number of times of the falling edge of the input signal, and when the falling edge change of the input signal is detected, the register is added with 1; the output signal rising edge counting register is used for recording the number of times of the rising edge of the output signal, and when the rising edge change of the output signal is detected, the register is added with 1; the output signal falling edge counting register is used for recording the number of times of the falling edge of the output signal, and when the falling edge change of the output signal is detected, the register is added with 1; the square wave frequency measurement and pulse width measurement high-level register is used for recording the width and the overtime state of the high level of the input signal; the square wave frequency measurement and pulse width measurement low-level register is used for recording the width and the overtime state of the low level of the input signal; a square wave and pulse output high level register, which configures the width of high level, and the configuration parameter is the number of clocks; the square wave and pulse output low level register is used for configuring the width of a low level, and the configuration parameter is the number of clocks; the register is only effective when the corresponding bit of the output control register is set to be 1, the number of bits 29 to 0 of the register represents the threshold number of square wave and pulse output, when the bit 30 is 1, the register represents that the square wave is output and the output is not stopped, when the bit 0 represents that the pulse is output, when the number of the pulse output reaches the number of the bits 29 to 0, the pulse stops output, the bit 31 automatically clears 0, when the bit 31 of the register is 1, the register represents that the square wave and pulse output is started, and when the bit 0 represents that the square wave and pulse output is stopped.

The first input signal filtering module 103a and the second input signal filtering module 103b have the same structure, and are multiplexed for 2 times, and each module supports the filtering function of 32 input signals. Each input signal filtering module is provided with a timer, each path of input signal filtering function needs to generate a filtering clock through the configuration parameters of the register control module connected with the input signal filtering module, when the filtering parameter is set to 1000, when input signals acquired by the clock for 1000 times continuously are all low level, the low level is considered to be effective, or when the input signals acquired by the clock for 1000 times continuously are all high level, the high level is considered to be effective.

The first square wave and pulse detection control module 104a and the second square wave and pulse detection control module 104b have the same structure, are multiplexed for 2 times, and each module supports the square wave frequency measurement and pulse width measurement functions of 32 paths of input signals. Each square wave and pulse detection control module is provided with two timers for timing high and low levels respectively, when the square wave measurement factor register is set to be N, the time of N high levels and the number of clocks of N low levels are continuously recorded, the clock period is 10 nanoseconds, the number of high level timing clocks is latched on a falling edge, the number of high level timing clocks is stored in a square wave frequency measurement and pulse width measurement high level register, the number of low level timing clocks is latched on a rising edge, the number of low level timing clocks is stored in a square wave frequency measurement and pulse width measurement low level register, a processor reads the square wave frequency measurement and pulse width measurement high level register and the square wave frequency measurement and pulse width measurement low level register through driving software to obtain the number of high level clocks and the number of low level clocks, the period and the duty ratio of the square wave or the width of the pulse can be calculated, and the square wave period (unit: the number of the high level clocks plus the number of the low level clocks)/N10 nanoseconds is obtained, the square wave duty ratio is equal to the number of high-level clocks/(the number of high-level clocks + the number of low-level clocks), the frequency of the square wave is equal to 1/the square wave period, the positive pulse width is equal to the number of high-level clocks 10 nanoseconds, and the negative pulse width is equal to the number of low-level clocks 10 nanoseconds. The module supports square wave or pulse measurement with frequency of more than 0.5Hz, the period is 2 seconds at most, therefore, timeout time of 2 seconds is set in the module, when the signal does not jump on the rising edge or the falling edge within 2 seconds, the timer is cleared and returns to the timeout state, and when the software acquires the timeout state, the current input signal is considered to be an abnormal square wave or an abnormal pulse signal. Therefore, the high level time and the low level time of the square wave frequency measurement do not exceed 2 seconds, the high level width does not exceed 2 seconds when the positive pulse is used for measuring the width, and the low level width does not exceed 2 seconds when the negative pulse is used for measuring the width.

The first square wave and pulse generation control module 105a and the second square wave and pulse generation control module 105b have the same structure, each square wave and pulse detection control module is provided with a counter and two timers and is multiplexed for 2 times, and each square wave and pulse generation control module supports the control function of 32 paths of square wave or pulse output signals. The processor sets a relevant register in the register control module through driving software to realize parameter configuration of the pulse generation control module; in an output control register in the register control module, writing '0' in a corresponding bit indicates that a corresponding channel outputs a common level, and writing '1' in the corresponding bit indicates that the corresponding channel outputs a square wave or a pulse; configuring a pulse output type register, writing '0' to a corresponding bit to indicate that the output of a corresponding channel is a positive pulse, writing '1' to the corresponding bit to indicate that the output of the corresponding channel is a negative pulse, and writing the output of the corresponding bit to indicate that the output of the corresponding channel is a high level; configuring a square wave and pulse output high-level register, and determining the number of square wave or pulse output high-level clocks; configuring a square wave and pulse output low-level register, and determining the number of square wave or pulse output low-level clocks; if the common level needs to be output, the value of the corresponding bit of the register is controlled by setting the common level output signal, so that the corresponding output channel outputs the corresponding level, if the corresponding bit is written with '0', the corresponding channel outputs the low level, and if the corresponding bit is written with '1', the corresponding channel outputs the high level; if square wave or pulse is required to be output, the number register for outputting square wave and pulse is configured to configure the number of output pulses, configure whether the output is square wave or pulse and start square wave or pulse output, the register is only effective when the corresponding bit of the output control register is set to be ' 1 ', the number of the threshold values of the square wave and pulse output is represented by bits 29 to 0 of the register, when the bit 30 is ' 1 ', the square wave is represented to be output and not to be stopped, when the bit 0 is represented by ' 0 ', the pulse is stopped to be output and 31 bits are automatically cleared to be ' 0 ', when the bit 31 of the register is ' 1 ', the square wave and pulse output is started, and when the bit 0 ' is represented to be stopped to be square wave and pulse output.

Fig. 2 is an application example of a control system for multi-element signal generation and detection, which is implemented in an FPGA through Verilog code, and a bridge module is implemented inside the FPGA and connects the system with an external processor, and driver software of the system needs to be developed and run on the processor so as to control the system to work normally.

According to the disclosure of the present invention, a filtering method with adjustable filtering width is described in detail, which is implemented in the first input signal filtering module 103a and the second input signal filtering module 103b in fig. 1, and fig. 3 is an effect diagram of the filtering function.

A filtering method with adjustable filtering width comprises the following steps:

(1) the processor configures an input signal filtering shielding register through driving software, when the corresponding bit of the input signal filtering shielding register is '1', the corresponding input channel signal is not filtered, and when the corresponding bit is '0', the corresponding input channel signal needs to be filtered;

(2) the processor configures an input signal filtering time register through driving software, a clock signal used by the filtering function is a 10 nanosecond period, if the input signal needs to be filtered for 10000 nanoseconds, the filtering parameter of the register is configured to 1000, the number of 1000 clocks is represented, and the calculation formula is that the filtering parameter is filtering time (nanosecond)/10 nanoseconds;

(3) a timer is arranged in the input signal filtering module, when the two consecutive sampling results of the input signal are the same, the timer is added with 1, and when the two consecutive sampling results are different (the two sampling results are that the signal before filtering and the signal before filtering in fig. 3 are delayed by 1 clock signal), the timer is set with 1; when the value of the timer reaches the value of the input signal filtering time register (when the filtering time is 10000 ns, the register value is 1000), the input signal is considered to be valid, otherwise, the input signal is considered to have no change, the previous value is maintained, that is, the input signal is considered to be valid only if the input signal keeps 1000 clocks unchanged, in fig. 3, the signal with the time width equal to 1000 clocks is a valid signal, the signal with the time width equal to 999 clocks is an invalid signal, and the invalid signal is filtered.

According to the present invention, a method for controlling square wave frequency measurement and pulse width measurement is described in detail, and is implemented in a first square wave and pulse detection control module 104a and a second square wave and pulse detection control module 104b in fig. 1.

A control method for measuring frequency and width of pulse by square wave comprises the following steps:

(1) the processor configures a square wave measurement factor register into N through driving software;

(2) when measuring the frequency of the square wave, starting two timers in a square wave and pulse detection control module, wherein the timer 1 is used for recording the high-level time T1 of continuous N square wave periodic signals, and the timer 2 is used for recording the low-level time of the continuous N square wave periodic signals; at the falling edge of the signal of the Nth square wave period, the time T1 of the timer 1 is latched in a 32-bit square wave frequency measurement and pulse width measurement high-level register, at the rising edge of the signal of the Nth square wave period, the time T2 of the timer 2 is latched in a 32-bit square wave frequency measurement and pulse width measurement low-level register, T1 and T2 are represented by the number of clocks, and the clock period is 10 nanoseconds;

(3) when the pulse width is measured, two timers are started internally, the timer 1 is used for recording the time of the high level of the latest 1 positive pulse signal, the timer 2 is used for recording the time of the low level of the latest 1 negative pulse signal, the time T1 of the timer 1 is latched in a 32-bit square wave frequency measurement and pulse width measurement high level register at the falling edge of the positive pulse signal, the time T2 of the timer 2 is latched in a 32-bit square wave frequency measurement and pulse width measurement low level register at the rising edge of the negative pulse signal, the T1 and the T2 are clock numbers, and the clock period is 10 nanoseconds;

(4) when the signal does not change in rising edge and falling edge within 2 seconds, the signal returns to a timeout state, and in the timeout state, the bit 31 of the T1 time register is '1' or the bit 31 of the T2 time register is '1', which indicates that square wave frequency measurement or pulse width measurement is invalid;

(5) the processor obtains the value of a square wave frequency measurement and pulse width measurement high level register T1 and the value of a square wave frequency measurement and pulse width measurement low level register T2 through driving software, and during square wave frequency measurement, if a bit 31 of T1 is '0' and a bit 31 of T2 is '0', the square wave frequency measurement is considered to be effective; when the pulse width is measured, if the bit 31 of the T1 is '0', the positive pulse width is considered to be effective, and if the bit 31 of the T2 is '0', the negative pulse width is considered to be effective;

(6) when the square wave is measured, the frequency and the duty ratio of the square wave can be calculated through a calculation formula, wherein the square wave period (unit: nanosecond) is (number of high-level clocks + number of low-level clocks)/N + 10 nanoseconds, the square wave duty ratio is number of high-level clocks/(number of high-level clocks + number of low-level clocks), the frequency of the square wave is 1/square wave period, if N is 10, T1 is 10000, T1 is 30000, the square wave period is 40000 nanoseconds, the square wave frequency is 25000Hz, and the square wave duty ratio is 25% (the conversion of the unit is not explained here);

(7) when the pulse width is measured, the pulse width can be calculated through a calculation formula, and the positive pulse width measurement formula is as follows: positive pulse width (unit: nanosecond) is 10 nanoseconds times high level clock, and negative pulse width measurement formula: the negative pulse width (unit: ns) — 10 ns for low level clocks, and if T1 ═ 10000 and T2 ═ 30000, the positive pulse width is 100000 ns and the negative pulse width is 300000 ns (the unit conversion is not described here).

In accordance with the teachings of the present invention, a method of controlling square wave and pulse generation is detailed, and is implemented in a first square wave and pulse generation control module 105a and a second square wave and pulse generation control module 105b in fig. 1.

A control method for square wave and pulse generation is as follows:

(1) the processor configures an output control register through driving software, and writes '1' to a corresponding bit, which indicates that a square wave or a pulse is to be output by a corresponding output channel;

(2) the processor configures a square wave and pulse output high-level register and a square wave and pulse output low-level register through driving software, wherein the registers are filled with clock numbers, and the clock period is 10 nanoseconds;

(3) if the square wave frequency is 10000Hz and the duty ratio is 30%, the square wave period is calculated first, the square wave period is 1/the square wave frequency is 100000 nanoseconds, then the square wave high level width and the square wave low level width are calculated, the square wave high level width is the square wave period and the duty ratio is 30000 nanoseconds, the square wave low level width is the square wave period and the square wave high level width is 70000 nanoseconds, the value of the square wave and pulse output high level register is 3000 which is the square wave high level width, and the value of the square wave and pulse output low level register is 7000 which is the square wave low level width/10 nanoseconds (the conversion of the unit is not explained here);

(4) if the pulse width is 100000 nanoseconds and the pulse interval is 10000000 nanoseconds, the number of clocks for converting the pulse width into a 10 nanosecond period is 100000 nanoseconds/10 nanoseconds which is 10000, the pulse interval is respectively converted into a 10 nanosecond period which is 10000000 nanoseconds/10 nanoseconds which is 1000000, if a positive pulse is to be output, the square wave and pulse output high level register fills in the number of clocks for filling the positive pulse width of 10000, and the square wave and pulse output low level register fills in the number of clocks for filling the pulse interval of 1000000; if negative pulses are to be output, the square wave and pulse output low-level register fills in 10000 clocks with low pulse width, and the square wave and pulse output high-level register fills in 1000000 clocks with pulse interval;

(5) the processor configures a square wave and pulse output number register through driving software, wherein the register is a 32-bit wide register, a bit 31 is '1' to indicate that square wave or pulse output is started, a bit 31 is '0' to indicate that square wave or pulse output is stopped, a bit 30 is '1' to indicate that the type of an output signal is square wave, a bit 30 is '0' to indicate that the type of the output signal is pulse, and bits 29 to 0 are the number of output pulses;

(6) if a square wave is to be output, a square wave and pulse output number register is configured to be 0xC000000, namely a bit 31 is '1' and a bit 30 is '1', a bit 29 to a bit 0 are 0, a timer is started at the same time, the timer can add 1 on each clock rising edge, when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the square wave signal is output to be changed from low level to high level, the timer is set to be 1, when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the square wave signal is output to be changed from high level to low level, the timer is set to be 1, and the operation is circulated, so that the required square wave signal can be generated;

(7) if a pulse is to be output, the registers for outputting the square waves and the pulses are configured to be 0x8000008, that is, the bit 31 is "1" and the bit 30 is "0", and the bits 29 to 0 are 8, and simultaneously, a timer is started, and the timer will add 1 on each clock rising edge; when the output level is low level and the value of the timer is equal to the value of the square wave and pulse output low level register, the output square wave signal is changed from low level to high level, and the timer is set to 1; when the output level is high level and the value of the timer is equal to the value of the square wave and pulse output high level register, the output square wave signal is changed from high level to low level, and the timer is set to 1; and simultaneously starting a counter, if the positive pulse is output currently, adding 1 to the counter at the pulse falling edge time to indicate that the positive pulse is generated once successfully, if the negative pulse is output currently, adding 1 to the counter at the pulse rising edge time to indicate that the negative pulse is generated once successfully, and stopping generating the pulse when the value of the counter is equal to the pulse number 8 (the pulse number is the value from bit 29 to bit 0).

The filtering method with adjustable filtering width, the control method for measuring frequency and pulse width of the square wave and the method for measuring frequency and pulse width of the square wave have the characteristics of good real-time performance, flexible function configuration, strong universality and wide application range, and can shorten the design period and reduce the design cost to a great extent.

According to the scheme, a logic design of a control system for generating and detecting the multi-element signals is described by using a Verilog HDL language, logic synthesis and layout wiring are completed, the controller logic design is mapped into a programmable logic device to be realized, and the functions of the control system are tested. The test result shows that the invention has good implementability and the performance meets the expectation.

The design scheme of the invention has the advantages that: (1) the invention supports the functions of level input signal state detection, square wave input signal frequency measurement, pulse input signal width measurement, input signal rising edge counting and interruption, input signal falling edge counting and interruption, input and output signal self-checking and the like; (2) the invention supports the functions of level signal output, square wave signal output with adjustable period and duty ratio, and pulse output with adjustable pulse type, pulse width and pulse number; (3) the invention supports the filtering function with adjustable filtering width; (4) the invention can support the detection of 64 input signals and the generation of 64 output signals at most; (5) the invention has richer functions, strong universality and wide application range, and can shorten the design period and reduce the design cost to a great extent.

The invention has rich functional design and strong universality, can improve the design efficiency, can shorten the design period to a great extent, reduces the design cost and improves the design reliability.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.