Switching element and method for manufacturing the same
阅读说明:本技术 开关元件及其制造方法 (Switching element and method for manufacturing the same ) 是由 永冈达司 西中浩之 吉本昌广 于 2020-02-25 设计创作,主要内容包括:本发明抑制在具有上表面由(010)晶面构成的氧化镓基板的开关元件中的裂纹。本发明提供一种开关元件,其具有:氧化镓基板,其由氧化镓晶体构成;以及多个栅极,其隔着栅极绝缘膜与所述氧化镓基板相对。所述氧化镓基板的上表面与所述氧化镓晶体的(010)晶面平行。当俯视观察所述氧化镓基板的所述上表面时,各个所述栅极的长度方向与所述氧化镓晶体的(100)晶面延伸的方向相交。(The invention provides a switching element having a gallium oxide substrate whose upper surface is formed of a (010) crystal plane, wherein cracks are suppressed. The present invention provides a switching element, comprising: a gallium oxide substrate composed of a gallium oxide crystal; and a plurality of gate electrodes facing the gallium oxide substrate with a gate insulating film interposed therebetween. The upper surface of the gallium oxide substrate is parallel to the (010) crystal plane of the gallium oxide crystal. When the upper surface of the gallium oxide substrate is viewed in plan, the length direction of each gate intersects with the direction in which the (100) plane of the gallium oxide crystal extends.)
1. A kind of switching element is disclosed, which has a high-voltage power supply,
it has the following components:
a gallium oxide substrate composed of a gallium oxide crystal; and
a plurality of gate electrodes facing the gallium oxide substrate with a gate insulating film interposed therebetween,
the upper surface of the gallium oxide substrate is parallel to the (010) crystal plane of the gallium oxide crystal,
when the upper surface of the gallium oxide substrate is viewed in plan, the length direction of each gate intersects with the direction in which the (100) plane of the gallium oxide crystal extends.
2. The switching element according to claim 1,
the upper surface of the gallium oxide substrate is provided with a plurality of grooves,
when the upper surface of the gallium oxide substrate is viewed in plan, the length direction of each of the trenches intersects with the direction in which the (100) crystal plane extends,
a plurality of the gates are disposed within the plurality of trenches.
3. The switching element according to claim 1 or 2,
the switching element further includes a gate plate disposed above the upper surface of the gallium oxide substrate and connected to each of the gates,
the gallium oxide substrate has:
a first side surface constituted by the (100) crystal plane; and
a second side surface constituted by a (001) plane of the gallium oxide crystal,
when the upper surface of the gallium oxide substrate is viewed in plan, the gate plate is disposed in a range between a straight line extending from a connection portion between the first side surface and the second side surface in a direction perpendicular to the second side surface and the first side surface.
4. The switching element according to claim 1 or 2,
the switching element further has:
a main electrode disposed above the upper surface of the gallium oxide substrate; and
a gate plate disposed above the upper surface of the gallium oxide substrate and connected to each of the gates,
the gallium oxide substrate has:
a third side surface parallel to the (100) crystal plane; and
a fourth side surface perpendicular to both of the (100) crystal plane and the (010) crystal plane,
when the upper surface of the gallium oxide substrate is viewed in plan view, the main electrode and the gate plate are arranged with a gap in the direction in which the (100) plane extends.
5. The switching element according to any one of claims 1 to 4,
when the upper surface of the gallium oxide substrate is viewed in plan, the length of the gallium oxide substrate in the direction perpendicular to the (100) crystal plane is shorter than the length of the gallium oxide substrate in the direction in which the (100) crystal plane extends.
6. A manufacturing method for manufacturing the switching element according to any one of claims 1 to 5, comprising the steps of:
a step of thinning a gallium oxide wafer, which is made of a gallium oxide crystal and has a diameter of 2 inches or more, by polishing a surface of the gallium oxide wafer; and
and a step of manufacturing the switching element using the gallium oxide wafer.
Technical Field
The technology disclosed in the present specification relates to a switching element and a method for manufacturing the same.
Background
Patent document 1 discloses a switching element having a gallium oxide substrate. The switching element has a plurality of gates facing the gallium oxide substrate with a gate insulating film interposed therebetween.
Patent document 1: japanese patent laid-open publication No. 2016-164906
In the gallium oxide crystal, the thermal conductivity in the [010] direction is higher than the thermal conductivity in the other directions. Therefore, in the switching element, by forming the upper surface of the gallium oxide substrate to be a (010) crystal plane, heat can be efficiently radiated from the upper surface. On the other hand, in a gallium oxide crystal, cleavage easily occurs in the (100) crystal plane. Therefore, if the upper surface of the gallium oxide substrate is made to be the (010) crystal plane, there is a problem that the gallium oxide substrate is likely to crack along the (100) crystal plane (i.e., a plane perpendicular to the upper surface). In the present specification, a technique is proposed which suppresses the occurrence of cracks in a switching element having a gallium oxide substrate whose upper surface is composed of a (010) crystal plane.
Disclosure of Invention
The switching element disclosed in the present specification includes: a gallium oxide substrate composed of a gallium oxide crystal; and a plurality of gate electrodes facing the gallium oxide substrate with a gate insulating film interposed therebetween. The upper surface of the gallium oxide substrate is parallel to the (010) crystal plane of the gallium oxide crystal. When the upper surface of the gallium oxide substrate is viewed in plan, the length direction of each gate intersects with the direction in which the (100) plane of the gallium oxide crystal extends.
In the above switching element, since the upper surface of the gallium oxide substrate is parallel to the (010) crystal plane, the switching element can efficiently dissipate heat from the upper surface. In the above switching element, when the upper surface of the gallium oxide substrate is viewed in plan, the longitudinal direction of each gate electrode intersects with the direction in which the (100) crystal plane extends (i.e., the direction in which cracks are likely to occur). Since the gate electrode extends so as to intersect the direction in which the (100) crystal plane extends, the occurrence of cracks along the (100) crystal plane can be suppressed.
Drawings
Fig. 1 is a diagram showing a unit cell of a gallium oxide crystal.
Fig. 2 is a plan view of the switching element of embodiment 1.
Fig. 3 is a sectional view taken along the line III-III of fig. 2.
Fig. 4 is a plan view of a switching element of embodiment 2.
Fig. 5 is a sectional view taken along line V-V of fig. 4.
Fig. 6 is a plan view of a switching element of embodiment 3.
Fig. 7 is a sectional view taken along line VII-VII of fig. 6 (a sectional view of the switching element in a packaged state).
Detailed Description
First, a gallium oxide crystal will be explained. Fig. 1 shows a unit cell of a gallium oxide crystal. An angle γ between the crystal axis a and the crystal axis b and an angle α between the crystal axis b and the crystal axis c are 90 °. The angle β between the crystallization axis c and the crystallization axis a is 104 °. That is, the gallium oxide crystal is monoclinic. The length of the crystal axis a is about 1.22nm, the length of the crystal axis b is about 0.30nm, and the length of the crystal axis c is about 0.58 nm. In the gallium oxide crystal, cleavage easily occurs along a (100) crystal plane parallel to the crystal axis b and the crystal axis c. Therefore, cracks are likely to occur along the (100) crystal plane in the gallium oxide crystal. In addition, in the gallium oxide crystal, the thermal conductivity in the direction parallel to the crystal axis b is higher than the thermal conductivity in the other directions.
[ example 1]
Fig. 2 and 3 show a switching
As shown in fig. 3, a plurality of gate
As shown in fig. 3, each
As shown in fig. 3, each
The
The
Each
Each
Each
The
The
An n-channel type mosfet (metal oxide semiconductor field effect transistor) is formed from the
If the switching element 10 (i.e., MOSFET) is operated, the
As described above, in the gallium oxide crystal, cracks are likely to occur along the (100) crystal plane. For example, cracks are likely to occur along the (100) crystal plane from the
As shown in fig. 2, when
[ example 2]
Fig. 4 and 5 show a switching element 110 according to embodiment 2. The switching element 110 has a gallium oxide substrate 112. The gallium oxide substrate 112 is formed in a parallelogram plate shape. The gallium oxide substrate 112 has an upper surface 112a, a lower surface 112b, a side surface 112c, a side surface 112d, a side surface 112e, and a side surface 112 f. The upper surface 112a is constituted by a (010) crystal plane. The lower surface 112b is constituted by a (0-10) crystal plane. The side surface 112c is constituted by a (100) crystal plane. The side surface 112e is constituted by a (-100) crystal plane. The side surface 112d is constituted by a (001) crystal plane. The side surface 112f is constituted by a (00-1) crystal plane. That is, the side surface 112d and the side surface 112f are parallel to the (001) crystal plane.
As shown in fig. 5, a plurality of trenches 118 are provided on the upper surface 112a of the gallium oxide substrate 112. A gate insulating film 120 and a gate electrode 122 are provided in each trench 118. Further, a plurality of source electrodes 124 are provided on the upper surface 112a of the gallium oxide substrate 112. In fig. 4, the source 124 is not shown.
As shown in fig. 4, each trench 118 extends linearly in a direction in which the (001) crystal plane extends on the upper surface 112a of the gallium oxide substrate 112. The plurality of trenches 118 are arranged at intervals in a direction perpendicular to the (001) crystal plane. As shown in fig. 5, each gate insulating film 120 covers the inner surface of the trench 118. Each gate electrode 122 is disposed in trench 118 and covers the surface of gate insulating film 120. Each gate electrode 122 is insulated from the gallium oxide substrate 112 by a gate insulating film 120. That is, each gate electrode 122 faces the gallium oxide substrate 112 through the gate insulating film 120. Each gate 122 extends along a trench 118. That is, as shown in fig. 4, when the upper surface 112a of the gallium oxide substrate 112 is viewed in plan, each gate electrode 122 linearly extends along the direction in which the (001) crystal plane extends. In other words, when the upper surface 112a of the gallium oxide substrate 112 is viewed in plan, the longitudinal direction of each gate electrode 122 intersects the direction in which the (100) crystal plane extends (i.e., the direction of the crystal axis c). A gate wiring 140 and a gate plate 142 are provided on the upper surface 112a of the gallium oxide substrate 112. The gate wiring 140 and the gate plate 142 are insulated from the gallium oxide substrate 112 by an interlayer insulating film not shown. The gate wiring 140 is connected to an end of each gate 122 in the longitudinal direction. The gate wiring 140 connects each gate 122 to the gate plate 142.
Line 160 of fig. 4 shows a straight line extending from the connection portion 113 of the side surface 112c and the side surface 112d in a direction perpendicular to the side surface 112 d. Since the upper surface 112a of the gallium oxide substrate 112 is a parallelogram, a triangular region 162 exists between the straight line 160 and the side surface 112c when the upper surface 112a is viewed in plan. The gate plate 142 is disposed in the region 162 of the upper surface 112 a. It is difficult to form the gate 122 in the triangular region 162. For example, if the gate 122 is formed in the region 162, electric field concentration may occur near the gate 122 in the region 162. As shown in fig. 4, the gate electrode 122 is not provided in the region 162, whereby the withstand voltage of the switching element 110 can be increased. Further, by providing the gate plate 142 in the region 162, the region 162 can be efficiently used, and the switching element 110 can be downsized. In addition, a straight line 170 of fig. 4 shows a straight line extending from the connection portion 114 of the side surface 112e and the side surface 112f in a direction perpendicular to the side surface 112 f. When upper surface 112a is viewed from above, there is a triangular region 172 between line 170 and side surface 112 e. The gate plate 142 is disposed in the region 172 of the upper surface 112 a. By providing the gate plate 142 in the region 172, the region 172 can be efficiently used, and the switching element 110 can be downsized.
As shown in fig. 5, each source 124 is disposed between adjacent gates 122. Each source 124 is in contact with the upper surface 112a of the gallium oxide substrate 112.
The drain 126 is provided so as to be in contact with the lower surface 112b of the gallium oxide substrate 112. The drain 126 covers the entire lower surface 112b of the gallium oxide substrate 112.
The gallium oxide substrate 112 is provided inside with a plurality of source regions 130, a plurality of body contact regions 132, a body region 134, a drift region 136, and a drain region 138.
Each source region 130 is n-type and is disposed in a position in contact with the source 124 and the gate insulating film 120. Each source region 130 is in contact with the gate insulating film 120 at the upper end portion of the trench 118. Each source region 130 is in ohmic contact with the source 124.
Each body contact region 132 is p-type and is disposed below the source 124. Each body contact region 132 is in ohmic contact with the source electrode 124.
Each body region 134 is disposed under the source region 130 and the body contact region 132. Each body region 134 is p-type with a lower p-type impurity concentration than body contact regions 132. Each body region 134 is in contact with the gate insulating film 120 on the lower side of the source region 130.
The drift region 136 is n-type and is disposed below the body region 134. The drift region 136 is in contact with the gate insulating film 120 on the lower side of the body region 134. The drift region 136 is separated from the source region 130 by the body region 134.
The drain region 138 is n-type with a higher n-type impurity concentration than the drift region 136. A drain region 138 is disposed on the underside of the drift region 136. The drain region 138 is in ohmic contact with the drain 126.
An n-channel MOSFET is formed from the gate insulating film 120, the gate 122, the source 124, the drain 126, the source region 130, the body contact region 132, the body region 134, the drift region 136, and the drain region 138.
When the switching element 110 is operated, the gallium oxide substrate 112 generates heat. As described above, in the gallium oxide crystal, the thermal conductivity in the direction parallel to the crystal axis b is high. As described above, the upper surface 112a and the lower surface 112b of the gallium oxide substrate 112 are formed of a crystal plane parallel to the (010) crystal plane (i.e., a crystal plane perpendicular to the crystal axis b). Therefore, heat generated in the gallium oxide substrate 112 is easily conducted to the source 124 and the drain 126. Therefore, a temperature increase of the switching element 110 can be suppressed.
As described above, in the gallium oxide crystal, cracks are likely to occur along the (100) crystal plane. However, in the switching element 110 of embodiment 2, as shown in fig. 4, the plurality of gates 122 extend in a direction intersecting the direction in which the (100) crystal plane extends. Since the gallium oxide substrate 112 is reinforced by the gate electrode 122, the occurrence of cracks along the (100) crystal plane in the gallium oxide substrate 112 can be suppressed. Therefore, in the switching element 110 of embodiment 2, the occurrence of cracks in the gallium oxide substrate 112 can be suppressed during the use and the manufacturing process of the switching element 110.
[ example 3]
Fig. 6 and 7 show a
As shown in fig. 6, a plurality of gate electrodes 222 are provided in the
Fig. 7 shows a cross-sectional view of the
As shown in fig. 7, no electrode is provided at the
The switching elements of embodiments 1 to 3 were explained above. In addition, in the manufacturing process of the switching elements of examples 1 to 3, the switching elements can be manufactured using gallium oxide wafers having a diameter of 2 inches or more. In this case, a step of thinning the gallium oxide wafer by polishing the front surface (for example, the lower surface) of the gallium oxide wafer may be performed. Thus, when a gallium oxide wafer having a large diameter and a small thickness is used, cracks are more likely to occur in the gallium oxide wafer in the production process. In the above-described production process, by applying the crack-suppressing technique described in examples 1 to 3, cracks in the gallium oxide wafer can be suppressed efficiently.
The relationship between the components of the above embodiment and the components of the claims will be described below. Side 112c of embodiment 2 is an example of the first side of the claims. Side 112d of embodiment 2 is an example of the second side of the claims. The side surfaces 212c and 212e of embodiment 3 are an example of the third side surface of the claims. The side surfaces 212d and 212f of embodiment 3 are an example of the fourth side surface of the claims.
Technical elements disclosed in the present specification are listed below. The following technical elements are independently useful.
In the switching element of one example disclosed in the present specification, a plurality of trenches may be provided on the upper surface of the gallium oxide substrate. When the upper surface of the gallium oxide substrate is viewed in plan, the length direction of each trench may intersect the direction in which the (100) crystal plane extends. A plurality of gates may be disposed within the plurality of trenches.
With this configuration, cracks in the gallium oxide substrate can be suppressed in the switching element having the trench-type gate electrode.
The switching element of one example disclosed in the present specification may further include a gate plate disposed on an upper portion of the upper surface of the gallium oxide substrate and connected to each gate. In addition, the gallium oxide substrate may have a first side surface composed of a (100) crystal plane and a second side surface composed of a (001) crystal plane of the gallium oxide crystal. When the upper surface of the gallium oxide substrate is viewed in plan, the gate plate may be disposed in a range between a straight line extending from a connection portion between the first side surface and the second side surface in a direction perpendicular to the second side surface and the first side surface.
Since the gallium oxide crystal has a monoclinic crystal structure, if the first side face is made to form a (100) crystal plane and the second side face is made to form a (001) crystal plane, the angle between the first side face and the second side face will be greater than 90 °. Therefore, if a straight line extending from a connecting portion of the first side surface and the second side surface in a direction perpendicular to the second side surface is virtually provided when the upper surface of the gallium oxide substrate is viewed in plan, a triangular space is generated between the straight line and the first side surface. By providing the gate plate in this space, the space can be efficiently used.
The switching element of another example disclosed in the present specification may further include: a main electrode disposed on an upper portion of an upper surface of the gallium oxide substrate; and a gate plate disposed on an upper portion of the upper surface of the gallium oxide substrate and connected to each gate electrode. The gallium oxide substrate may have a third side surface parallel to the (100) plane and a fourth side surface perpendicular to both the (100) plane and the (010) plane. When the upper surface of the gallium oxide substrate is viewed in plan, the main electrode and the gate plate may be arranged with a space in the direction in which the (100) plane extends.
Stress is easily applied to the space between the main electrode and the gate electrode. If this spacing extends along the (100) crystal plane, the gallium oxide substrate will be susceptible to cracking at this spacing. As described above, if the upper-surface lower main electrode and the gate plate of the gallium oxide substrate are arranged with a gap therebetween in the direction in which the (100) plane extends in plan view, the gap between the main electrode and the gate plate extends in the direction intersecting the (100) plane. Therefore, the occurrence of cracks in the gallium oxide substrate at the gap can be suppressed.
In the switching element of one example disclosed in the present specification, when the upper surface of the gallium oxide substrate is viewed in plan, the length of the gallium oxide substrate in the direction perpendicular to the (100) crystal plane may be shorter than the length of the gallium oxide substrate in the direction parallel to the (100) crystal plane.
In this way, the gallium oxide substrate has a shape elongated in a direction parallel to the (100) crystal plane, and therefore the gallium oxide substrate is less likely to crack along the (100) crystal plane.
A method for manufacturing a switching element according to an example disclosed in the present specification may include: that is, a step of thinning a gallium oxide wafer, which is made of a gallium oxide crystal and has a diameter of 2 inches or more, by polishing a surface of the gallium oxide wafer; and a step of manufacturing a switching element using the gallium oxide wafer.
When a gallium oxide wafer having a large diameter is thinned as described above, the gallium oxide wafer is likely to be cracked in the process of manufacturing a switching element. By adopting any of the above-described structures of the switching element, cracking of the gallium oxide wafer in the manufacturing process can be suppressed.
The embodiments have been described in detail, but these are merely examples and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples described above. The technical elements described in the present specification or the drawings of the specification can exhibit their technical effects alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, although the technologies illustrated in the present specification or the drawings of the specification achieve a plurality of objects at the same time, there is a technical effect in that only one of the objects is achieved.