阅读说明：本技术 激光冲击制备亚纳米级沟道背电极场效应晶体管的方法 (Method for preparing sub-nanometer channel back electrode field effect transistor by laser shock ) 是由 胡耀武 程佳瑞 何亚丽 黄正 于 2020-05-06 设计创作，主要内容包括：本发明属于场效应晶体管领域,具体涉及一种激光冲击制备亚纳米级沟道背电极场效应晶体管的方法,包括以下步骤：(1)在一维或二维材料场效应晶体管的百纳米级背电极上铺设至少一层介电二维材料作为隔离层；(2)在隔离层表面覆盖两面平整的金属薄膜；(3)在金属薄膜表面覆盖固体透光层；(4)采用一定脉冲宽度、一定功率的脉冲激光垂直照射固体透光层一定时间；(5)去除金属薄膜及固体透光层,得到亚纳米级沟道背电极场效应晶体管。本发明操作要求简单,通过控制激光强度和曝光时间能够精确地减小沟道长度,提高晶体管的性能,降低功耗,突破摩尔定律带来的物理极限,实现大规模具有高电子性能和集成密度的场效应晶体管的生产。(The invention belongs to the field of field effect transistors, and particularly relates to a method for preparing a sub-nanometer channel back electrode field effect transistor by laser shock, which comprises the following steps: (1) laying at least one layer of dielectric two-dimensional material as an isolation layer on a hundred-nanometer back electrode of a one-dimensional or two-dimensional material field effect transistor; (2) covering a metal film with two smooth surfaces on the surface of the isolation layer; (3) covering a solid light-transmitting layer on the surface of the metal film; (4) vertically irradiating the solid euphotic layer for a certain time by adopting pulse laser with certain pulse width and certain power; (5) and removing the metal thin film and the solid euphotic layer to obtain the sub-nanometer channel back electrode field effect transistor. The invention has simple operation requirement, can accurately reduce the length of a channel by controlling the laser intensity and the exposure time, improve the performance of the transistor, reduce the power consumption, break through the physical limit brought by the moore's law and realize the production of the field effect transistor with high electronic performance and integrated density on a large scale.)

1. A method for preparing a sub-nanometer channel back electrode field effect transistor by laser shock is characterized by comprising the following steps:

(1) laying a dielectric two-dimensional material as an isolation layer on a hundred-nanometer back electrode of a one-dimensional or two-dimensional material field effect transistor;

(2) covering a metal film with two flat surfaces on the surface of the isolation layer;

(3) covering a solid light-transmitting layer on the surface of the metal thin film;

(4) vertically irradiating the solid euphotic layer for a certain time by adopting pulse laser with certain pulse width and certain power;

(5) and removing the metal thin film and the solid euphotic layer to obtain the sub-nanometer channel back electrode field effect transistor.

2. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (1), the isolation layer is a single-layer or few-layer hexagonal boron carbide two-dimensional material prepared by chemical vapor deposition, and the thickness of the isolation layer is 0.5-1 nm.

3. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (1), the isolation layer is transferred to the surface of the hundred-nanometer-scale back electrode by a dry transfer method or a wet transfer method.

4. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (2), the metal film is any one of aluminum foil, gold foil, silver foil and copper foil, the surface roughness of the metal film is lower than 0.5 micron, and the thickness of the metal film is 1 mu m-1 mm.

5. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (3), the solid euphotic layer is light-transmitting glass or quartz, and the thickness of the solid euphotic layer is 5mm-3 cm.

6. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (4), the pulse width of the pulse laser is 1-30ns, the frequency is 1-10Hz, and the laser power density is 0.4GW/cm²The irradiation time was 1 second.

7. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 6, wherein: the variation (R) of the channel pitch is related to the laser energy density (F), the feature size (L) and the structure thickness (H) by: when F is less than or equal to 14.5KJ/m²When R is 0.01144F³*L/H+0.15469*F²L/H + 0.77031F L/H + 0.10379L/H; when F is more than or equal to 14.5KJ/m²When R is 0.0015F³*L/H-0.1495*F²*L/H+4.5355*F*L/H+37.6238L/H。

8. The method for preparing the sub-nanometer channel back electrode field effect transistor by laser shock according to claim 1, wherein the method comprises the following steps: in the step (5), the size of the obtained back electrode field effect transistor channel is reduced to 1-10 nm.

Technical Field

The invention belongs to the field of field effect transistors, and particularly relates to a method for preparing a sub-nanometer channel back electrode field effect transistor by laser shock.

Background

The integrated circuit chip is used as the basis of modern electronic information technology and has the characteristics of strong function, low power consumption, high speed and low cost. Gorden, one of the founders of intel, once predicted the development of the semiconductor industry, doubling the number of micro devices that can be housed on an integrated circuit chip every 18 months, and doubling its performance. In the first decades, integrated circuits have followed moore's law substantially. The premise that moore's law can be put into effect is that devices can continue to be miniaturized, i.e., the channel length of the devices is continuously reduced. As device feature sizes continue to scale, carriers travel in the channel with little to no scattering, known as ballistic transport. Therefore, how to reduce the length of the transistor channel to make the integrated circuit chip support more and more functions, and at the same time, reducing the chip cost and improving the equivalent integration level of the circuit have become the research focus of researchers in the field of field effect transistors.

Disclosure of Invention

The invention aims to provide a method for preparing a sub-nanometer channel back electrode field effect transistor by laser impact, which has simple and convenient preparation process and is easy to adjust.

The scheme adopted by the invention for realizing the purpose is as follows: a method for preparing a sub-nanometer channel back electrode field effect transistor by laser shock comprises the following steps:

(1) laying a dielectric two-dimensional material as an isolation layer on a hundred-nanometer back electrode of a one-dimensional or two-dimensional material field effect transistor;

(2) covering a metal film with two flat surfaces on the surface of the isolation layer;

(3) covering a solid light-transmitting layer on the surface of the metal thin film;

(4) vertically irradiating the solid euphotic layer for a certain time by adopting pulse laser with certain pulse width and certain power;

(5) and removing the metal thin film and the solid euphotic layer to obtain the sub-nanometer channel back electrode field effect transistor.

Preferably, in the step (1), the isolation layer is a single-layer or few-layer hexagonal boron carbide two-dimensional material prepared by chemical vapor deposition, and the thickness of the isolation layer is 0.5-1 nm.

Preferably, in the step (1), the isolation layer is transferred to the surface of the hundreds nanometer level back electrode by a dry transfer method or a wet transfer method.

Preferably, in the step (2), the metal thin film is any one of aluminum foil, gold foil, silver foil and copper foil, the surface roughness of the metal thin film is less than 0.5 micron, and the thickness of the metal thin film is 1 μm to 1 mm.

Preferably, in the step (3), the solid light-transmitting layer is made of light-transmitting glass or quartz and has a thickness of 5mm-3 cm.

Preferably, in the step (4), the pulse width of the pulsed laser is 1-30ns, the frequency is 1-10Hz, the laser power density is 0.4GW/cm2, and the irradiation time is 1 second.

Preferably, the variation (R) of the channel pitch is related to the laser energy density (F), the characteristic dimension (L) of the metal electrode structure and the thickness (H) of the metal electrode structure by: when F is less than or equal to 14.5KJ/m²When R is 0.01144F³*L/H+0.15469*F²L/H + 0.77031F L/H + 0.10379L/H; when F is more than or equal to 14.5KJ/m²When R is 0.0015F³*L/H-0.1495*F²*L/H+4.5355*F*L/H+37.6238L/H。

Preferably, in the step (5), the size of the channel of the back electrode field effect transistor is reduced to 1-10 nm.

The invention has the following advantages and beneficial effects:

the method for preparing the sub-nanometer channel back electrode field effect transistor by laser impact utilizes laser to vertically irradiate the metal electrode of the transistor, and the metal electrode obtains energy to deform, thereby achieving the purpose of reducing the channel size. By controlling the intensity and the exposure time of the laser, the metal electrode in the transistor is induced to deform and flatten, and the horizontal area is increased, so that the length of the channel is reduced, and the accurate target size is obtained.

The method has simple operation requirement, can accurately reduce the length of a channel by controlling the laser intensity and the exposure time, improve the performance of the transistor, reduce the power consumption, break through the physical limit brought by the moore's law, realize the production of the field effect transistor with high electronic performance and integration density on a large scale, and provide a new way for promoting the development of the semiconductor industry.

Drawings

FIG. 1 is a schematic diagram of a laser shock fabrication of a sub-nanometer channel back-electrode field-effect transistor of the present invention;

FIG. 2 is an atomic force microscope representation of a metal structure, a two-dimensional material covered metal structure, and a laser shock reliably prepared two-dimensional material wrapped structure;

FIG. 3 is a diagram of results of atomic force microscopy on characterizing the aspect ratios of three structures, namely a randomly distributed metal structure, a two-dimensional material covered metal structure, and a two-dimensional material wrapped structure reliably prepared by laser shock;

FIG. 4 is a calculation result of the molecular dynamics of a two-dimensional material-wrapped metal structure under reliable laser shock preparation;

FIG. 5 is a sub-nanocrystallization of a two-dimensional material covered transistor channel with a laser shock reliably fabricated field effect transistor channel;

FIG. 6 is a scanning electron microscope photograph of a sub-nanometer channel back electrode field effect transistor prepared by laser shock.

In the figure, 1, a solid light-transmitting layer, 2, a metal thin film, 3, an isolation layer, 4, a metal electrode, 5, a low-dimensional semiconductor material, 6, a dielectric layer, 7, a substrate, 8 and a pulse laser.

Detailed Description

The following examples are provided to further illustrate the present invention for better understanding, but the present invention is not limited to the following examples.