阅读说明：本技术 一种亚纳米顶栅电极场效应晶体管的可控制备方法 (Controllable preparation method of sub-nanometer top gate field effect transistor ) 是由 胡耀武 黄正 何亚丽 于 2020-05-28 设计创作，主要内容包括：本发明属于场效应晶体管领域,具体涉及一种亚纳米顶栅电极场效应晶体管的可控制备方法,包括以下步骤：在金属纳米颗粒二聚体表面转移隔离层；在隔离层覆盖吸收层和透光层；利用脉冲激光垂直照射透光层；得到亚十纳米沟道的金属电极；将二维材料和高k栅介质材料转移到金属电极；将基片沉积的金属层和二维材料层转移到柔性衬底；将柔性衬底切成小块；将柔性衬底小块用柔性高分子材料包裹,切成薄片；将薄片转移到高k栅介质材料,留下的金属作为亚纳米顶栅电极。本发明的方法操作简单,能突破传统曝光技术的限制,打破制造亚十纳米沟道的技术壁垒,降低晶体管的生产成本,提高晶体管的性能,为推动超短沟道场效应晶体管的发展提供了一条新的道路。(The invention belongs to the field of field effect transistors, and particularly relates to a controllable preparation method of a sub-nanometer top gate field effect transistor, which comprises the following steps: transferring an isolation layer on the surface of the metal nanoparticle dimer; covering the absorption layer and the euphotic layer on the isolation layer; vertically irradiating the euphotic layer by using pulse laser; obtaining a metal electrode of a sub-ten nanometer channel; transferring the two-dimensional material and the high-k gate dielectric material to a metal electrode; transferring the metal layer deposited by the substrate and the two-dimensional material layer to a flexible substrate; dicing the flexible substrate; wrapping the small flexible substrate blocks with a flexible high polymer material, and cutting into slices; the sheet is transferred to a high-k gate dielectric material, leaving the metal as a sub-nanometer top gate electrode. The method of the invention has simple operation, can break through the limitation of the traditional exposure technology, break through the technical barrier of manufacturing the sub-ten nanometer channel, reduce the production cost of the transistor, improve the performance of the transistor and provide a new way for promoting the development of the ultra-short channel field effect transistor.)

1. A controllable preparation method of a sub-nanometer top gate field effect transistor is characterized by comprising the following steps:

(1) transferring a two-dimensional dielectric material on the surface of the metal nanoparticle dimer as an isolation layer;

(2) covering an absorption layer and a euphotic layer on the surface of the isolation layer in sequence;

(3) vertically irradiating the euphotic layer by using pulse laser;

(4) removing the residual two-dimensional dielectric material on the surface of the deformed metal nano particles to obtain a metal electrode of a sub-ten-nanometer channel;

(5) sequentially transferring a two-dimensional material and a high-k gate dielectric material to the surface of the metal electrode of the sub-ten nanometer channel;

(6) sequentially depositing a metal layer and a two-dimensional material layer on the surface of a substrate, and transferring the metal layer and the two-dimensional material layer to the surface of a flexible substrate;

(7) dicing the flexible substrate;

(8) wrapping the small flexible substrate blocks with a flexible high polymer material, and cutting the small flexible substrate blocks into thin sheets;

(9) transferring the thin sheet to the surface of the high-k gate dielectric material in the step (5), removing the two-dimensional material and the flexible high polymer material, and taking the remained metal as a sub-nanometer top gate electrode to prepare a sub-nanometer top gate electrode field effect transistor;

wherein the steps (1) - (5) are not in sequence with the steps (6) - (8).

2. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (1), the distance between the metal nanoparticle dimers is 50-100 nm; the metal nano-particle dimer is prepared by a template method through magnetron sputtering, pulsed laser deposition or chemical vapor deposition; the isolating layer is a boron carbide layer with the thickness of 0.5-3 nm.

3. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (2), the absorption layer is a metal film coated with graphite, the metal film is any one of aluminum foil, gold foil, silver foil and copper foil, the surface roughness of the metal film is lower than 0.5 micron, and the thickness of the metal film is 1-20 microns; the light-transmitting layer is made of light-transmitting glass or quartz and has a thickness of 1-5 cm.

4. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (3), the pulse laser wavelength is 1064nm, the pulse width is 1-10ns, the frequency is 1-10Hz, and the laser flux is 10-20kJ/cm²The irradiation time was 1 s.

5. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (4), the two-dimensional dielectric material is removed by adopting an etching method; the etching method is hydrogen plasma etching or oxygen plasma etching.

6. The controllable preparation method of sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (5), the two-dimensional material is MoS₂Or MoSe₂The thickness is 0.3-3 nm; the high-k gate dielectric material is HfO₂(ii) a The thickness is 10-20 nm.

7. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (6), the substrate is Si/SiO₂A substrate; the deposition method is atomic layer deposition, chemical vapor deposition, magnetron sputtering, electron beam deposition or pulsed laser deposition; the metal layer is Au, Ti or Ni, and the thickness is 2-5 nm; the two-dimensional material layer is MoS₂、MoSe₂、WSe₂Graphene or boron nitride with a thickness of 0.5-3 nm; the flexible substrate is polymethyl methacrylate.

8. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (7), the flexible substrate is cut into small blocks by a diamond cutter, and the width of each small block is 10-20 mm.

9. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (8), the flexible high polymer material is cut into slices in a nanometer cutting mode, and the thickness of each slice is 20-100 nm; the flexible high polymer material is epoxy resin.

10. The controllable preparation method of the sub-nanometer top gate field effect transistor according to claim 1, characterized in that: in the step (9), the method for removing the two-dimensional material and the flexible polymer material is an etching method.

Technical Field

The invention belongs to the field of field effect transistors, and particularly relates to a controllable preparation method of a sub-nanometer top gate field effect transistor.

Background

The integrated circuit chip is used as the basis of modern electronic information technology and has the characteristics of strong function, low power consumption, high speed and low cost. Mr. gorden proposed that the number of components that can be accommodated on an integrated circuit doubles approximately every 18-24 months, and performance doubles, a well-known moore's law. During the first decades, the development of integrated circuits has followed moore's law. An important prerequisite for the implementation of moore's law is that devices can be continuously miniaturized, i.e., the channel length of the devices is continuously reduced. However, the fabrication of ultra-short channel field effect transistors is very difficult due to the short channel effect. As the channel length decreases, field effect transistor devices are limited by the small size of the fabrication technology. In the prior art, when a transistor channel is prepared, high-precision exposure technologies such as electron beam exposure, ultraviolet exposure, deep ultraviolet exposure, extreme ultraviolet exposure and the like are mostly adopted, but the technologies are difficult to realize the exposure precision of sub-ten nanometers.

In order to break through the limitation of the traditional method for preparing the sub-ten-nanometer channel, researchers provide a new way for preparing the sub-ten-nanometer channel. Chinese patent CN 106653854a discloses an ultrashort channel transistor and a manufacturing method thereof, in which graphene with nanoscale grain boundaries is used as a source/drain electrode of a field effect transistor to prepare a sub-ten-nanometer ultrashort channel transistor. However, the method is difficult to accurately control the crystal boundary of the graphene, is not beneficial to industrial production, and the prepared ultra-short channel transistor has poor repeatability.

The metal nano-particles can be induced to deform under the action of the ultrashort pulse laser on the metal nano-particle dimers, and the distance between the metal nano-particles is expected to be reduced to be in a sub-ten nano-scale so as to be used as a metal electrode of the field effect transistor. The method breaks through the technical barrier of manufacturing the sub-ten nanometer channel and has great significance to the whole semiconductor industry.

Disclosure of Invention

The invention aims to provide a controllable preparation method of a sub-nanometer top gate field effect transistor, which is simple to operate, can break through the limitation of the traditional exposure technology, break through the technical barrier of manufacturing a sub-ten nanometer channel, reduce the production cost of the transistor and improve the performance of the transistor.

The scheme adopted by the invention for realizing the purpose is as follows: a controllable preparation method of a sub-nanometer top gate field effect transistor comprises the following steps:

(1) transferring a two-dimensional dielectric material on the surface of the metal nanoparticle dimer as an isolation layer;

(2) covering an absorption layer and a euphotic layer on the surface of the isolation layer in sequence;

(3) vertically irradiating the euphotic layer by using pulse laser;

(4) removing the residual two-dimensional dielectric material on the surface of the deformed metal nano particles to obtain a metal electrode of a sub-ten-nanometer channel;

(5) sequentially transferring a two-dimensional material and a high-k gate dielectric material to the surface of the metal electrode of the sub-ten nanometer channel;

(6) sequentially depositing a metal layer and a two-dimensional material layer on the surface of a substrate, and transferring the metal layer and the two-dimensional material layer to the surface of a flexible substrate;

(7) dicing the flexible substrate;

(8) wrapping the small flexible substrate blocks with a flexible high polymer material, and cutting the small flexible substrate blocks into thin sheets;

(9) transferring the thin sheet to the surface of the high-k gate dielectric material in the step (5), removing the two-dimensional material and the flexible high polymer material, and taking the remained metal as a sub-nanometer top gate electrode to prepare a sub-nanometer top gate electrode field effect transistor;

wherein the steps (1) - (5) are not in sequence with the steps (6) - (8).

Preferably, in the step (1), the distance between the metal nanoparticle dimers is 50-100 nm; the metal nano-particle dimer is prepared by a template method through magnetron sputtering, pulsed laser deposition or chemical vapor deposition; the isolating layer is a boron carbide layer with the thickness of 0.5-3 nm.

Preferably, in the step (2), the absorption layer is a metal thin film coated with graphite, the metal thin film is any one of aluminum foil, gold foil, silver foil and copper foil, the surface roughness of the metal thin film is lower than 0.5 micrometer, and the thickness of the metal thin film is 1-20 micrometers; the light-transmitting layer is made of light-transmitting glass or quartz and has a thickness of 1-5 cm.

Preferably, in the step (3), the pulse laser wavelength is 1064nm, the pulse width is 1-10ns, the frequency is 1-10Hz, and the laser flux is 10-20kJ/cm²The irradiation time was 1 s.

The invention can realize the accurate control of the dimension of the ultrashort channel by controlling the intensity and the irradiation time of the laser.

Preferably, in the step (4), the two-dimensional dielectric material is removed by an etching method; the etching method is hydrogen plasma etching or oxygen plasma etching.

Preferably, in the step (5), the two-dimensional material is MoS₂Or MoSe₂The thickness is 0.3-3 nm; the high-k gate dielectric material is HfO₂(ii) a The thickness is 10-20 nm.

Preferably, in the step (6), the substrate is Si/SiO₂A substrate; the deposition method is atomic layer deposition, chemical vapor deposition, magnetron sputtering, electron beam deposition or pulsed laser deposition; the metal layer is Au, Ti or Ni, and the thickness is 2-5 nm; the two-dimensional material layer is MoS₂、MoSe₂、WSe₂Graphene or boron nitride with a thickness of 0.5-3 nm; the flexible substrate is polymethyl methacrylate.

Preferably, in the step (7), the flexible substrate is cut into small blocks with the width of 10-20mm by using a diamond knife.

Preferably, in the step (8), the flexible polymer material is cut into slices in a nanometer cutting mode, and the thickness of each slice is 20-100 nm; the flexible high polymer material is epoxy resin.

Preferably, in the step (9), the method for removing the two-dimensional material and the flexible polymer material is an etching method.

Compared with the prior art, the method of the invention has the following obvious substantive characteristics and obvious advantages: the metal nano-particles can be induced to deform by the action of pulse laser on the metal nano-particle dimers, the distance between the nano-dimers is reduced to a sub-ten nano-scale to form an ultra-short channel, the two-dimensional dielectric material is transferred to the metal nano-particle dimers to be used as an isolation layer when the laser impacts, the adhesion phenomenon generated after the nano-particles deform can be effectively prevented, meanwhile, the surface roughness of the nano-particles can be improved, and the contact resistance between a metal electrode and the subsequently transferred two-dimensional material is reduced.

The method of the invention has simple operation, can break through the limitation of the traditional exposure technology, break through the technical barrier of manufacturing the sub-ten nanometer channel, reduce the production cost of the transistor, improve the performance of the transistor and provide a new way for promoting the development of the ultra-short channel field effect transistor.

Drawings

FIG. 1 is a schematic process diagram of step (1) according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the process of step (2) according to the embodiment of the present invention;

FIG. 3 is a schematic diagram of the process of step (3) according to the embodiment of the present invention;

FIG. 4 is a schematic view of another process of step (3) according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of the process of step (4) according to the embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating the process of step (5) according to the embodiment of the present invention;

FIG. 7 is a schematic view of another process of step (5) according to the embodiment of the present invention; (ii) a

FIG. 8 is a schematic diagram of the process of step (9) according to the embodiment of the present invention.

In the figure: 1. a substrate; 2. SiO 2₂A layer; 3. a metal nanoparticle dimer; 4. an isolation layer; 5. an absorbing layer; 6. a light transmitting layer; 7. MoS₂A layer; 8. HfO₂A layer; 9. and an Au layer.

Detailed Description

The following examples are provided to further illustrate the present invention for better understanding, but the present invention is not limited to the following examples.

The transfer, etching and deposition modes involved in the invention are all the prior art, and the etching method comprises but is not limited to oxygen plasma etching and hydrogen plasma etching. Transfer includes, but is not limited to, dry transfer or wet transfer. Deposition methods include, but are not limited to, atomic layer deposition, chemical vapor deposition, magnetron sputtering, electron beam deposition, pulsed laser deposition.

Fig. 1 to 8 are schematic flow charts of the method of the present invention, the operation of the present invention includes the following steps:

(1) coating 300nm SiO on the high-conductivity silicon wafer substrate 1₂ Layer 2, obtaining a hundred-nanometer pattern by a low-cost low-resolution photoetching technology and evaporating Au/Ti to obtain a metal nanoparticle dimer 3, as shown in figure 1;

(2) transferring a single-layer hexagonal boron carbide two-dimensional material as an isolation layer 4 by a wet transfer method with polymethyl methacrylate (PMMA) as a carrier, as shown in FIG. 2;

(3) washing with acetone solution to remove polymethyl methacrylate (PMMA), and drying the sample; after the sample is dried, covering an aluminum foil coated with graphite and having a thickness of 10 mu m on the surface of the isolation layer 4 to serve as an absorption layer 5, and covering light-transmitting glass on the aluminum foil to serve as a light-transmitting layer 6; using pulse laser emitted by Nd-YAG laser with pulse width of 10ns and wavelength of 1064nm to vertically irradiate the light-transmitting layer 6, and controlling laser flux to be 15kJ/cm²The irradiation time is 1s, as shown in FIG. 3; after the impact, the metal nanoparticle dimer 3 deforms, so that the distance between the metal nanoparticle dimer 3 becomes smaller; the presence of the isolating layer 4 prevents the metal electrodes from sticking during the impact, as shown in fig. 4;

(4) and etching the residual isolating layer 4 on the surface of the deformed metal nanoparticle dimer 3 by using hydrogen plasma for 60min to obtain the metal electrode of the sub-ten-nanometer channel after etching treatment, as shown in fig. 5.

(5) Single layer MoS to be prepared using chemical vapor deposition₂Layer 7 and high-k gate dielectric material HfO₂Layer 8 is transferred to the metal electrode of the sub-ten nanometer channel as shown in fig. 6 and 7.

(6) In Si/SiO₂Depositing an Au layer 9 with the thickness of 10nm and a single-layer graphene on a substrate, transferring the Au layer and the single-layer graphene onto polymethyl methacrylate (PMMA), and cutting the PMMA into small blocks with the width of 20mm by using a diamond cutter;

(7) placing the PMMA small block into a vacuum mold, wrapping the PMMA small block with epoxy resin, and exhausting air between Au and graphene and the epoxy resin to enable the Au and the graphene to be in close contact;

(8) cutting the epoxy resin wrapped with Au and graphene along the short edge by using a nano cutter, wherein the thickness is controlled to be 20-50 nm;

(9) transferring the cut slice to HfO₂On layer 8, note that the Au layer 9 is to be aligned with the channel between the metal electrode pair, as in fig. 8;

(10) and etching the graphene and the epoxy resin on the sheet for 2h by using oxygen plasma, wherein the pressure of a plasma cavity is 200mTorr, the power is 30W, and the remained Au layer 9 is used as a top gate electrode to prepare the sub-nanometer top gate electrode field effect transistor.

While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.