阅读说明：本技术 光检测装置
(Optical detection device
) 是由 藤田卓也
田村有正
牧野健二
马场隆
山本晃永 于 2019-01-24 设计创作，主要内容包括：光检测装置具备由化合物半导体构成的雪崩光电二极管阵列基板(10)。在雪崩光电二极管阵列基板(10),二维排列有以盖革模式动作的多个雪崩光电二极管(20)。电路基板(50)具有互相并联连接并形成至少1个信道(40)的多个输出单元(30)。各输出单元(30)具有被动淬灭元件(31)及电容元件(32)。被动淬灭元件(31)与多个雪崩光电二极管(20)的至少一个串联连接。电容元件(32)与至少1个雪崩光电二极管(20)串联连接且与被动淬灭元件(31)并联连接。(The photodetector includes an avalanche photodiode array substrate (10) made of a compound semiconductor. A plurality of avalanche photodiodes (20) operating in a Geiger mode are arranged two-dimensionally on an avalanche photodiode array substrate (10). The circuit board (50) has a plurality of output units (30) connected in parallel with each other and forming at least 1 channel (40). Each output unit (30) has a passive quenching element (31) and a capacitance element (32). A passive quenching element (31) is connected in series with at least one of the plurality of avalanche photodiodes (20). The capacitive element (32) is connected in series with at least 1 avalanche photodiode (20) and in parallel with the passive quenching element (31).)
1. A light detection device, wherein,
comprises the following steps:
an avalanche photodiode array substrate in which a plurality of avalanche photodiodes operating in a geiger mode are two-dimensionally arranged and which is composed of a compound semiconductor; and
a circuit substrate on which the avalanche photodiode array substrate is mounted,
the circuit substrate includes a plurality of output units connected in parallel with each other and forming at least 1 channel,
each of the output cells includes a passive quenching element connected in series with at least one of the plurality of avalanche photodiodes, and a capacitive element connected in series with the at least 1 avalanche photodiode and connected in parallel with the passive quenching element.
2. The light detection arrangement of claim 1,
the passive quenching element is formed by a 1 st polysilicon layer arranged on the circuit substrate,
the capacitor element is formed of a 2 nd polysilicon layer provided on the circuit substrate, a dielectric layer laminated on the 2 nd polysilicon layer, and a 3 rd polysilicon layer laminated on the dielectric layer,
the 1 st polysilicon layer is formed to the same height as the 2 nd or 3 rd polysilicon layer in a thickness direction of the circuit substrate.
Technical Field
The present invention relates to a photodetection device.
Background
A photodetector in which a plurality of avalanche photodiodes are two-dimensionally arranged is known (for example, patent document 1). The plurality of avalanche photodiodes operate in a geiger mode. The plurality of avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor.
Disclosure of Invention
Problems to be solved by the invention
When a plurality of avalanche photodiodes formed on a semiconductor substrate made of a compound semiconductor operate in a geiger mode, a dark pulse and a remaining pulse increase in accordance with a temperature change. If the noise increases due to the dark pulse and the residual pulse, the signal from the avalanche photodiode may not be appropriately detected.
In the case where the avalanche photodiode operates in the geiger mode, it is known to arrange a passive quenching element in series with the avalanche photodiode in order to quench the avalanche multiplication. Determining whether an avalanche multiplication process generated inside an avalanche photodiode connected to the passive quenching element is properly quenched, corresponding to a resistance value of the passive quenching element. If the resistance value of the quenching element is insufficient, the quenching may not be properly performed due to the occurrence of a lock-up current or the like. For appropriate quenching, it is necessary to select a resistance value of the quenching element necessary enough.
The larger the resistance value of the passive quenching element is, the more time is required for quenching of the avalanche photodiode connected in series with the passive quenching element. If the time required for quenching increases, the dead time in which light cannot be detected by the avalanche photodiode increases. In order to ensure both appropriate quenching and reduction of dead time and to ensure photodetection sensitivity and photodetection time resolution, a circuit design of a passive quenching element having an optimum resistance value is required.
Since the parasitic capacitance in the passive quenching element also affects the pulse signal, the parasitic capacitance is also removed. In order to further improve the light detection time resolution, the peak value of the pulse signal is also improved. It is extremely difficult to design a device in which a plurality of avalanche photodiodes formed on a semiconductor substrate made of a compound semiconductor are operated in a geiger mode so as to satisfy all of the above-described desired conditions.
An object of one embodiment of the present invention is to provide a photodetection device having a structure in which a plurality of avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor, and having both improved photodetection sensitivity and photodetection time resolution.
Means for solving the problems
A photodetection device according to one embodiment of the present invention includes an avalanche photodiode array substrate and a circuit substrate. The avalanche photodiode array substrate is composed of a compound semiconductor. An avalanche photodiode array substrate is mounted on the circuit substrate. In the avalanche photodiode array substrate, a plurality of avalanche photodiodes are two-dimensionally arranged. The plurality of avalanche photodiodes operate in a geiger mode. The circuit board has a plurality of output units connected in parallel with each other. The plurality of output units form at least 1 channel. Each output unit has a passive quenching element and a capacitance element. The passive quenching element is connected in series with at least one of the plurality of avalanche photodiodes. The capacitive element is connected in series with at least 1 avalanche photodiode and in parallel with the passive quenching element.
In this embodiment, the plurality of output units each including the passive quenching element and the capacitor element are provided on a circuit board separate from the avalanche photodiode array substrate. Therefore, compared to the case where a plurality of output cells are arranged on the avalanche photodiode array substrate, the space in which the plurality of output cells can be formed can be enlarged. If the output unit is provided on a circuit substrate separate from the avalanche photodiode array substrate, the parasitic capacitance generated between the structure of the avalanche photodiode and the output unit can be reduced. In this case, a manufacturing process different from that of the avalanche photodiode array substrate may be used. Therefore, the design of the plurality of output units becomes easy. The photodetector has a capacitance element connected in series with at least 1 avalanche photodiode and connected in parallel with a passive quenching element. Therefore, the peak value of the pulse signal from the avalanche photodiode connected in series to the capacitance element can be increased by the capacitance of the capacitance element. Therefore, the pulse signals from the plurality of avalanche photodiodes can be easily detected, and the photodetection time resolution can be further improved.
In this embodiment, the passive quenching element may be formed of the 1 st polysilicon layer provided on the circuit board. The capacitor element may be formed of a 2 nd polysilicon layer provided on the circuit substrate, a dielectric layer stacked on the 2 nd polysilicon layer, and a 3 rd polysilicon layer stacked on the dielectric layer. The 1 st polysilicon layer is formed to the same height as the 2 nd or 3 rd polysilicon layer in the thickness direction of the circuit substrate. In this case, the plurality of output units can be formed in a simple manufacturing process.
ADVANTAGEOUS EFFECTS OF INVENTION
According to one embodiment of the present invention, there is provided a photodetection device which can be easily designed and can ensure photodetection accuracy in a structure in which a plurality of avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor.
Drawings
Fig. 1 is a perspective view of a light detection device according to an embodiment.
Fig. 2 is a diagram showing a cross-sectional structure of the light detection device.
Fig. 3 is a plan view of the circuit substrate.
Fig. 4 is a plan view of a light detection region of the avalanche photodiode array substrate.
Fig. 5 is a diagram showing the structure of the circuit substrate.
Fig. 6 is a diagram showing a circuit configuration used for the photodetection device.
Fig. 7 is a diagram showing a circuit configuration used in a photodetection device according to a modification of the present embodiment.
Fig. 8 is a plan view of the mounting region of the circuit substrate.
Fig. 9 is a diagram showing the components of the pulse signal from the avalanche photodiode.
Fig. 10 is a graph showing the characteristics of the recharge pulse.
Fig. 11 is a graph showing the characteristics of a fast pulse.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the description, the same elements or elements having the same function are denoted by the same reference numerals, and redundant description thereof is omitted.
First, the overall configuration of the photodetection device according to the present embodiment will be described with reference to fig. 1 to 8. Fig. 1 is a perspective view of a light detection device according to the present embodiment. Fig. 2 is a diagram showing a cross-sectional structure of the photodetection device according to the present embodiment. In fig. 2, hatching is omitted to improve visibility. Fig. 3 is a plan view of the circuit substrate. Fig. 4 is a top view showing a portion of the avalanche photodiode array substrate. Fig. 6 is a diagram showing a circuit configuration used in the photodetection device according to the present embodiment. Fig. 8 is a plan view showing a part of the circuit substrate.
As shown in fig. 1, the photodetector 1 includes an avalanche photodiode array substrate 10 and a circuit board 50. Hereinafter, the "avalanche photodiode" is referred to as "APD". The "avalanche photodiode array substrate" is referred to as an "APD array substrate". The circuit substrate 50 is disposed opposite to the APD array substrate 10. The APD array substrate 10 and the circuit substrate 50 are rectangular in plan view.
The APD array substrate 10 includes a main surface 10A, a main surface 10B, and a side surface 10C that face each other. The circuit board 50 includes a main surface 50A, a main surface 50B, and a side surface 50C that face each other. The main surface 10B of the APD array substrate 10 faces the main surface 50A of the circuit substrate 50. The surfaces parallel to the principal surfaces of the APD array substrate 10 and the circuit substrate 50 are XY-axis planes, and the direction orthogonal to the principal surfaces is a Z-axis direction.
The side surface 50C of the circuit substrate 50 is located outside the side surface 10C of the APD array substrate 10 in the XY-axis plane direction. That is, the area of the circuit substrate 50 is larger than the area of the APD array substrate 10 in a plan view. The side surface 10C of the APD array substrate 10 and the side surface 50C of the circuit substrate 50 may be the same plane. In this case, the outer edge of the APD array substrate 10 coincides with the outer edge of the circuit substrate 50 in a plan view.
A glass substrate may be disposed on the main surface 10A of the APD array substrate 10. The glass substrate is optically connected to the APD array substrate 10 by an optical adhesive. The glass substrate may also be formed directly on the APD array substrate 10. The side surface 10C of the APD array substrate 10 and the side surface of the glass substrate may be the same surface. In this case, the outer edge of the APD array substrate 10 coincides with the outer edge of the glass substrate in a plan view. The side surface 10C of the APD array substrate 10, the side surface 50C of the circuit substrate 50, and the side surface of the glass substrate may be the same surface. In this case, the outer edge of the APD array substrate 10, the outer edge of the circuit substrate 50, and the outer edge of the glass substrate coincide with each other in a plan view.
The APD array substrate 10 is mounted to the circuit substrate 50. As shown in fig. 2, the APD array substrate 10 and the circuit substrate 50 are connected by the bump electrodes 25. Specifically, as shown in fig. 3, the APD array substrate 10 is connected to the mounting region α disposed at the center of the circuit substrate 50 by the bump electrode 25 when viewed in the thickness direction of the APD array substrate 10. In the present embodiment, the mounting region α has a rectangular shape.
The circuit board 50 has a ground line 3, a cathode line 5, and an anode line 7 around the mounting region α. The ground line 3, the cathode line 5, and the anode line 7 extend from the mounting region α. The ground line 3 is connected to a ground electrode 63 described below. The cathode line 5 is electrically connected to the APD array substrate 10 mounted in the mounting region α for voltage application to the APD array substrate 10. The anode line 7 is connected to metal layers 65, 66 described below for signal readout from the APD array substrate 10.
The APD array substrate 10 has a plurality of APDs 20 operating in geiger mode. As shown in fig. 4, the APDs 20 are two-dimensionally arranged in the light detection region β of the semiconductor substrate 11 when viewed from the thickness direction of the APD array substrate 10. The light detection region β has a rectangular shape, and overlaps the mounting region α of the circuit substrate 50 when viewed in the thickness direction of the APD array substrate 10.
The APD array substrate 10 includes an N-type semiconductor substrate 11 made of a compound semiconductor. The semiconductor substrate 11 has a substrate 12 made of InP forming a main surface 10A. On the substrate 12, a buffer layer 13 made of InP, an absorption layer 14 made of InGaAsP, an electric field relaxation layer 15 made of InGaAsP, and a multiplication layer 16 made of InP are formed in this order from the principal surface 10A side to the principal surface 10B side. The absorption layer 14 may also be formed of InGaAs. The semiconductor substrate 11 may be formed of GaAs, InGaAs, AlGaAs, inalgas, CdTe, HgCdTe, or the like.
As shown in fig. 2 and 4, each APD20 is surrounded by the insulating portion 21 when viewed in the thickness direction of the APD array substrate 10. Each APD20 has a P-type active region 22 formed by doping the multiplication layer 16 with impurities from the main surface 10B side. The doped impurity is, for example, Zn (zinc). The insulating portion 21 is formed by forming a polyimide (polyimide) film in a trench formed by, for example, wet etching or dry etching. The active region 22 is formed in a circular shape when viewed in the thickness direction, and the insulating portion 21 is formed in an annular shape along the edge of the active region 22. The insulating portion 21 reaches the substrate 12 from the main surface 10B side of the semiconductor substrate 11 in the thickness direction of the APD array substrate 10.
Fig. 5 is a view showing a part of an avalanche photodiode array substrate used in a photodetection device according to a modification of the present embodiment. As shown in fig. 5, the active region 22 may be formed in a substantially rectangular shape when viewed in the thickness direction. Here, the substantially rectangular shape is a rectangular shape with rounded corners. Thereby, concentration of the electric field to the corners of the active region 22 is suppressed. In this case, the insulating portion 21 is formed in a ring shape along the edge of the substantially rectangular active region 22.
The APD array substrate 10 has an insulating layer 23 and a plurality of electrode pads 24. The insulating layer 23 covers the semiconductor substrate 11 on the main surface 10B side. The electrode pad 24 is formed on the semiconductor substrate 11 on the main surface 10B side of each APD20, and is in contact with the active region 22. The electrode pad 24 is exposed from the insulating layer 23, passes through the bump electrode 25, and is connected to the circuit substrate 50.
As shown in fig. 2, the circuit substrate 50 is connected to the APD array substrate 10 on the main surface 50A side via the bump electrode 25. The circuit board 50 has a plurality of output units 30. As shown in fig. 6, the plurality of output units 30 are connected in parallel with each other to form 1 channel 40. Each of the plurality of output cells 30 is connected in series to each APD20 provided in the APD array substrate 10. Each output unit 30 has a passive quenching element 31 and a capacitance element 32 connected in parallel with each other. The passive quenching element 31 and the capacitive element 32 are both connected in series with the APD 20.
Fig. 7 is a diagram for explaining a circuit configuration used in the photodetection device according to the modified example of the present embodiment. As shown in fig. 7, a plurality of channels 40 may be formed on the circuit board 50. In this case, each channel 40 is formed by a plurality of output units 30 connected in parallel with each other. As long as at least one of the plurality of channels 40 is formed by a plurality of output units 30 connected in parallel with each other.
The circuit board 50 includes a silicon substrate 51 and a wiring layer 61 laminated on the silicon substrate 51. As shown in FIG. 2, the silicon substrate 51 has P in the order from the main surface 50B side to the main surface 50A side+Layer 52, P－Layer 53, P+And a layer 54. P+Layer 52 is formed by coating at P－The layer 53 is provided by doping with impurities. P+Layer 54 is formed by coating at P－The layer 53 is provided by doping with impurities. Doped in P－The impurity of the layer 53 is, for example, boron. An oxide film layer 60 formed by, for example, an element isolation process using thermal oxidation is provided between the silicon substrate 51 and the wiring layer 61. P+The layer 54 is exposed from the oxide film layer 60 and is in contact with the wiring layer 61.
The wiring layer 61 has an insulating layer 62, a ground electrode 63, an electrode pad 64, metal layers 65, 66, via holes 67, 68, 69, 70, polysilicon layers 71, 72, 73, and a dielectric layer 74. A ground electrode 63, an electrode pad 64, metal layers 65, 66, vias 67, 68, 69, 70, polysilicon layers 71, 72, 73, and a dielectric layer 74 are disposed at each APD 20. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are formed in the same layer. In other words, the ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are formed to have the same height in the thickness direction of the circuit board 50.
The insulating layer 62 is made of, for example, SiO2And (4) forming. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are made of Al, AlCu, AlSiCu, or the like, for example. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 may be formed of the same material. The through holes 67, 68, 69, 70 are formed of, for example, W (tungsten). Dielectric layer 74 is made of, for example, SiO2Or Si3N4And (4) forming.
The wiring layer 61 is covered with an insulating layer 62. P of silicon substrate 51+The layer 54 is connected to a through hole 67 exposed from the insulating layer 62 of the wiring layer 61 toward the silicon substrate 51. P+Layer 54 passes through via 67 and is connected to ground electrode 63. The ground electrode 63 is disposed at a height at which the ground electrode 63 is disposed in the thickness direction of the circuit board 50, and is disposed opposite to the electrode pad 64 and the metal layers 65 and 66 via the insulating layer 62. The ground electrode 63 is not directly connected to the electrode pad 64 and the metal layers 65 and 66.
The electrode pad 64 is exposed from the insulating layer 62, passes through the bump electrode 25, and is connected to the APD 20. The electrode pads 64 are two-dimensionally arranged on the main surface 50A side as shown in fig. 8. Electrode pad 64 passes through via 68 and is connected to polysilicon layer 71. Polysilicon layer 71 passes through via 69 and is connected to metal layer 65. The electrode pad 64 is disposed at a height at which the electrode pad 64 is disposed in the thickness direction of the circuit board 50, and is disposed opposite to the metal layers 65 and 66 via the insulating layer 62. The electrode pads 64 are not directly connected to the metal layers 65, 66. The polysilicon layer 71 is included in the 1 st polysilicon layer.
The polysilicon layer 71 constitutes the passive quenching element 31. With the above structure, the passive quenching element 31 is connected in series to the APD20 through the bump electrode 25, the electrode pad 64 and the via 68. That is, the pulse signal from the APD20 passes through the bump electrode 25, the electrode pad 64, and the through hole 68 and is input to the passive quenching element 31. The pulse signal input to the passive quenching element 31 passes through the passive quenching element 31, the channel 69, and the metal layer 65 and is output from the channel 40.
The electrode pads 64 are connected to the metal layer 66 at a height at which the electrode pads 64 are arranged in the thickness direction of the circuit board 50. Metal layer 66 passes through via 70 and connects to polysilicon layer 72. Polysilicon layer 72 is stacked on dielectric layer 74. A dielectric layer 74 is laminated over polysilicon layer 73. Polysilicon layer 73 is connected to metal layer 65 through a via hole not shown. The polysilicon layers 71 and 73 are formed to have the same height in the thickness direction of the circuit substrate 50. The polysilicon layers 71 and 72 may be formed to have the same height in the thickness direction of the circuit substrate 50. Polysilicon layer 72 is included in polysilicon layer 3. Polysilicon layer 73 is included in polysilicon layer 2.
Polysilicon layer 72, dielectric layer 74, and polysilicon layer 73 constitute capacitive element 32. With the above-described structure, the capacitor element 32 is connected in series to the APD20 through the bump electrode 25, the electrode pad 64, and the via hole 68. That is, the pulse signal from the APD20 passes through the bump electrode 25, the electrode pad 64, and the via hole 68 and is input to the polysilicon layer 72 of the capacitive element 32. The pulse signal is input to the polysilicon layer 72 of the capacitor 32, and the pulse signal is output from the polysilicon layer 73 of the capacitor 32. The pulse signal output from the capacitor 32 passes through a via hole and the metal layer 65, not shown, and is output from the channel 40.
The passive quenching element 31 and the capacitance element 32 are electrically connected to the electrode pad 64 and the metal layer 65. Therefore, the passive quenching element 31 and the capacitance element 32 are connected in parallel with each other.
Next, the operation and effects of the photodetector 1 will be described with reference to fig. 9 to 11. Fig. 9 is a diagram showing a pulse signal output from APD 20. As shown in fig. 9, the pulse signal 26 from APD20 is divided into a fast pulse 27 and a recharge pulse 28. The fast pulse 27 is a pulse component having a peak of the pulse signal. The recharge pulse 28 is a component that is detected after the fast pulse 27 is detected and has a longer pulse width than the fast pulse 27.
Fig. 10 shows a waveform of a pulse signal output from the APD20 with the capacitance element 32 removed from the output unit 30 and the resistance value of the passive quenching element 31 set as a parameter. Fig. 10 is an integer diagram in which the unit of the vertical axis is current (a) and the unit of the horizontal axis is time(s). The data a, b, c, and d are pulse signals obtained when the passive quenching elements 31 having different resistance values are provided in the output unit 30. The passive quenching element 31 having a higher resistance value is provided in the order of data a, b, c, d.
As shown in fig. 10, the smaller the resistance value of passive quenching element 31, the steeper the slope of recharge pulse 28. The steeper the slope of the recharge pulse 28, the shorter the time required for quenching and the shorter the dead time for failure to detect light with APD 20. By using the passive quenching element 31 having a large resistance value, it is possible to achieve appropriate quenching that suppresses the occurrence of a latch-up current or the like. However, the larger the resistance value, the more the dead time increases.
The pulse width of the pulse signal from the APD20 connected to the passive quenching element 31 also changes depending on the resistance value of the passive quenching element 31. As shown in fig. 10, the dead time of the APD20 connected in series to the passive quenching element 31 increases as the resistance value of the passive quenching element 31 increases. Therefore, in order to achieve both appropriate quenching and reduction in dead time, and to ensure photodetection sensitivity and photodetection time resolution, the circuit design of the passive quenching element 31 having an optimum resistance value is required.
In the photodetector 1, the plurality of output cells 30 each having the passive quenching element 31 and the capacitance element 32 are provided on a circuit substrate 50 separate from the APD array substrate 10. Therefore, the space in which the plurality of output cells 30 can be formed can be made larger than in the case where the plurality of output cells 30 are disposed on the APD array substrate 10. Therefore, the design of the plurality of output units 30 becomes easy.
Since the plurality of output cells 30 are provided on the circuit substrate 50 that is separate from the APD array substrate 10, parasitic capacitance generated between the structure of the APD20 and the output cells 30 can be reduced. A different fabrication process than the APD array substrate 10 may also be used. Since a manufacturing process suitable for each of the APD array substrate 10 and the circuit substrate 50 can be used, the design of the plurality of output cells 30 can be facilitated.
Fig. 11 shows waveforms of pulse signals output from the APD20 with the passive quenching element 31 set to a constant value and the capacitance of the capacitive element 32 as a parameter. Fig. 11 is a univariate graph in which the unit of the vertical axis is current (a) and the unit of the horizontal axis is time(s). The data a is data of a pulse signal in the case where the capacitive element 32 is removed from the output unit 30. The data b, c, d are pulse signal data in the case where the capacitive elements 32 having different capacitances are provided in the output unit 30. The capacitor element 32 having a higher electrostatic capacitance is provided in the order of data b, c, and d.
As shown in fig. 11, by providing the capacitive element 32, the peak value of the fast pulse 27 is increased. The higher the electrostatic capacitance of the capacitive element 32, the larger the peak value of the fast pulse 27. Therefore, by providing the capacitive element 32, the time resolution of the pulse signal from the plurality of APDs 20 is improved. The larger the peak value of the fast pulse 27, the easier it is to detect pulse signals from multiple APDs 20.
The photodetector 1 includes a capacitive element 32 connected in series with at least 1 APD20 and connected in parallel with the passive quenching element 31. According to the above configuration, the peak value of the pulse signal from the APD20 connected in series to the capacitive element 32 can be increased by the capacitance of the capacitive element 32 according to the characteristics described with reference to fig. 11. Therefore, pulse signals from a plurality of APDs 20 can be easily detected, and the optical detection time resolution can be improved. The photodetection device 1 can count the number of incident photons while achieving desired photodetection sensitivity and photodetection time resolution.
In the APD array substrate 10 made of a compound semiconductor, in the structure in which the plurality of APDs 20 operate in the geiger mode, the influence of noise can be suppressed by reducing the electric field intensity applied to each APD 20.
The photodetector 1 includes polysilicon layers 71 and 73 provided on the circuit substrate 50, a dielectric layer 74 provided on the polysilicon layer 73, and a polysilicon layer 72 provided on the dielectric layer 74. The passive quenching element 31 is formed by a polysilicon layer 71, and the capacitive element 32 is formed by a polysilicon layer 73, a dielectric layer 74, and a polysilicon layer 72. The polysilicon layer 71 is formed to the same height as the polysilicon layer 72 or 73 in the thickness direction of the circuit substrate 50. In this case, the plurality of output units 30 can be formed in a simple manufacturing process.
While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.
For example, the passive quenching element 31 may be formed by a metal thin film instead of the polysilicon layer 71. The capacitance element 32 may be formed of 2 metal layers instead of the polysilicon layers 72, 73. In this case, the capacitor element 32 has a structure in which 2 parallel metal layers sandwich the dielectric layer 74.
Description of the symbols
1 … light detection device, 10 … APD array substrate, 20 … APD, 30 … output unit, 31 … passive quenching element, 32 … capacitance element, 40 … channel, 50 … circuit substrate, 71, 72, 73 … polysilicon layer, 74 … dielectric layer.
