阅读说明：本技术 一种GaN HEMT器件的制备方法 (Preparation method of GaN HEMT device ) 是由 蒋洋 于洪宇 汪青 范梦雅 何佳琦 于 2020-05-11 设计创作，主要内容包括：本发明实施例公开了一种GaN HEMT器件的制备方法,包括提供外延基底,外延基底包括衬底以及在衬底上依次层叠设置的沟道层以及势垒层；采用氧化刻蚀工艺图形化势垒层,形成源极欧姆接触凹槽和漏极欧姆接触凹槽；在源极欧姆接触凹槽内形成源极欧姆接触电极,同时在漏极欧姆接触凹槽内形成漏极欧姆接触电极；在势垒层、源极欧姆接触电极以及漏极欧姆接触电极背离衬底一侧形成图形化的钝化层,在钝化层背离外延基底的一侧形成源极、漏极、栅极开孔并沉积金属电极,金属电极包括源极金属电极、漏极金属电极和栅极金属电极。该方法能够精确控制刻蚀深度,改善欧姆接触区域的刻蚀形貌,提升欧姆接触质量,提升输出饱和电流,提升器件性能。(The embodiment of the invention discloses a preparation method of a GaN HEMT device, which comprises the steps of providing an epitaxial substrate, wherein the epitaxial substrate comprises a substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate; patterning the barrier layer by adopting an oxidation etching process to form a source electrode ohmic contact groove and a drain electrode ohmic contact groove; forming a source ohmic contact electrode in the source ohmic contact groove and simultaneously forming a drain ohmic contact electrode in the drain ohmic contact groove; and forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side departing from the substrate, forming openings on the source electrode, the drain electrode and the grid electrode on the side of the passivation layer departing from the epitaxial substrate, and depositing metal electrodes, wherein the metal electrodes comprise a source metal electrode, a drain metal electrode and a grid metal electrode. The method can accurately control the etching depth, improve the etching appearance of the ohmic contact area, improve the ohmic contact quality, improve the output saturation current and improve the device performance.)

1. A preparation method of a GaN HEMT device is characterized by comprising the following steps:

providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate;

patterning the barrier layer by adopting an oxidation etching process to form a source electrode ohmic contact groove and a drain electrode ohmic contact groove; the source ohmic contact groove exposes a source electrode in the channel layer, and the drain ohmic contact groove exposes a drain electrode in the channel layer;

forming a source ohmic contact electrode in the source ohmic contact groove, and forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is in contact with the source electrode, and the drain ohmic contact electrode is in contact with the drain electrode;

forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side away from the substrate; the passivation layer comprises a source opening, a drain opening and a gate opening, wherein a vertical projection of the source opening on the source ohmic contact electrode is positioned in the source ohmic contact electrode, a vertical projection of the drain opening on the drain ohmic contact electrode is positioned in the drain ohmic contact electrode, and a vertical projection of the gate opening on the barrier layer is positioned between the source ohmic contact electrode and the drain ohmic contact electrode;

forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrodes include a source metal electrode, a drain metal electrode, and a gate metal electrode, the source metal electrode is connected to the source ohmic contact electrode through the source opening, the drain metal electrode is connected to the drain ohmic contact electrode through the drain opening, and the gate metal electrode is connected to the barrier layer through the gate opening.

2. The method of claim 1, wherein patterning the barrier layer using an oxide etch process to form a source ohmic contact recess and a drain ohmic contact recess comprises:

forming a patterned first photoresist layer on the side, away from the substrate, of the barrier layer; the first photoresist layer does not cover the regions of the barrier layer corresponding to the source electrode and the drain electrode;

oxidizing the barrier layer by taking the first photoresist layer as a mask to form an oxidation structure;

and removing the oxidation structure to form the source ohmic contact groove and the drain ohmic contact groove.

3. The method of claim 2, wherein the oxidizing the barrier layer comprises: oxidizing the barrier layer with an oxygen plasma;

the removing the oxidation structure comprises: and removing the oxidation structure by using dilute hydrochloric acid.

4. The method of claim 3, wherein the parameters of the oxidation process for oxidizing the barrier layer with an oxygen plasma comprise: the power of the upper electrode is 100W-450W, the power of the lower electrode is 20W-80W, the flow rate of oxygen is 20 sccm-80 sccm, the pressure of the chamber is 5 mToor-20 mToor, and the oxidation time is 1 min-5 min;

the volume ratio of hydrochloric acid to water in the dilute hydrochloric acid is 1: 3-1: 5.

5. The method of manufacturing according to claim 2, wherein forming a source ohmic contact electrode in the source ohmic contact groove and simultaneously forming a drain ohmic contact electrode in the drain ohmic contact groove comprises:

forming a contact electrode layer on one side of the first photoresist layer, the source ohmic contact groove and the drain ohmic contact groove, which is far away from the substrate;

and removing the first photoresist layer and the contact electrode layer on the first photoresist layer, and performing annealing treatment to form the source ohmic contact electrode and the drain ohmic contact electrode.

6. The production method according to claim 5, wherein the contact electrode layer comprises Ti₅Al₁An alloy layer and a TiN metal cap layer, the Ti₅Al₁The alloy layer and the TiN metal cap layer are stacked along the direction departing from the substrate.

7. The method according to claim 1, wherein forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on a side facing away from the substrate comprises:

forming an initial passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side away from the substrate;

forming a patterned second photoresist layer on the side of the initial passivation layer away from the substrate, wherein the second photoresist layer does not cover partial areas of the initial passivation layer corresponding to the source ohmic contact electrode, the drain ohmic contact electrode and the barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode;

and etching the initial passivation layer by taking the second photoresist layer as a mask to form the patterned passivation layer.

8. The method of claim 1, wherein forming a metal electrode on a side of the passivation layer facing away from the epitaxial substrate comprises:

forming a patterned third photoresist layer on the passivation layer, wherein a vertical projection of the third photoresist layer on the substrate is positioned in a vertical projection of the passivation layer on the substrate;

forming a metal electrode layer on the third photoresist layer, the source opening, the drain opening and the grid opening at the side away from the substrate;

and removing the third photoresist layer and the metal electrode layer on the third photoresist layer to form the metal electrode.

9. The method of manufacturing according to claim 1, wherein the epitaxial substrate further comprises a buffer layer and a spatial isolation layer, the buffer layer being disposed between the substrate and the channel layer, the spatial isolation layer being disposed between the channel layer and the barrier layer; in the preparation method, before the barrier layer is patterned by adopting an oxidation etching process to form a source ohmic contact groove and a drain ohmic contact groove, the method further comprises the following steps:

and patterning the barrier layer, the space isolation layer, the channel layer and the buffer layer to form a device isolation groove.

10. A preparation method of a GaN HEMT device is characterized by comprising the following steps:

providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer, a barrier layer and a p-type semiconductor layer which are sequentially stacked on the substrate;

patterning the p-type semiconductor layer to form a p-type semiconductor grid;

patterning the barrier layer to form a source ohmic contact groove and a drain ohmic contact groove; the source ohmic contact groove and the drain ohmic contact groove are formed on two opposite sides of the p-type semiconductor grid, the source ohmic contact groove exposes the source electrode in the channel layer, and the drain ohmic contact groove exposes the drain electrode in the channel layer;

forming a source ohmic contact electrode in the source ohmic contact groove, and forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is in contact with the source electrode, and the drain ohmic contact electrode is in contact with the drain electrode;

forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode, the p-type semiconductor gate and the drain ohmic contact electrode on the side away from the substrate; the passivation layer comprises a source opening, a drain opening and a gate opening, wherein a vertical projection of the source opening on the source ohmic contact electrode is positioned in the source ohmic contact electrode, a vertical projection of the drain opening on the drain ohmic contact electrode is positioned in the drain ohmic contact electrode, and a vertical projection of the gate opening on the p-type semiconductor gate is positioned in the p-type semiconductor gate;

forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrodes comprise source metal electrodes, drain metal electrodes and grid metal electrodes, the source metal electrodes are connected with the source ohmic contact electrodes through the source openings, the drain metal electrodes are connected with the drain ohmic contact electrodes through the drain openings, and the grid metal electrodes are connected with the p-type semiconductor grids through the grid openings;

wherein "patterning the p-type semiconductor layer to form a p-type semiconductor gate" and "patterning the barrier layer to form at least one of a source ohmic contact recess and a drain ohmic contact recess" comprises an oxide etch process.

Technical Field

The embodiment of the invention relates to a semiconductor technology, in particular to a preparation method of a GaN HEMT device.

Background

A GaN (gallium nitride) HEMT (High Electron Mobility Transistor) device has the characteristics of High Electron Mobility, large output current, High breakdown voltage and the like, and is widely applied to High-frequency and High-power occasions.

The GaN HEMT device is a three-terminal device, the structure of the GaN HEMT device takes an AlGaN/GaN heterojunction as a main part, and the concentration of two-dimensional electron gas (2DEG) in the AlGaN/GaN heterojunction is controlled through a Schottky barrier below a grid electrode, so that the control of current between a source electrode and a drain electrode is realized. Fig. 1 is a schematic structural view of a normally-on GaN HEMT device, showing the main film structure of the GaN HEMT device. Referring to fig. 1, a film structure of the thin film transistor is, from bottom to top, a substrate (Si)01, a channel layer (GaN)03, and a barrier layer (AlGaN)05, wherein a gate metal electrode 071 is disposed above the barrier layer 05, the gate metal electrode 071 is opposite to an active region in the channel layer, metal electrodes (051 and 052) are further disposed in the barrier layer 05 on opposite sides of the gate metal electrode 071, and the two metal electrodes are respectively in contact with a source region (hereinafter referred to as a source) and a drain region (hereinafter referred to as a drain) in the channel layer 03. In order to realize efficient transmission of an electrical signal, ohmic contacts with low contact resistance are generally formed between the metal electrode and the source electrode and between the metal electrode and the drain electrode. Therefore, the quality of the ohmic contact directly affects the performance indexes of the device, such as output saturation current, on-resistance, breakdown voltage and the like.

As shown in fig. 1, when forming ohmic contact electrodes of a source and a drain (051 and 052), it is necessary to etch the barrier layer to expose the channel layer at the source and the drain, and then prepare a metal electrode so that the metal electrode forms ohmic contact with the source and the drain. At present, chlorine-based gas etching is often adopted in the etching process. However, in the etching method, the etching depth is mainly controlled by controlling the etching time, and the etching time is often difficult to accurately control, so that the etching depth is difficult to accurately control, and if the etching is not completed, good ohmic contact cannot be formed, the ohmic contact quality is reduced, the on-resistance of a device is increased, and the output saturation current is reduced. In addition, the plasma can damage the surface of the sample in the etching process, so that the surface appearance of an ohmic contact area is rough, the ohmic contact quality is further reduced, the on-resistance of the device is increased, and the output saturation current is reduced.

Disclosure of Invention

The embodiment of the invention provides a preparation method of a GaN HEMT device, which can accurately control the etching depth, improve the etching morphology of an ohmic contact area, realize the effects of improving the ohmic contact quality, improving the output saturation current and improving the device performance.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a GaN HEMT device, including:

providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate;

patterning the barrier layer by adopting an oxidation etching process to form a source electrode ohmic contact groove and a drain electrode ohmic contact groove; the source ohmic contact groove exposes a source electrode in the channel layer, and the drain ohmic contact groove exposes a drain electrode in the channel layer;

forming a source ohmic contact electrode in the source ohmic contact groove and simultaneously forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is contacted with the source electrode, and the drain ohmic contact electrode is contacted with the drain electrode;

forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side away from the substrate; the passivation layer comprises a source electrode opening, a drain electrode opening and a grid electrode opening, wherein the vertical projection of the source electrode opening on the source electrode ohmic contact electrode is positioned in the source electrode ohmic contact electrode, the vertical projection of the drain electrode opening on the drain electrode ohmic contact electrode is positioned in the drain electrode ohmic contact electrode, and the vertical projection of the grid electrode opening on the barrier layer is positioned between the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode;

forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrode comprises a source metal electrode, a drain metal electrode and a grid metal electrode, the source metal electrode is connected with the source ohmic contact electrode through a source opening, the drain metal electrode is connected with the drain ohmic contact electrode through a drain opening, and the grid metal electrode is connected with the barrier layer through a grid opening.

Optionally, patterning the barrier layer by using an oxidation etching process to form a source ohmic contact groove and a drain ohmic contact groove, including:

forming a patterned first photoresist layer on one side of the barrier layer, which is far away from the substrate; the first photoresist layer does not cover the region corresponding to the source electrode and the drain electrode in the barrier layer;

oxidizing the barrier layer by using the first photoresist layer as a mask to form an oxidation structure;

and removing the oxidation structure to form a source ohmic contact groove and a drain ohmic contact groove.

Optionally, the oxidation barrier layer comprises: oxidizing the barrier layer with oxygen plasma;

removing the oxidized structure, comprising: and removing the oxidation structure by using dilute hydrochloric acid.

Optionally, the oxidation process parameters when the oxygen plasma is used to oxidize the barrier layer include: the power of the upper electrode is 100W-450W, the power of the lower electrode is 20W-80W, the flow rate of oxygen is 20 sccm-80 sccm, the pressure of the chamber is 5 mToor-20 mToor, and the oxidation time is 1 min-5 min;

the volume ratio of the hydrochloric acid to the water in the dilute hydrochloric acid is 1: 3-1: 5.

Optionally, forming a source ohmic contact electrode in the source ohmic contact groove and forming a drain ohmic contact electrode in the drain ohmic contact groove at the same time includes:

forming a contact electrode layer on one side of the first photoresist layer, the source ohmic contact groove and the drain ohmic contact groove, which is far away from the substrate;

and removing the first photoresist layer and the contact electrode layer on the first photoresist layer, and carrying out annealing treatment to form a source ohmic contact electrode and a drain ohmic contact electrode.

Optionally, the contact electrode layer comprises Ti₅Al₁Alloy layer and TiN metal cap layer, Ti₅Al₁Alloy layer andand the TiN metal cap layer is stacked along the direction departing from the substrate.

Optionally, forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode, and the drain ohmic contact electrode on a side away from the substrate includes:

forming an initial passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side departing from the substrate;

forming a second patterned photoresist layer on one side of the initial passivation layer, which is far away from the substrate, wherein the second photoresist layer does not cover partial areas, corresponding to the source ohmic contact electrode, the drain ohmic contact electrode and the barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode, in the initial passivation layer;

and etching the initial passivation layer by taking the second photoresist layer as a mask to form a patterned passivation layer.

Optionally, forming a metal electrode on a side of the passivation layer facing away from the epitaxial substrate includes:

forming a patterned third photoresist layer on the passivation layer, wherein the vertical projection of the third photoresist layer on the substrate is positioned in the vertical projection of the passivation layer on the substrate;

forming a metal electrode layer on the third photoresist layer, the source opening, the drain opening and the side, away from the substrate, of the grid opening;

and removing the third photoresist layer and the metal electrode layer on the third photoresist layer to form a metal electrode.

Optionally, the epitaxial substrate further includes a buffer layer and a space isolation layer, the buffer layer is disposed between the substrate and the channel layer, and the space isolation layer is disposed between the channel layer and the barrier layer; in the preparation method, before the barrier layer is patterned by adopting an oxidation etching process to form the source ohmic contact groove and the drain ohmic contact groove, the method further comprises the following steps:

and patterning the barrier layer, the space isolation layer, the channel layer and the buffer layer to form a device isolation groove.

The embodiment of the invention also provides a preparation method of the GaN HEMT device, which comprises the following steps:

providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer, a barrier layer and a p-type semiconductor layer which are sequentially stacked on the substrate;

patterning the p-type semiconductor layer to form a p-type semiconductor grid;

patterning the barrier layer to form a source ohmic contact groove and a drain ohmic contact groove; a source ohmic contact groove and a drain ohmic contact groove are formed on two opposite sides of the p-type semiconductor grid, the source ohmic contact groove exposes the source in the channel layer, and the drain ohmic contact groove exposes the drain in the channel layer;

forming a source ohmic contact electrode in the source ohmic contact groove and simultaneously forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is contacted with the source electrode, and the drain ohmic contact electrode is contacted with the drain electrode;

forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode, the p-type semiconductor grid and the drain ohmic contact electrode on the side away from the substrate; the passivation layer comprises a source electrode opening, a drain electrode opening and a grid electrode opening, wherein the vertical projection of the source electrode opening on the source electrode ohmic contact electrode is positioned in the source electrode ohmic contact electrode, the vertical projection of the drain electrode opening on the drain electrode ohmic contact electrode is positioned in the drain electrode ohmic contact electrode, and the vertical projection of the grid electrode opening on the p-type semiconductor grid electrode is positioned in the p-type semiconductor grid electrode;

forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrode comprises a source metal electrode, a drain metal electrode and a grid metal electrode, the source metal electrode is connected with the source ohmic contact electrode through a source opening, the drain metal electrode is connected with the drain ohmic contact electrode through a drain opening, and the grid metal electrode is connected with the p-type semiconductor grid through a grid opening;

wherein the patterning the p-type semiconductor layer to form the p-type semiconductor gate and the patterning the barrier layer to form at least one of the source ohmic contact groove and the drain ohmic contact groove comprises an oxide etching process.

According to the embodiment of the invention, the source ohmic contact groove and the drain ohmic contact groove are formed in the barrier layer through an oxidation etching process, the oxidation etching process is carried out in two steps, firstly, the region corresponding to the source and the drain in the barrier layer is oxidized to form an oxide, and then the oxide is removed to form the groove. In the oxidation process, the oxide layer that forms can cover on the barrier layer surface, prevents further oxidation, and consequently, the depth that the barrier layer can be oxidized is limited, can not increase along with the extension of oxidation time to can realize the control of oxidation depth, and the etching process is then only carried out the sculpture to the barrier layer of oxidizing, thereby can avoid damaging the rete outside the regional oxidation, obtains good source electrode ohmic contact recess of appearance and drain electrode ohmic contact recess. The oxidation etching method solves the problems that the etching depth is difficult to control, etching damage is caused and the like when chlorine-based gas is adopted for etching, realizes the effects of accurately controlling the etching depth and improving the etching appearance of an ohmic contact area, and thus achieves the purposes of improving the ohmic contact quality, improving the output saturation current and improving the device performance.

Drawings

FIG. 1 is a schematic structural diagram of a normally-on GaN HEMT device;

fig. 2 is a schematic flow chart of a method for manufacturing a GaN HEMT device according to an embodiment of the present invention;

fig. 3-8 are schematic views illustrating a process for manufacturing a normally-on GaN HEMT device according to an embodiment of the present invention;

fig. 9 is a schematic flow chart of another method for manufacturing a GaN HEMT device according to an embodiment of the present invention;

fig. 10-16 are schematic views of a process for manufacturing a normally-off GaN HEMT device according to embodiments of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The GaN HEMT device comprises a normally-on device and a normally-off device, wherein grooves are formed on a barrier layer firstly, and then metal is deposited to form ohmic contact electrodes of a source electrode and a drain electrode. The embodiment of the invention takes the normally-on type GaN HEMT device and the normally-off type GaN HEMT device as examples, introduces the preparation method thereof, and the method can accurately control the etching depth and improve the etching morphology, thereby improving the ohmic contact quality.

Fig. 2 is a manufacturing method of a GaN HEMT device according to an embodiment of the present invention, which is suitable for manufacturing a normally-open GaN HEMT device. Fig. 3 to 8 are schematic views of a manufacturing process of a normally-on GaN HEMT device according to an embodiment of the present invention, and the manufacturing process of the normally-on GaN HEMT device is described below with reference to fig. 2 to 8. As shown in fig. 2, the preparation method comprises the following steps:

s101, providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate;

referring to fig. 3, the epitaxial substrate may optionally include a buffer layer 02 and a space isolation layer 04 in addition to the substrate 01, the channel layer 03, and the barrier layer 05, the buffer layer 02 being disposed between the substrate 01 and the channel layer 03, and the space isolation layer 04 being disposed between the channel layer 03 and the barrier layer 05. The barrier layer 05 and the channel layer 03 form a semiconductor heterojunction of the GaN HEMT device, two-dimensional electron gas with high electron mobility can be formed at the interface of the semiconductor heterojunction under the action of gate voltage, and the two-dimensional electron gas is transmitted between a source electrode and a drain electrode in the channel layer to form current. The space isolation layer 04 is provided to confine the two-dimensional electron gas to the side of the channel layer 03 close to the barrier layer 05. The buffer layer 02 is provided to reduce current leakage during device operation.

Illustratively, the substrate material may be Si, the buffer layer material may be GaN, the channel layer material may be GaN, the space isolation layer material may be AlN, and the barrier layer material may be AlGaN.

It should be noted that fig. 3 to 8 exemplarily show a process flow of fabricating a GaN HEMT device including a buffer layer and a space isolation layer for the convenience of the subsequent description. The buffer layer and the spatial isolation layer may be selectively disposed by those skilled in the art according to actual requirements, which is not limited by the embodiment of the present invention.

S102, patterning the barrier layer by adopting an oxidation etching process to form a source ohmic contact groove and a drain ohmic contact groove; the source ohmic contact groove exposes a source electrode in the channel layer, and the drain ohmic contact groove exposes a drain electrode in the channel layer;

referring to fig. 5, after the oxidation etching process, a source ohmic contact recess 0510 and a drain ohmic contact recess 0520 are formed in the barrier layer 05.

The oxidation etching process is a novel etching process provided by the embodiment of the invention, and particularly relates to a process for performing oxidation treatment and then etching treatment. The regions to be etched in the barrier layer 05 (i.e., the regions 0510 and 0520) may be formed into oxide structures by an oxidation process, and then the oxide structures may be removed to form recesses. In the oxidation treatment process, the formed oxidation layer covers the surface of the barrier layer to prevent further oxidation, so that the oxidation depth of the barrier layer is limited and cannot be increased along with the extension of the oxidation time, the inaccuracy of controlling the etching depth by controlling the time can be avoided, and the accurate control of the etching depth is realized. Illustratively, the etching process may employ wet etching. The oxide structure can be removed only in the etching treatment process, and other areas cannot be damaged, so that the problem of poor etching appearance of an ohmic contact area due to etching damage of chlorine-based gas in the etching process is solved. The process parameters used in the oxidation process and the etching process will be described in the following, and will not be described in detail.

S103, forming a source ohmic contact electrode in the source ohmic contact groove, and forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is contacted with the source electrode, and the drain ohmic contact electrode is contacted with the drain electrode;

referring to fig. 6, the source ohmic contact electrode 051 forms an ohmic contact with the source electrode, and the drain ohmic contact electrode 052 forms a drain contact with the drain electrode. The formation of the source and drain ohmic contact electrodes will be described in detail later, and will not be described herein too much.

S104, forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side departing from the substrate; the passivation layer comprises a source electrode opening, a drain electrode opening and a grid electrode opening, wherein the vertical projection of the source electrode opening on the source electrode ohmic contact electrode is positioned in the source electrode ohmic contact electrode, the vertical projection of the drain electrode opening on the drain electrode ohmic contact electrode is positioned in the drain electrode ohmic contact electrode, and the vertical projection of the grid electrode opening on the barrier layer is positioned between the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode;

referring to fig. 7, a passivation layer 06 is formed on the surface of the GaN HEMT device and may function as a protection device. The formation of the passivation layer will be described in detail later and will not be described in detail. By forming the gate opening 061, the source opening 062, and the drain opening 063 in the passivation layer, provision is made for the subsequent formation of the external electrode pin of the GaN HEMT device.

S105, forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrode comprises a source metal electrode, a drain metal electrode and a grid metal electrode, the source metal electrode is connected with the source ohmic contact electrode through a source opening, the drain metal electrode is connected with the drain ohmic contact electrode through a drain opening, and the grid metal electrode is connected with the barrier layer through a grid opening.

Referring to fig. 8, the gate metal electrode 071, the source metal electrode 072 and the drain metal electrode 073 are external electrode pins of the GaN HEMT device, through which the GaN HEMT device is electrically connected in the operating circuit. The formation of the gate metal electrode, the source metal electrode and the drain metal electrode will be described in detail later, and will not be described herein too much.

It should be noted that, in the actual production process of the GaN HEMT device, the gate opening, the source opening, and the drain opening are not formed at the same time, the gate metal electrode, the source metal electrode, and the drain metal electrode are not formed at the same time, and different metal materials may be used for the gate metal electrode, the source metal electrode, and the drain metal electrode. In an actual manufacturing process, a source opening and a drain opening are usually formed on a passivation layer, and then a source metal electrode and a drain metal electrode are formed. And after the GaN HEMT device is subjected to performance test, forming a grid opening on the passivation layer and then forming a grid metal electrode to obtain a final product. For convenience of description, the gate metal electrode, the source metal electrode and the drain metal electrode are prepared at the same time for illustration.

According to the embodiment of the invention, the source ohmic contact groove and the drain ohmic contact groove are formed in the barrier layer through an oxidation etching process, the oxidation etching process is carried out in two steps, firstly, the region corresponding to the source and the drain in the barrier layer is oxidized to form an oxide, and then the oxide is removed to form the groove. In the oxidation process, the oxide layer that forms can cover on the barrier layer surface, prevents further oxidation, and consequently the depth that the barrier layer can be oxidized is limited, can not increase along with the extension of oxidation time to can realize the control of oxidation depth, and the etching process is then only carried out the sculpture to the barrier layer of oxidizing, thereby can avoid damaging the rete outside the regional oxidation, obtains good source electrode ohmic contact recess of appearance and drain electrode ohmic contact recess. The oxidation etching method solves the problems that the etching depth is difficult to control, etching damage is caused and the like when chlorine-based gas is adopted for etching, realizes the effects of accurately controlling the etching depth and improving the etching appearance of an ohmic contact area, and thus achieves the purposes of improving the ohmic contact quality, improving the output saturation current and improving the device performance.

Based on the above embodiments, the method for manufacturing the normally-on GaN HEMT device will be described in further detail below with reference to fig. 3 to 8.

Optionally, before patterning the barrier layer by using an oxidation etching process to form the source ohmic contact groove and the drain ohmic contact groove (S102), the method further includes: and patterning the barrier layer, the space isolation layer, the channel layer and the buffer layer to form a device isolation groove.

Referring to fig. 4, a device isolation trench 011 serves to isolate devices. And after the preparation process is finished, cutting the epitaxial substrate along the device isolation groove to obtain a plurality of GaN HEMT devices.

Illustratively, forming the device isolation trench may include the steps of: the first step, the epitaxial substrate is sequentially processed by CUltrasonically cleaning the sample for 5min by ketone, ultrasonically cleaning the sample by isopropanol for 10min, flushing the sample by deionized water for 10min, and drying the sample by nitrogen to remove impurities on the surface of the sample; secondly, sequentially carrying out steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the cleaned sample, and defining a device isolation graph; thirdly, placing the sample processed in the second step into a transmission cavity of ICP-RIE (inductively coupled plasma etching) equipment, and placing the sample into BCl₃/Cl₂The barrier layer, the space isolation layer and the channel layer (the buffer layer of the isolation part can also be etched) of the isolation part are etched in the etching gas to form a device isolation groove, and the etching depth can be 300 nm-500 nm.

Optionally, in S102, the barrier layer is patterned by using an oxidation etching process to form a source ohmic contact groove and a drain ohmic contact groove, and the method may include:

the method comprises the following steps that firstly, a first patterned photoresist layer is formed on one side, away from a substrate, of a barrier layer; the first photoresist layer does not cover the region corresponding to the source electrode and the drain electrode in the barrier layer;

the first photoresist layer has the same shape as the patterned barrier layer 05 shown in fig. 5, and functions as a mask to expose the barrier layer in the region to be etched and protect the barrier layer outside the region to be etched. For example, the sample forming the device isolation groove may be subjected to ultrasonic cleaning with acetone for 5min, ultrasonic cleaning with isopropanol for 10min, rinsing with deionized water for 10min, and blow-drying with nitrogen gas to remove impurities. Then, the cleaned sample is sequentially subjected to steps of spin coating, prebaking, photoetching, developing, postbaking and the like to form a first patterned photoresist layer so as to define (expose) ohmic contact regions of the source electrode and the drain electrode.

Secondly, oxidizing the barrier layer by taking the first photoresist layer as a mask to form an oxidation structure;

alternatively, the barrier layer may be oxidized using an oxygen plasma. Further optionally, the oxidation process parameters when the oxygen plasma is used to oxidize the barrier layer include: the upper electrode power (ICP power) is 100W-450W, the lower electrode power (RF power) is 20W-80W, the oxygen flow is 20 sccm-80 sccm, the chamber pressure is 5 mToor-20 mToor, and the oxidation time is 1 min-5 min.

Illustratively, the oxidation of the barrier layer in the ohmic contact region can be performed by using an ICP-RIE apparatus, and only oxygen is introduced during the oxidation process. The control of different oxidation depths can be realized by adjusting the parameters of the ICP equipment. Specifically, the oxygen is ionized into an oxygen plasma by applying the upper electrode power, and the concentration of the oxygen plasma is determined by the upper electrode power. The power of the lower electrode is loaded to form a built-in electric field in the chamber and accelerate the oxygen plasma to fall to the surface of the sample, and the falling speed of the oxygen plasma and the depth of the oxygen plasma penetrating into the barrier layer are determined by the power of the lower electrode. The chamber pressure can be used to adjust the uniformity of the etch. During the oxidation process, the concentration of the oxygen plasma can be regulated by regulating the oxygen flow and the power of the upper electrode. When oxygen plasma concentration reaches saturation, the barrier layer with a certain depth on the surface can be oxidized, the formed oxide layer covers the surface of the barrier layer and can prevent the barrier layer with a deeper layer from being oxidized, and the oxygen plasma can not continuously permeate and oxidize the barrier layer with a deeper layer under the action of the built-in electric field, so that the automatic stop effect of oxidation is realized, the depth of the barrier layer which can be oxidized is limited, the depth can not be increased along with the extension of the oxidation time, the uncertainty of controlling the etching depth by controlling the etching time is avoided, and the purpose of controlling the oxidation depth is realized.

And thirdly, removing the oxidation structure to form a source ohmic contact groove and a drain ohmic contact groove.

Alternatively, dilute hydrochloric acid may be used to remove the oxidized structure. Because the barrier layer forms an oxidation structure with certain depth and shape after being oxidized by the oxygen plasma, when a sample is immersed in the dilute hydrochloric acid, the dilute hydrochloric acid only reacts with the oxidation structure, and the film layer outside the oxidation structure is not damaged, so that the etching damage caused by adopting chlorine-based gas etching can be avoided, and the shape of the ohmic contact groove is improved. Further optionally, the volume ratio of hydrochloric acid to water in the dilute hydrochloric acid is 1: 3-1: 5, the reaction time can be 3 min-5 min, and after the reaction is finished, the diluted hydrochloric acid can be washed with deionized water for 15min and dried with nitrogen to remove impurities.

It should be noted that the oxygen plasma oxidation process and the hydrochloric acid removal process may be repeated several times until the AlGaN barrier layer is completely etched away. Thus, the controllability of the etching depth can be further improved.

Optionally, in S103, a source ohmic contact electrode is formed in the source ohmic contact groove, and a drain ohmic contact electrode is formed in the drain ohmic contact groove at the same time, which may be implemented by the following steps:

firstly, forming a contact electrode layer on one side of the first photoresist layer, the ohmic contact groove of the source electrode and the ohmic contact groove of the drain electrode, which is far away from the substrate;

for example, after the ohmic contact groove is formed in S102, the processed sample may be immediately placed in a transmission cavity of a magnetron sputtering evaporation device, so as to prevent the sample from being further oxidized and affecting the ohmic contact effect. And coating by using a magnetron sputtering evaporation device to obtain a contact electrode layer.

And secondly, removing the first photoresist layer and the contact electrode layer on the first photoresist layer, and carrying out annealing treatment to form a source ohmic contact electrode and a drain ohmic contact electrode.

For example, the sample with the contact electrode layer deposited thereon may be immersed in a dimethylsulfoxide solution, and the first photoresist layer and the contact electrode layer on the first photoresist layer are stripped off by heating in a water bath at 60-80 ℃, and then washed with isopropyl alcohol for 10min, deionized water for 10min, and dried with nitrogen gas to remove impurities. As shown in fig. 6, after the metal stripping is completed, a source ohmic contact electrode 051 and a drain ohmic contact electrode 052 may be formed. The sample after the metal stripping is thermally annealed in the nitrogen atmosphere of 1000sccm, the annealing temperature can be set between 500 ℃ and 650 ℃, and a better ohmic contact effect can be obtained.

Optionally, the contact electrode layer comprises Ti₅Al₁Alloy layer and TiN metal cap layer, Ti₅Al₁The alloy layer and the TiN metal cap layer are stacked along the direction departing from the substrate.

In the embodiment of the invention, the Ti/Al alloy and TiN are adopted to form the gold-free ohmic contact electrode. Ti in the Ti/Al alloy can react with AlGaN to generate TiN during annealing, a plurality of N vacancies are left in the barrier layer, the two-dimensional electron gas concentration in the barrier layer is improved, Al in the Ti/Al alloy can prevent Al in AlGaN from diffusing out, and the two-dimensional electron gas concentration of the channel layer can be effectively maintained. In addition, the ratio of Ti/Al is also an important factor influencing the quality of ohmic contact, preferably, the ratio of Ti/Al in this embodiment is 5:1, and experiments show that the alloy layer formed by the ratio can maximally improve the ohmic contact effect of the device.

Optionally, in S104, a patterned passivation layer is formed on the barrier layer, the source ohmic contact electrode, and the drain ohmic contact electrode on a side away from the substrate, and the method may include:

firstly, forming an initial passivation layer on the barrier layer, the source ohmic contact electrode and the drain ohmic contact electrode on the side departing from the substrate;

for example, after the annealing of the sample is completed, the sample can be placed in a plasma enhanced chemical vapor deposition device to evaporate an initial passivation layer so as to protect the device. The material of the initial passivation layer can be selected from Si₃N₄And the thickness may be 150 nm. After the initial passivation layer is formed, an opening needs to be formed in the initial passivation layer to prepare an external metal pin of a device to be manufactured subsequently.

Secondly, forming a second patterned photoresist layer on one side of the initial passivation layer, which is far away from the substrate, wherein the second photoresist layer does not cover partial areas, corresponding to the source ohmic contact electrode, the drain ohmic contact electrode and the barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode, in the initial passivation layer;

the second photoresist layer has the same shape as the passivation layer 06 patterned in fig. 7, and functions as a mask to expose the region to be etched of the initial passivation layer and protect the initial passivation layer outside the region to be etched. For example, the sample for forming the initial passivation layer may be sequentially subjected to spin coating, pre-baking, photolithography, development, post-baking, and the like to form a patterned second photoresist layer, so as to define the opening patterns of the gate electrode, the source electrode, and the drain electrode.

And thirdly, etching the initial passivation layer by taking the second photoresist layer as a mask to form a patterned passivation layer.

Referring to FIG. 7, for example, a sample may be placed in a transfer chamber of an ICP-RIE etching apparatus at SF₆Etching off surface Si in/Ar etching gas₃N₄A passivation layer forming a gate opening 061, a source opening 062, and a drain opening 063. And then, carrying out ultrasonic cleaning on the sample for 5min by acetone, ultrasonic cleaning on the sample for 10min by isopropanol, washing the sample for 10min by deionized water, and drying the sample by nitrogen to remove impurities, so as to prepare for a subsequent process.

Optionally, in S105, a metal electrode is formed on a side of the passivation layer away from the epitaxial substrate, and the following steps may be adopted:

a first step of forming a third patterned photoresist layer on the passivation layer, wherein the vertical projection of the third photoresist layer on the substrate is positioned in the vertical projection of the passivation layer on the substrate;

for example, the sample with the opening formed in S104 may be sequentially subjected to spin coating, pre-baking, photolithography, developing, post-baking, and the like to form a patterned third photoresist layer to define the metal electrode patterns of the gate electrode, the source electrode, and the drain electrode. The third photoresist layer has a similar shape to the passivation layer 06 in fig. 7, and in this embodiment, by setting the vertical projection of the third photoresist layer on the substrate to be located in the vertical projection of the passivation layer on the substrate, the opening area of the third photoresist layer can be larger than the opening area of the passivation layer, so as to ensure that at least a portion of the metal electrode is located on the passivation layer, and improve the firmness of the metal electrode.

Secondly, forming a metal electrode layer on the third photoresist layer, the source opening, the drain opening and the grid opening which are far away from the substrate;

for example, after forming the opening, the sample may be placed in an electron beam evaporation apparatus to deposit a metal electrode layer, the material of the metal electrode layer may be Ti, Al, Ti, and Au in sequence along a direction away from the substrate, and the thickness of each metal layer may be 20nm, 110nm, 40nm, and 50nm in sequence.

And thirdly, removing the third photoresist layer and the metal electrode layer on the third photoresist layer to form a metal electrode.

For example, after the metal electrode layer is formed, the sample may be immersed in a dimethyl sulfoxide solution, and metal stripping may be performed by heating in a water bath at 60 ℃ to 80 ℃ to remove the third photoresist layer and the metal electrode layer on the third photoresist layer. After stripping, the sample is washed by isopropanol for 10min, washed by deionized water for 10min and dried by nitrogen gas to remove impurities. As shown in fig. 8, after the metal is stripped, the gate metal electrode 071, the source metal electrode 072 and the drain metal electrode 073 are exposed outside the device as external pins for connecting to a working circuit, and the passivation layer 06 protects the device.

Fig. 9 is another method for manufacturing a GaN HEMT device according to an embodiment of the present invention, which is suitable for manufacturing a normally-off GaN HEMT device. Fig. 10 to 16 are schematic views of a manufacturing process of a normally-off GaN HEMT device according to an embodiment of the present invention, and the manufacturing process of the normally-off GaN HEMT device is described below with reference to fig. 9 to 16.

First, it should be noted that there are many methods for realizing a normally-off type GaN HEMT, such as insertion of a p-GaN type gate, a recessed gate technique, and a fluorine ion implantation technique. The embodiments of the present invention and the accompanying drawings describe a method for fabricating a normally-off device by inserting a p-type semiconductor gate (e.g., p-GaN) on the basis of a normally-on device. Since the structures of the normally-off device and the normally-on device have a plurality of same film structures, the materials and the processing processes of the same film structures can be referred to the above description of the normally-on device, and will not be described in detail later.

As shown in fig. 9, the preparation method includes the steps of:

s201, providing an epitaxial substrate; the epitaxial substrate comprises a substrate, and a channel layer, a barrier layer and a p-type semiconductor layer which are sequentially stacked on the substrate;

the schematic structure of this step is shown in fig. 10. Illustratively, the material of the p-type semiconductor layer 08 may be p-GaN.

S202, patterning the p-type semiconductor layer to form a p-type semiconductor grid;

the schematic structure of this step is shown in fig. 12. By etching the p-type semiconductor layer 08, a p-type semiconductor gate 081 can be formed at a portion corresponding to the active region of the channel layer 03 to exhaust two-dimensional electron gas between the barrier layer 05 and the channel layer 03, so that the device is turned off, and a normally-off GaN HEMT device is formed.

Because the p-type semiconductor layer is positioned on the barrier layer, if the etching is excessive, the barrier layer is thinned, the concentration of two-dimensional electron gas is reduced, and the output saturation current of the device is reduced. Therefore, the patterning of the p-type semiconductor grid electrode can be carried out by adopting the oxidation etching process, so that the etching depth can be accurately controlled, and the etching damage can be avoided.

S203, patterning the barrier layer to form a source ohmic contact groove and a drain ohmic contact groove; a source ohmic contact groove and a drain ohmic contact groove are formed on two opposite sides of the p-type semiconductor grid, the source ohmic contact groove exposes the source in the channel layer, and the drain ohmic contact groove exposes the drain in the channel layer;

as shown in fig. 13, after the barrier layer 05 is patterned, a source ohmic contact recess 0510 and a drain ohmic contact recess 0520 may be formed.

S204, forming a source ohmic contact electrode in the source ohmic contact groove, and forming a drain ohmic contact electrode in the drain ohmic contact groove; the source ohmic contact electrode is contacted with the source electrode, and the drain ohmic contact electrode is contacted with the drain electrode;

as shown in fig. 14, an active ohmic contact electrode 051 is formed in the source ohmic contact groove, and a drain ohmic contact electrode 052 is formed in the drain ohmic contact groove.

S205, forming a patterned passivation layer on the barrier layer, the source ohmic contact electrode, the p-type semiconductor grid and the drain ohmic contact electrode on the side away from the substrate; the passivation layer comprises a source electrode opening, a drain electrode opening and a grid electrode opening, wherein the vertical projection of the source electrode opening on the source electrode ohmic contact electrode is positioned in the source electrode ohmic contact electrode, the vertical projection of the drain electrode opening on the drain electrode ohmic contact electrode is positioned in the drain electrode ohmic contact electrode, and the vertical projection of the grid electrode opening on the p-type semiconductor grid electrode is positioned in the p-type semiconductor grid electrode;

this step is schematically illustrated in fig. 15, and the patterned passivation layer 06 includes a gate opening 061, a source opening 062, and a drain opening 063.

S206, forming a metal electrode on one side of the passivation layer, which is far away from the epitaxial substrate; the metal electrode comprises a source metal electrode, a drain metal electrode and a grid metal electrode, the source metal electrode is connected with the source ohmic contact electrode through a source opening, the drain metal electrode is connected with the drain ohmic contact electrode through a drain opening, and the grid metal electrode is connected with the p-type semiconductor grid through a grid opening.

As shown in fig. 16, a gate metal electrode 071, a source metal electrode 072 and a drain metal electrode 073 are formed in the opening of the passivation layer 06.

In the above step, the "patterning the p-type semiconductor layer, forming the p-type semiconductor gate" and the "patterning the barrier layer, forming at least one of the source ohmic contact groove and the drain ohmic contact groove" includes an oxide etching process.

Preferably, the step of patterning the p-type semiconductor layer to form the p-type semiconductor grid and the step of patterning the barrier layer to form the source ohmic contact groove and the drain ohmic contact groove are carried out by adopting an oxidation etching process, so that the etching depth is accurately controlled, and the etching damage is avoided.

Next, with reference to fig. 10 to 16, a complete process flow for manufacturing a normally-off GaN HEMT device is provided. The preparation process flow comprises the following steps:

1. and (3) carrying out ultrasonic cleaning on the epitaxial substrate for 5min by acetone, ultrasonic cleaning for 10min by isopropanol, washing for 10min by deionized water, and carrying out blow-drying by nitrogen to remove impurities on the surface of the sample. Fig. 10 shows the structure of an epitaxial substrate, which illustratively includes, in order from bottom to top, a Si substrate 01, a GaN buffer layer 02, a GaN channel layer 03, an AlN space isolation layer 04, an AlGaN barrier layer 06, and a p-type semiconductor (p-GaN) layer 08.

2. And sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the cleaned sample, and defining a device isolation region.

3. Placing the sample processed in the step 2 in a transmission cavity of ICP-RIE etching equipment, and placing the sample in BCl₃/Cl₂Etching the p-GaN/AlGaN/GaN layer of the isolation part in the etching gas, wherein the etching depth is 300 nm-500 nm. The structure after etching is shown in fig. 11.

4. And (3) ultrasonically cleaning the etched sample in the step (3) for 5min by acetone, ultrasonically cleaning the sample by isopropanol for 10min, flushing the sample by deionized water for 10min, and drying the sample by nitrogen.

5. And sequentially carrying out steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the cleaned sample to define the p-GaN grid region.

6. And (5) placing the sample processed in the step (5) in a transmission cavity of ICP-RIE etching equipment, and performing a p-GaN etching process by using an oxidation etching method to form a p-GaN grid electrode. First, p-GaN is oxidized into Ga₂O₃Only 40sccmO is introduced in the oxidation process₂. Preferably, ICP power is set to 100W, RF power is set to 40W, chamber pressure is set to 15mTorr, and oxidation time is set to 3 min.

7. The oxidized sample was then immersed in a dilute hydrochloric acid solution (HCl: H)₂O is 1: 4) removing an oxide layer on the surface of the sample in 3min, then washing with deionized water for 15min, and finally drying with nitrogen.

8. Steps 6 and 7 are repeated until the p-GaN layer is completely etched away. The structure after etching the p-GaN layer is shown in fig. 12.

9. And (3) ultrasonically cleaning the etched sample in the step (8) for 5min by acetone, ultrasonically cleaning the sample by isopropanol for 10min, flushing the sample by deionized water for 10min, and drying the sample by nitrogen.

10. And sequentially carrying out steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the cleaned sample, and defining ohmic contact patterns of the source electrode and the drain electrode.

11. And (3) placing the sample processed in the step (10) in a transmission cavity of ICP-RIE etching equipment, and etching the AlGaN barrier layer by using an oxidation etching method (access process of ohmic contact). Firstly, oxidizing the AlGaN layer of the ohmic contact part, and only introducing 40sccm O in the oxidation process₂. Preferably, ICPpower is set at 100W, RF power is set at 40W, chamber pressure is 15mTorr, and oxidation is performedThe time is 3 min.

12. The sample treated in step 11 was immersed in a dilute hydrochloric acid solution (HCl: H)₂O is 1: 4) removing an oxide layer on the surface of the sample in 3min, then washing with deionized water for 15min, and finally drying with nitrogen.

13. Steps 11 and 12 are repeated until the AlGaN barrier layer is completely etched away. The structure of the AlGaN barrier layer after etching is shown in fig. 13.

14. And (4) immediately putting the sample treated in the step (13) into a transmission cavity of a magnetron sputtering evaporation device, so as to avoid further oxidation of the sample and influence on ohmic contact effect. In the coating process, Ti with the thickness of 60nm to 80nm is evaporated in sequence₅Al₁An alloy layer and a 60nmTiN metal cap layer.

15. And (3) immersing the sample of the ohmic metal evaporated in the step (14) in a dimethyl sulfoxide solution, and carrying out metal stripping in a water bath heating mode at the temperature of 60-80 ℃. And after stripping, washing for 10min by isopropanol, washing for 10min by deionized water and drying by nitrogen in sequence.

16. The sample after stripping the metal is at 1000sccm N₂The thermal annealing is carried out in the atmosphere, and the annealing temperature can be set between 500 ℃ and 650 ℃ so as to obtain the best ohmic contact effect. The structure after formation of the ohmic contact electrode is shown in fig. 14.

17. After the sample annealing is finished, the sample is placed in plasma enhanced chemical vapor deposition equipment for evaporating and coating a layer of 150nm Si₃N₄And a passivation layer.

18. And (4) sequentially carrying out steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the sample processed in the step (17), and defining the opening patterns of the source electrode and the drain electrode.

19. The sample processed in the step 18 is placed in a transmission cavity of an ICP-RIE etching device at SF₆Etching off surface Si in/Ar etching gas₃N₄A source opening and a drain opening are formed.

20. And (3) ultrasonically cleaning the etched sample in the step (19) for 5min by acetone, ultrasonically cleaning the sample by isopropanol for 10min, flushing the sample by deionized water for 10min, and drying the sample by nitrogen.

21. And (3) sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the sample processed in the step (20), and defining the metal electrode patterns of the source electrode and the drain electrode.

22. And (3) putting the sample treated in the step (21) into an electron beam evaporation device, and depositing a metal electrode Ti/Al/Ti/Au (20nm/110nm/40nm/50nm) connected with the ohmic contact electrode.

23. And (3) immersing the sample of the metal electrode evaporated in the step (22) in a dimethyl sulfoxide solution, and carrying out metal stripping in a water bath heating mode at the temperature of 60-80 ℃. And after stripping, washing for 10min by isopropanol, washing for 10min by deionized water and drying by nitrogen in sequence.

24. And (4) sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the sample processed in the step (23), and defining the opening pattern of the grid.

25. Placing the sample processed in the step 24 in a transmission cavity of ICP-RIE etching equipment in SF₆Etching off surface Si in/Ar etching gas₃N₄And forming a gate opening.

26. And (4) ultrasonically cleaning the etched sample in the step (25) for 5min by acetone, ultrasonically cleaning the sample by isopropanol for 10min, flushing the sample by deionized water for 10min, and drying the sample by nitrogen.

27. And (3) sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the sample processed in the step (26), and defining the metal electrode pattern of the grid.

28. And (3) putting the sample treated in the step (27) into an electron beam evaporation device to deposit a metal electrode Ti/Au (40nm/100nm) of a grid electrode.

29. And (3) immersing the sample of the evaporated grid metal in the step 28 in a dimethyl sulfoxide solution, and carrying out metal stripping in a water bath heating mode at the temperature of 60-80 ℃. And after stripping, washing for 10min by isopropanol, washing for 10min by deionized water and drying by nitrogen in sequence.

It should be noted that, the above specific process introduces a preparation process of forming the source metal electrode 072 and the drain metal electrode 073 (steps 17 to 23) and then forming the gate metal electrode 071 (steps 24 to 29). Referring to fig. 15 and 16, in particular, the structure after the passivation layer is formed with the opening is shown in fig. 15, and the structure after the metal electrode is formed in the opening is shown in fig. 16.

Since the normally-off device includes all film structures in the normally-on device, a person skilled in the art can obtain a complete preparation process of the normally-on device by referring to the preparation process, and details of the embodiment of the present invention are not repeated.

Compared with the traditional preparation method, the preparation method of the normally-on device and the normally-off device provided by the embodiment of the invention applies a new oxidation etching method in the etching of the p-GaN layer and the etching of the AlGaN barrier layer. The oxidation etching method can greatly reduce the etching damage introduced in the etching process, can accurately control the etching depth, is beneficial to the formation of the subsequent ohmic contact process, can realize a low-temperature annealing process through the stress process, obtains a wider process window, and has lower requirements on equipment and processes. Meanwhile, the embodiment of the invention provides Ti₅Al₁The gold-free ohmic contact structure of the/TiN is beneficial to maintaining and even improving the concentration of the two-dimensional electron gas. The output characteristics of the device can be further improved by combining the oxidation etching process and the gold-free ohmic contact process, such as the starting voltage and the breakdown voltage of the device are improved, and meanwhile, the reliability and the stability of the device can also be improved. Particularly, for radio frequency devices, the performance improvement of ohmic contact has a great proportion to the overall performance improvement of the devices, and the oxidation etching and novel gold-free ohmic contact process can also be widely applied to the preparation process of the radio frequency devices.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.