阅读说明：本技术 半导体器件和制造半导体器件的方法 (Semiconductor device and method of manufacturing semiconductor device ) 是由 森隆弘 于 2020-02-05 设计创作，主要内容包括：本申请涉及半导体器件和制造半导体器件的方法。一种半导体器件,包括半导体衬底,该半导体衬底包括具有第一表面和第二表面的第一外延层、第二外延层、形成为穿过第一外延层和第二外延层的掩埋区域以及栅极电极。第二外延层包括漏极区域、源极区域、体区域、漂移区域、第一区域和第二区域。第一区域至少形成在漏极区域下方。第二区域在沟道长度方向上具有第一端和第二端。第一端在沟道长度方向上位于体区域和漏极区域之间。第二区域从第一端朝向第二端延伸,使得第二端至少延伸到源极区域下方。第二区域的杂质浓度大于第一区域的杂质浓度。(The present application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes a semiconductor substrate including a first epitaxial layer having a first surface and a second surface, a second epitaxial layer, a buried region formed through the first epitaxial layer and the second epitaxial layer, and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The first region is formed at least under the drain region. The second region has a first end and a second end in a channel length direction. The first end is located between the body region and the drain region in a channel length direction. The second region extends from the first end toward the second end such that the second end extends at least below the source region. The impurity concentration of the second region is greater than that of the first region.)

1. A semiconductor device, comprising:

a semiconductor substrate comprising:

a first epitaxial layer having a first conductivity type and having:

a first surface; and

a second surface opposite the first surface;

a second epitaxial layer having the first conductivity type and formed on the second surface, the second epitaxial layer having:

a third surface facing the second surface; and

a fourth surface opposite the third surface; and

a buried region having a second conductivity type opposite to the first conductivity type and formed through the first epitaxial layer and the second epitaxial layer; and

a gate electrode which is provided on the substrate,

wherein the second epitaxial layer comprises:

a drain region having the second conductivity type and formed on the fourth surface;

a source region of the second conductivity type formed on the fourth surface and spaced apart from the drain region;

a drift region having the second conductivity type and formed on the fourth surface such that the drift region surrounds the drain region;

a body region having the first conductivity type and formed on the fourth surface such that the body region surrounds the source region;

a first region having the first conductivity type and formed at a position closer to the buried region than the drift region in a thickness direction extending from the third surface to the fourth surface; and

a second region having the first conductivity type and formed at a position closer to the buried region than the first region in the thickness direction,

wherein the first region is formed at least below the drain region,

wherein the second region has a first end and a second end opposite to the first end in a channel length direction extending from the source region to the drain region,

wherein the first end is located between the body region and the drain region in the channel length direction,

wherein the second region extends from the first end to the second end such that the second end reaches at least below the source region,

wherein the impurity concentration of the second region is greater than the impurity concentration of the first region, an

Wherein the gate electrode faces the fourth surface between the source region and the drift region while the gate electrode is insulated.

2. The semiconductor device as set forth in claim 1,

wherein the trench is formed in the semiconductor substrate such that the trench extends from the fourth surface toward the first surface,

wherein the body region and the buried region are exposed from sidewalls of the trench, an

Wherein the second region extends from the first end such that the second end reaches the trench.

3. The semiconductor device as set forth in claim 2,

wherein the first region extends from below the drain region such that the first region reaches the trench.

4. The semiconductor device as set forth in claim 2,

wherein the first region is formed such that both end positions of the first region in the channel length direction coincide with both end positions of the drift region in the channel length direction, respectively.

5. The semiconductor device as set forth in claim 1,

wherein the second epitaxial layer includes a third region having the second conductivity type,

wherein the third region is formed closer to the buried region than the drift region in the thickness direction and farther from the buried region than the first region in the thickness direction,

wherein the third region has a third end and a fourth end opposite to the third end in the channel length direction,

wherein the third end is located between the body region and the drain region in the channel length direction,

wherein the third region extends from the third end towards the fourth end such that the fourth end reaches at least below the source region, an

Wherein the impurity concentration of the third region is greater than the impurity concentration of the first region.

6. The semiconductor device as set forth in claim 5,

wherein a trench is formed in the semiconductor substrate such that the trench extends from the fourth surface toward the first surface,

wherein the body region and the buried region are exposed from sidewalls of the trench, an

Wherein the third region extends such that the third region reaches the trench.

7. The semiconductor device as set forth in claim 5,

wherein the third region is formed such that positions of both ends of the third region in the channel length direction coincide with positions of both ends of the second region in the channel length direction, respectively.

8. A method of manufacturing a semiconductor device, comprising:

(a) providing a semiconductor substrate, the semiconductor substrate comprising:

a first epitaxial layer having a first conductivity type and having:

a first surface; and

a second surface opposite the first surface;

a second epitaxial layer having the first conductivity type and having:

a third surface formed on and facing the second surface; and

a fourth surface opposite the third surface; and

a buried region having a second conductivity type opposite to the first conductivity type and formed through the first epitaxial layer and the second epitaxial layer;

(b) forming a drain region having the second conductivity type on the fourth surface,

(c) forming a source region of the second conductivity type on the fourth surface and spaced apart from the drain region,

(d) forming a source region having the second conductivity type on the fourth surface,

(e) forming a drift region having the second conductivity type on the fourth surface to surround the drain region,

(f) forming a drift region having the first conductivity type on the fourth surface to surround the source region,

(g) forming a body region having the first conductivity type on the fourth surface,

(h) forming a first region having the first conductivity type at a position closer to the buried region than the drift region in a thickness direction from the third surface toward the fourth surface;

(i) forming a second region having the first conductivity type at a position closer to the buried region than the first region in the thickness direction; and

(j) a gate electrode is formed on the substrate,

wherein the first region is formed below at least the drain region;

wherein the second region has a first end and a second end opposite to the first end in a channel length direction from the source region toward the drain region,

wherein the first end is located between the body region and the drain region in the channel length direction,

wherein the second region is located from a first end to a second end such that the second end reaches below the source region; and

wherein the impurity concentration of the second region is greater than the impurity concentration of the first region.

9. The method of manufacturing a semiconductor device according to claim 8,

wherein the drift region and the first region are formed by ion implantation using the same mask.

10. The method of manufacturing a semiconductor device according to claim 8, comprising:

(k) forming a third region having the second conductivity type at a position closer to the buried region than the drift region in the thickness direction and farther from the buried region than the first region in the thickness direction,

wherein the third region has a third end and a fourth end opposite to the third end in the channel length direction,

wherein the third end is located between the body region and the drain region in the channel length direction,

wherein the third region extends from the third end towards the fourth end such that the fourth end reaches at least below the source region,

wherein the impurity concentration of the third region is larger than that of the first region, an

Wherein the second region and the third region are formed by ion implantation using the same mask.

Technical Field

The invention relates to a semiconductor device and a method of manufacturing the same.

Background

The disclosed techniques are listed below.

[ patent document 1] Japanese unexamined patent application publication No.2017-

[ patent document 2] Japanese unexamined patent application publication No.2011-

[ patent document 3] Japanese unexamined patent application publication No.2013-

Patent document 1 describes a semiconductor device including an LDMOS transistor.

The semiconductor device disclosed in patent document 1 includes a semiconductor substrate, a gate dielectric film, and a gate electrode. The semiconductor substrate includes a support substrate, an epitaxial layer formed on the support substrate, and a buried region. The conductivity type of the support substrate and the conductivity type of the epitaxial layer are p-type. The buried region is formed through the support substrate and the epitaxial layer. The conductivity type of the buried region is n-type.

The epitaxial layer has a first surface and a second surface. The first surface is a surface supporting the epitaxial layer on the substrate side. The second surface is an opposite surface of the first surface. The second surface is a main surface of the semiconductor substrate. In the epitaxial layer, a source region, a drain region, a well region, a drift region, a first region, and a second region are formed.

The source region is formed on the second surface. The drain region is formed on the second surface and spaced apart from the source region. A well region is formed on the second surface such that the well region surrounds the source region. The drift region is formed on the second surface such that the drift region surrounds the drain region. The conductivity type of the source region, the drain region and the drift region is n-type, and the conductivity type of the well region is p-type. Hereinafter, the second surface between the source region and the drift region is the channel region.

The first region is located below the drain region. The second region has one end and the other end in a channel length direction (a direction from the source region toward the drain region). One end of the second region is located between the body region and the drain region in the channel length direction. The other end of the second region is located below the source region. The first region is located between the drain region and the first surface in a thickness direction (a direction from the first surface toward the second surface). The second region is farther from the first surface than the first region in the thickness direction. The conductivity type of the first region and the second region is p-type. The impurity concentration of the second region is greater than that of the first region.

The gate electrode faces the channel region while being insulated from the gate dielectric film. The source region, the drain region, the well region, the drift region, the gate dielectric film, and the gate electrode constitute an LDMOS transistor.

Patent document 2 and patent document 3 also disclose semiconductor devices in which LDMOS transistors are formed, respectively.

Disclosure of Invention

In the semiconductor device disclosed in patent document 1, the on-breakdown voltage of the LDMOS transistor can be increased by the second region. The semiconductor device of patent document 1 includes a parasitic npn transistor having a drain region as a collector, a well region as a base, and a source region as an emitter. In the semiconductor device described in patent document 1, since the second region is farther from the first surface than the first region, the rise of the well region potential due to the potential of the buried region cannot be sufficiently suppressed. When the potential of the well region rises, the parasitic npn transistor operates, and the on-breakdown voltage decreases, so there is room for improvement in the on-resistance of the LDMOS in the semiconductor device disclosed in patent document 1.

Other problems and novel features will become apparent from the description of the specification and drawings.

A semiconductor device according to an embodiment includes: a first epitaxial layer of a first conductivity type having a first surface and a second surface opposite the first surface; a second epitaxial layer of the first conductivity type formed on the second surface and having a third surface facing the second surface and a fourth surface opposite to the third surface; a buried region of a second conductivity type opposite to the first conductivity type formed through the first epitaxial layer and the second epitaxial layer; and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The drain region is formed on the fourth surface. The source region is formed on a fourth surface spaced apart from the drain region. The drift region is formed on the fourth surface such that the drift region surrounds the drain region. The body region is formed on the fourth surface such that the body region surrounds the source region. The first region is formed at a position closer to the buried region than the drift region in a thickness direction (i.e., a direction from the third surface toward the fourth surface). The second region is formed at a position closer to the buried region than the first region in the thickness direction. The conductivity types of the body region, the first region, and the second region are the first conductivity type. The conductivity types of the drain region, the source region, and the drift region are a second conductivity type. The first region is formed at least under the drain region. The second region has a first end and a second end opposite to the first end in a channel length direction from the source region toward the drain region. The first end is located between the body region and the drain region in a channel length direction. The second region extends from the first end toward the second end such that the second end reaches at least below the source region. The impurity concentration of the second region is greater than that of the first region. The gate electrode faces the fourth surface between the source region and the drift region while being insulated.

According to the semiconductor device according to the embodiment, the on-state breakdown voltage of the LDMOS transistor can be increased.

Drawings

Fig. 1 is a schematic diagram showing a circuit configuration of a semiconductor device according to a first embodiment.

Fig. 2 is a plan view of a semiconductor device according to the first embodiment.

Fig. 3 is a cross-sectional view taken along the line III-III in fig. 2.

Fig. 4 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment.

Fig. 5 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment.

Fig. 6 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment.

Fig. 7 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment.

Fig. 8 is a cross-sectional view of the semiconductor device according to the first embodiment when the transistor Tr is composed of a plurality of fingers.

Fig. 9 is a process diagram showing a method of manufacturing a semiconductor device according to the first embodiment.

Fig. 10 is a cross-sectional view of the semiconductor device according to the first embodiment in the semiconductor substrate providing step S1.

Fig. 11 is a cross-sectional view of the semiconductor device according to the first embodiment in the first ion implantation step S2.

Fig. 12 is a cross-sectional view of the semiconductor device according to the first embodiment in the second ion implantation step S3.

Fig. 13 is a cross-sectional view of the semiconductor device according to the first embodiment in the third ion implantation step S4.

Fig. 14 is a cross-sectional view of the semiconductor device according to the first embodiment in the fourth ion implantation step S5.

Fig. 15 is a cross-sectional view of the semiconductor device according to the first embodiment in the fifth ion implantation step S6.

Fig. 16 is a cross-sectional view of the semiconductor device according to the first embodiment in the first insulating isolation film forming step S7.

Fig. 17 is a cross-sectional view of the semiconductor device according to the first embodiment in the gate dielectric film forming step S8.

Fig. 18 is a cross-sectional view of the semiconductor device according to the first embodiment in the gate forming step S9.

Fig. 19 is a cross-sectional view of the semiconductor device according to the first embodiment in the sixth ion implantation step S10.

Fig. 20 is a cross-sectional view of the semiconductor device according to the first embodiment in the sidewall spacer forming step S11.

Fig. 21 is a cross-sectional view of the semiconductor device according to the first embodiment in the seventh ion implantation step S12.

Fig. 22 is a cross-sectional view of the semiconductor device according to the first embodiment in the interlayer insulating film forming step S13.

Fig. 23 is a cross-sectional view of the semiconductor device according to the first embodiment in the second insulating film forming step S14.

Fig. 24 is a cross-sectional view of the semiconductor device according to the first embodiment in the contact plug forming step S15.

Fig. 25 is an explanatory diagram of a simulation when the second area DIF2 is formed.

Fig. 26 is an explanatory diagram of a simulation when the second area DIF2 is not formed.

Fig. 27 is a cross-sectional view of a semiconductor device according to a second embodiment.

Fig. 28 is a process diagram showing a manufacturing method of a semiconductor device according to the second embodiment.

Fig. 29 is a cross-sectional view of a semiconductor device according to a third embodiment.

Fig. 30 is a process diagram showing a method of manufacturing a semiconductor device according to the third embodiment.

Detailed Description

Details of the embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(first embodiment)

Hereinafter, a semiconductor device according to a first embodiment will be described.

(Circuit configuration of semiconductor device according to the first embodiment)

As shown in fig. 1, the semiconductor device according to the first embodiment includes, for example, a drive circuit DRC, a pre-drive circuit PDC, an emulation circuit ANC, a power supply circuit PWC, and an input/output circuit IOC. The drive circuit DRC includes, for example, a transistor Tr. The transistor Tr is an LDMOS transistor.

(configuration of LDMOS transistor in semiconductor device according to first embodiment)

As shown in fig. 2 and 3, in the region where the transistor Tr is formed, the semiconductor device according to the first embodiment includes a semiconductor substrate SUB, insulating isolation films ISL1 and ISL2, a gate dielectric film GI, and a gate electrode GE. In the region where the transistor Tr is formed, the semiconductor device according to the first embodiment further includes a sidewall spacer SWS, an interlayer insulating film ILD, an insulating isolation film ISL3, a contact plug CP1, a contact plug CP2, a contact plug CP3, a wiring WL1, and a wiring WL 2.

The semiconductor substrate SUB includes an epitaxial layer EP1, an epitaxial layer EP2, and a buried region BL. The epitaxial layer EP1 and the epitaxial layer EP2 are formed of, for example, single crystal silicon (Si) doped with impurities. The conductivity types of epitaxial layer EP1 and epitaxial layer EP2 are the first conductivity type. The first conductivity type is, for example, p-type. The epitaxial layer EP1 has a first surface F1 and a second surface F2. The second surface F2 is an opposite surface of the first surface F1. The epitaxial layer EP2 has a third surface F3 and a fourth surface F4. The fourth surface F4 is an opposite surface of the third surface F3.

Epitaxial layer EP2 is formed on epitaxial layer EP 1. More specifically, an epitaxial layer EP2 is formed on the second surface F2. The third surface F3 is opposite to the second surface F2. That is, the fourth surface F4 constitutes the main surface of the semiconductor substrate SUB.

The buried region BL is formed through the epitaxial layer EP1 and the epitaxial layer EP 2. The conductivity type of the buried region BL is the second conductivity type. The second conductivity type is an opposite conductivity type of the first conductivity type. That is, if the first conductivity type is p-type, the second conductivity type is n-type. The epitaxial layer EP1 and the epitaxial layer EP2 are electrically isolated from each other by the buried region BL.

A drain region DRA, a source region SR, a drift region DRI, a body region BR and a body contact region BCR are formed in the epitaxial layer EP 2.

The drain region DRA is formed in the fourth surface F4. The source region SR is formed on the fourth surface F4 remote from the drain region DRA. The source region SR has a first portion SRa and a second portion SRb. The first portion SRa is closer to the drain region DRA than the second portion SRb. The impurity concentration of the first portion SRa is smaller than that of the second portion SRb. In other words, the source region SR has a Lightly Doped Diffusion (LDD) structure. The conductivity types of the drain region DRA and the source region SR are the second conductivity type.

The drift region DRI is formed on the fourth surface F4 such that the drift region DRI surrounds the drain region DRA. The conductivity type of the drift region DRI is the second conductivity type. The impurity concentration of the drift region DRI is smaller than that of the drain region DRA.

The body region BR is formed on the fourth surface F4 such that the body region BR surrounds the source region SR. The conductivity type of the body region BR is the first conductivity type. The impurity concentration of body region BR is greater than the impurity concentration of epitaxial layer EP 2.

The body contact region BCR is formed on the fourth surface F4. The body contact region BCR is arranged adjacent to the source region SR on the side opposite to the drain region DRA. The body contact region BCR is surrounded by a body region BR. The conductivity type of the body contact region BCR is the first conductivity type. The impurity concentration of the body contact region BCR is greater than the impurity concentration of the body region BR.

The groove TR1 is formed on the fourth surface F4. The groove TR1 extends from the fourth surface F4 toward the third surface F3. The trench TR1 is located between the drain region DRA and the source region SR such that the trench TR1 is surrounded by the drift region DRI. The insulating isolation film ISL1 is buried in the trench TR 1. The insulating isolation film ISL1 is made of, for example, silicon oxide (SiO)₂) And (4) forming. The trench TR1 and the insulating isolation film ISL1 have a Shallow Trench Isolation (STI) structure. The insulating isolation film ISL1 (trench TR1) is formed such that the insulating isolation film ISL1 surrounds the drain region DRA in plan view (see fig. 2). The insulating isolation film ISL1 may be a local oxidation of silicon (LCOS).

A trench TR2 is formed on the fourth surface F4. The trench TR2 is located adjacent to the body contact region BCR on the other side compared to the source region SR. The groove TR2 extends from the fourth surface F4 toward the third surface F3. The trench TR2 is surrounded by a body region BR. The insulating isolation film ISL2 is buried in the trench TR 2. The insulating isolation film ISL2 is formed of, for example, silicon oxide. The trench TR2 and the insulating isolation film ISL2 have an STI structure. The insulating isolation film ISL2 (trench TR2) is formed such that the insulating isolation film ISL2 surrounds the body contact region BCR in a plan view. The insulating isolation film ISL2 may be LOCOS.

The gate dielectric film GI is formed on the fourth surface F4 between the source region SR and the trench TR 1. The gate dielectric film GI is formed of, for example, silicon oxide.

The gate electrode GE is formed on the gate dielectric film GI. The gate electrode GE may extend over the insulating isolation film ISL 1. Gate electrode GE faces the channel region (fourth surface F4 disposed between source region SR and drift region DRI) while being insulated from the channel region by gate dielectric film GI. The gate electrode GE is formed of, for example, polycrystalline silicon doped with impurities.

Drain region DRA, source region SR, drift region DRI, body region BR, gate dielectric film GI, and gate electrode GE constitute a transistor Tr.

A sidewall spacer SWS is formed on the first portion SRa such that the sidewall spacer SWS contacts the first side surface of the gate electrode GE. A sidewall spacer SWS is formed on the insulating isolation film ISL1 such that the sidewall spacer SWS is in contact with the second side surface of the gate electrode GE. The second side surface is a side surface of the gate electrode GE opposite to the first side surface of the gate electrode GE. The sidewall spacer SWS is made of, for example, silicon oxide and silicon nitride (Si)₃N) is formed.

An interlayer insulating film ILD is formed on the fourth surface F4 such that the interlayer insulating film ILD covers the gate electrode GE and the sidewall spacer SWS. The interlayer insulating film ILD is formed of, for example, silicon oxide.

A trench TR3 is formed in the interlayer insulating film ILD, the semiconductor substrate SUB, and the insulating isolation film ISL 2. The trench TR3 extends from the fourth surface F4 toward the first surface F1 in the semiconductor substrate SUB. The trench TR3 is formed such that the trench TR3 penetrates the buried region BL. From another perspective, the interlayer insulating film ILD, the insulating isolation film ISL2, the body region BR, the epitaxial layer EP2, the buried region BL, and the epitaxial layer EP1 are exposed from the side surfaces of the trench TR 3. The insulating isolation film ISL3 is buried in the trench TR 3. The insulating isolation film ISL3 is formed of, for example, silicon oxide. The trench TR3 and the insulating isolation film ISL3 are formed in a Deep Trench Isolation (DTI) structure. The insulating isolation film ISL3 (trench TR3) is formed such that the insulating isolation film ISL3 surrounds the transistor TR in a plan view.

The contact plug CP1, the contact plug CP2, and the contact plug CP3 are formed in the interlayer insulating film ILD. More specifically, the contact plug CP1, the contact plug CP2, and the contact plug CP3 are buried in a contact hole formed in the interlayer insulating film ILD. The contact plugs CP1, CP2, and CP3 are electrically connected to the drain region DRA, the source region SR, and the body contact region BCR, respectively. The contact plugs CP1, CP2, and CP3 are formed of, for example, tungsten (W).

The wiring WL1 and the wiring WL2 are formed on the interlayer insulating film ILD. The wiring WL1 is electrically connected to the contact plug CP1, and the wiring WL2 is electrically connected to the contact plug CP2 and the contact plug CP 3. The wiring WL1 and the wiring WL2 are formed of, for example, an aluminum (Al) alloy, a copper (Cu) alloy, or the like.

The epitaxial layer EP2 further includes a first region DIF1, a second region DIF2, and a third region DIF3 in the semiconductor device according to the first embodiment. The conductivity types of the first region DIF1, the second region DIF2, and the third region DIF3 are the first conductivity type.

The impurity concentration of the second region DIF2 is greater than that of the first region DIF 1. The impurity concentration of the third region DIF3 is greater than that of the first region DIF 1. Preferably, the impurity concentration of the third region DIF3 is greater than that of the second region DIF 2. The impurity concentration of the first region DIF1, the second region DIF2, and the third region DIF3 is larger than that of the epitaxial layer EP 2.

The first region DIF1 is closer to the third surface F3 than the drift region DRI and the body region BR in the thickness direction of the epitaxial layer EP2 (the direction from the third surface F3 to the fourth surface F4). From another point of view, the first region DIF1 is closer to the buried region BL than the drift region DRI and the body region BR in the thickness direction of the epitaxial layer EP 2. The first area DIF1 is formed to pass through the area in which the transistor Tr is formed.

The second region DIF2 is closer to the third surface F3 than the first region DIF1 in the thickness direction of the epitaxial layer EP2, that is, closer to the buried region BL than the first region DIF 1. The second area DIF2 has a first end and a second end in the channel length direction. The second end is the other end of the first end.

The first end of the second region DIF2 is located between the body region BR and the drain region DRA in the channel length direction. The second area DIF2 extends from the first end toward the second end such that the second end reaches the trench TR 3. That is, the second area DIF2 is formed such that the second area DIF2 avoids the lower position of the drain area DRA.

The third region DIF3 is closer to the third surface F3 (buried region BL) than the drift region DRI and the body region BR in the thickness direction of the epitaxial layer EP2, and is disposed farther from the third surface F3 (buried region BL) than the first region DIF 1. The third area DIF3 has a first end and a second end in the channel length direction. The second end is the other end of the first end.

The first end of the third region DIF3 is located between the body region BR and the drain region DRA in the channel length direction. The third area DIF3 extends from the first end toward the second end such that the second end reaches the trench TR 3. That is, the third region DIF3 is formed such that the third region DIF3 avoids the lower portion of the drain region DRA.

As shown in fig. 4 to 6, the first area DIF1 may not be formed to pass through the area where the transistor Tr is formed. More specifically, the first area DIF1 may be formed at least under the drain area DRA.

As shown in fig. 5 and 6, the second area DIF2 may not extend so that the second end reaches the trench TR 3. More specifically, the second region DIF2 may extend from the first end such that the second end extends at least below the source region SR. From another perspective, the second region DIF2 may be formed at least under the channel region SR and the source region SR.

As shown in fig. 6 and 7, the epitaxial layer EP2 may not include the third region DIF 3.

In the above description, the number of fingers of the transistor Tr (LDMOS transistor) is 1, but as shown in fig. 8, the number of fingers of the transistor Tr may be 2 or more. When the number of fingers of the transistor Tr is plural, the third region DIF3 (in fig. 8, the third region DIF3 channel at the center) which is not arranged adjacent to the trench Tr3 may have both ends between the body region BR and the drain region DRA, respectively.

As shown in fig. 9, the method of manufacturing a semiconductor device according to the first embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a third ion implantation step S4, a fourth ion implantation step S5, a fifth ion implantation step S6, a first insulating spacer film forming step S7, a gate dielectric film forming step S8, and a gate electrode forming step S9. The method of manufacturing a semiconductor device according to the first embodiment further includes a sixth ion implantation step S10, a sidewall spacer formation step S11, a seventh ion implantation step S12, an interlayer insulating film formation step S13, a second insulating spacer film formation step S14, a contact plug formation step S15, and a wiring formation step S16.

As shown in fig. 10, in a semiconductor substrate providing step S1, a semiconductor substrate SUB is provided. In the semiconductor substrate providing step S1, first, a semiconductor substrate including an epitaxial layer EP1 is provided. Next, in the semiconductor substrate providing step S1, ion implantation of the second surface F2 is performed. As a result, the buried region BL is formed. Third, in the semiconductor substrate providing step S1, epitaxial growth of an epitaxial layer EP2 is performed on the epitaxial layer EP 1. As described above, the semiconductor substrate SUB including the epitaxial layer EP1, the epitaxial layer EP2, and the buried region BL is provided. In addition, the buried region BL is finally formed through the epitaxial layer EP1 and the epitaxial layer EP2 by diffusing impurities associated with the heat treatment for forming the epitaxial layer EP2 (and the heat treatment in the subsequent step).

As shown in fig. 11, in the first ion implantation step S2, ion implantation for forming the second area DIF2 is performed. As shown in fig. 12, in the second ion implantation step S3, ion implantation for forming the first area DIF1 is performed. As shown in fig. 13, in the third ion implantation step S4, ion implantation for forming the third region DIF3 is performed.

As shown in fig. 14, in the fourth ion implantation step S5, ion implantation for forming the body region BR is performed. As shown in fig. 15, in the fifth ion implantation step S6, ion implantation for forming the drift region DRI is performed. For example, the first to fifth ion implantation steps S2 to S6 are performed using a photoresist as a mask.

As shown in fig. 16, in the first insulating isolation film forming step S7, an insulating isolation film ISL1 and an insulating isolation film ISL2 are formed. In the first insulating isolation film forming step S7, the trench TR1 and the trench TR2 are first formed. The trench TR1 and the trench TR2 are formed by anisotropic dry etching, such as Reactive Ion Etching (RIE).

Next, in the first insulating isolation film forming step S7, the materials constituting the insulating isolation film ISL1 and the insulating isolation film ISL2 are embedded in the trench TR1 and the trench TR 2. The insulating isolation film ISL1 and a material constituting the insulating isolation film ISL2 are buried in the trench TR1 and the trench TR2 by, for example, Chemical Vapor Deposition (CVD) or the like. Third, in the first insulating isolation film forming step S7, the materials constituting the insulating isolation films ISL1 and ISL2 protruding from the trenches TR1 and TR2 are removed by Chemical Mechanical Polishing (CMP) or the like.

As shown in fig. 17, in the gate dielectric film forming step S8, the gate dielectric film GI is formed. The gate dielectric film forming step S8 is performed by, for example, thermally oxidizing the fourth surface F4 of the epitaxial layer EP 2.

As shown in fig. 18, in the gate electrode forming step S9, the gate electrode GE is formed. In the gate electrode forming step S9, first, the material constituting the gate electrode GE is deposited by CVD or the like. Next, in the gate electrode forming step S9, the material constituting the formed gate electrode GE is patterned by anisotropic dry etching using a photoresist formed by photolithography.

As shown in fig. 19, in the sixth ion implantation step S10, a first portion SRa is formed. The sixth ion implantation step S10 is performed with the gate electrode GE as a mask.

As shown in fig. 20, in the sidewall spacer forming step S11, a sidewall spacer SWS is formed. First, in the sidewall spacer forming step S11, a material constituting the sidewall spacer SWS is deposited by CVD or the like. Next, in the sidewall spacer forming step S11, the material constituting the deposited sidewall spacers SWS is etched back.

As shown in fig. 21, in the seventh ion implantation step S12, a source region SR (more specifically, the second portion SRb), a drain region DRA, and a body contact region BCR are formed. The seventh ion implantation step S12 is performed using the gate electrode GE, the sidewall spacer SWS, and the photoresist as masks.

As shown in fig. 22, in the interlayer insulating film forming step S13, an interlayer insulating film ILD is formed. In the interlayer insulating film forming step S13, first, a material constituting the interlayer insulating film ILD is deposited by CVD or the like. Next, in the interlayer insulating film forming step S13, a material constituting the interlayer insulating film ILD formed by CMP or the like is planarized.

As shown in fig. 23, in the second insulating isolation film forming step S14, an insulating isolation film ISL3 is formed. In the second insulating isolation film forming step S14, the trench TR3 is first formed. The trench TR3 is formed by anisotropic dry etching. Next, in the second insulating isolation film forming step S14, the material constituting the insulating isolation film ISL3 is embedded in the trench TR3 by CVD or the like. Third, in the second insulating isolation film forming step S14, the material constituting the insulating isolation film ISL3 protruding from the trench TR3 is removed by CMP or the like.

As shown in fig. 24, in the contact plug forming step S15, contact plugs CP1, CP2, and CP3 are formed. In the contact plug forming step S15, first, a contact hole is formed in the interlayer insulating film ILD. For example, the contact hole is formed by anisotropic dry etching. Next, in the contact plug forming step S15, the materials constituting the contact plugs CP1, CP2, and CP3 are buried in the contact holes by CVD or the like. Third, in the contact plug forming step S15, the materials constituting the contact plugs CP1, CP2, and CP3 protruding from the contact holes are removed by CMP or the like.

In the wiring forming step S16, formation of the wiring WL1 and the wiring WL2 is performed. In the wiring forming step S16, first, materials constituting the wiring WL1 and the wiring WL2 are deposited by sputtering or the like. Next, in the wiring forming step S16, the materials constituting the deposition wiring WL1 and the wiring WL2 were patterned by anisotropic dry etching using a photoresist formed by photolithography. As described above, the semiconductor device according to the first embodiment shown in fig. 3 is formed.

As described above, in the semiconductor device according to the first embodiment, the first region DIF1 is formed at least below the drain region DRA, and the impurity concentration of the first region DIF1 is small. Therefore, when a positive potential is applied to the drain region DRA, punchthrough is likely to occur between the drift region DRI and the buried region BL. When the gap between the drift region DRI and the buried region BL is pierced, the potential applied to the drain region DRA is shared by the drain region DRA, the drift region DRI, and the buried region BL, and therefore, the semiconductor device according to the first embodiment can improve the off-state withstand voltage.

In the semiconductor device according to the first embodiment, the potential applied to the drain region DRA by the punch-through between the drift region DRI and the buried region BL is also shared by the buried region BL, and as a result, the potential of the buried region BL tends to rise. When the potential of the buried region BL is raised, the depletion layer tends to extend from the buried region BL to the body region BR, and the potential of the body region BR tends to be raised.

The semiconductor device according to the first embodiment comprises a parasitic npn transistor having a drain region DRA as collector, a body region BR as base and a source region SR as emitter. Therefore, if the potential of the body region BR is raised, the parasitic npn transistor operates and the on-state breakdown voltage may be lowered.

However, as described above, the semiconductor device according to the first embodiment includes the second region DIF2 extending such that the second terminal DIF2b reaches at least below the source region SR. Since the second region DIF2 has a high impurity concentration and is arranged close to the buried region BL, even if the potential of the buried region BL is raised, it is difficult for the depletion layer to extend from the buried region BL to the body region BR. That is, in the semiconductor device according to the first embodiment, the potential of the body region BR hardly rises, and the decrease in the on-state breakdown voltage is suppressed.

Fig. 25 shows the result of simulation performed by the process cad (TCAD) when the second area DIF2 is formed, and fig. 26 shows the result of simulation performed by the TCAD when the second area DIF2 is not formed. In fig. 25 and 26, equipotential lines are indicated by dashed lines at 2V intervals. In these simulations, the potential applied to the drain region DRA was set to 70v, and the potential applied to the gate electrode GE was set to 4 v.

As shown in fig. 25 and 26, when the second region DIF2 is not formed, the potential of the body region BR is raised by the potential of the buried region BL, and when the second region DIF2 is formed, the rise in the potential of the body region BR due to the potential of the buried region BL is suppressed.

Since the first end of the second region DIF2 is disposed between the body region BR and the drain region DRA in the channel length direction (i.e., formed to avoid the lower portion of the drain region DRA), when a positive potential is applied to the drain region DRA, the off-state breakdown voltage can be maintained without preventing punch-through between the drift region DRI and the buried region BL.

In the semiconductor device according to the first embodiment, since the first region DIF1 is formed at least below the drain region DRA, it is difficult to punch through between the drift region and the buried region BL when a negative potential is applied to the drain region DRA. Therefore, according to the semiconductor device of the first embodiment, the negative input breakdown voltage can be improved.

The semiconductor device according to the first embodiment further includes a parasitic npn transistor including a buried region BL as a collector, a body region BR as a base, and a source region SR as an emitter. In the semiconductor device according to the first embodiment, since the parasitic npn transistor hardly operates by suppressing the potential rise of the body region BR, substrate implantation is hardly caused, and a leakage current when the body diode is intentionally operated can be reduced.

In the semiconductor device according to the first embodiment, the drift region DRI is easily depleted even if the impurity concentration of the drift region DRI increases or even if the impurity concentration of the drift region DRI increases due to the reduced surface field (RESURF) effect of the third region DIF 3. That is, in the semiconductor device according to the first embodiment, the on-resistance can be reduced while maintaining the off withstand voltage of the transistor Tr.

The conductivity in the vicinity of the side surface of the trench TR3 is the first conductivity type. It is considered that this is caused by the deposition caused by the etching of the buried region BL adhering to the side surface of the trench TR3 when the etching of the buried region BL is performed in the second insulating isolation film forming step S14. In the semiconductor device according to the first embodiment, since the first region DIF1, the second region DIF2, and the third region DIF3 are extended so that the first region DIF1, the second region DIF2, and the third region DIF3 are in contact with the side surface of the trench TR3, a decrease in the negative input breakdown voltage due to punch-through between the drift region DRI and the side surface of the trench TR3 can be suppressed.

In the semiconductor device according to the first embodiment, when substrate injection occurs in a region other than the region where the transistor Tr is formed, electrons are annihilated by recombination in the second region DIF2 at the deepest position, and are also annihilated by recombination in the first region DIF1 and the third region DIF 3. Therefore, in the semiconductor device according to the first embodiment, the influence of the substrate implantation from the region other than the region in which the transistor Tr is formed can be reduced.

In the semiconductor device according to the first embodiment, since the second region DIF2 is in contact with the trench TR3 and is located in the vicinity of the buried region BL, an increase in the potential of the buried region BL located in the vicinity of the trench TR3 can be suppressed. As a result, according to the semiconductor device of the first embodiment, the reliability of the insulating isolation film ISL3 can be improved.

(second embodiment)

Hereinafter, a semiconductor device according to a second embodiment will be described. Here, differences from the semiconductor device according to the first embodiment will be mainly described, and the description will not be repeated.

(configuration of semiconductor device according to second embodiment)

The semiconductor device according to the second embodiment includes: semiconductor substrate SUB, insulating isolation films ISL1 and ISL2, gate dielectric film GI, gate electrode GE, sidewall spacer SWS, interlayer insulating film ILD, insulating isolation films ISL3, contact plug CP1, contact plug CP2, contact plug CP3, wiring WL1, and wiring WL 2. The semiconductor substrate SUB includes an epitaxial layer EP1, an epitaxial layer EP2, and a buried region BL.

Epitaxial layer EP2 includes drain region DRA, source region SR, drift region DRI, body region BR, body contact region BCR, first region DIF1, second region DIF2 and third region DIF 3. In these respects, the semiconductor device according to the second embodiment is similar in configuration to the semiconductor device according to the first embodiment.

However, in the semiconductor device according to the second embodiment, as shown in fig. 27, the both end positions of the first region DIF1 in the channel length direction are formed to coincide with the both end positions of the drift region DRI in the channel length direction. In this regard, the configuration of the semiconductor device according to the second embodiment is different from that of the semiconductor device according to the first embodiment.

(method of manufacturing semiconductor device according to second embodiment)

As shown in fig. 28, the method of manufacturing a semiconductor device according to the second embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a third ion implantation step S4, a fourth ion implantation step S5, a first insulating isolation film forming step S7, a gate dielectric film forming step S8, and a gate electrode forming step S9. The method of manufacturing a semiconductor device according to the second embodiment further includes a sixth ion implantation step S10, a sidewall spacer formation step S11, a seventh ion implantation step S12, an interlayer insulating film formation step S13, a second insulating spacer film formation step S14, a contact plug formation step S15, and a wiring formation step S16. In these respects, the method of manufacturing a semiconductor device according to the second embodiment is different from the method of manufacturing a semiconductor device according to the first embodiment.

However, the method of manufacturing a semiconductor device according to the second embodiment is different from the method of manufacturing a semiconductor device according to the first embodiment in that the method of manufacturing a semiconductor device according to the second embodiment does not include the fifth ion implantation step S6. In the semiconductor device according to the second embodiment, since both end positions of the first region DIF1 in the channel length direction coincide with both end positions of the drift region DRI in the channel length direction, the first region DIF1 and the drift region DRI can be formed using the same mask by changing the type of ions to be implanted and the implantation depth in the second ion implantation step S3.

(Effect of the semiconductor device according to the second embodiment)

In the semiconductor device according to the second embodiment, since the first region DIF1 and the drift region DRI can be formed by ion implantation using the same mask, the manufacturing process can be simplified.

(third embodiment)

Hereinafter, a semiconductor device according to a third embodiment will be described. Here, differences from the semiconductor device according to the first embodiment will be mainly described, and the description will not be repeated.

(configuration of semiconductor device according to third embodiment)

The semiconductor device according to the third embodiment includes: a semiconductor substrate SUB; an insulating isolation film ISL1 and an insulating isolation film ISL 2; a gate dielectric film GI; a gate electrode GE; a sidewall spacer SWS; an interlayer insulating film ILD; an insulating isolation film ISL 3; contact plug CP 1; contact plug CP 2; a contact plug CP3, a wiring WL1, and a wiring WL 2. The semiconductor substrate SUB has an epitaxial layer EP1 and an epitaxial layer EP2 in the semiconductor substrate SUB. The epitaxial layer EP1 has a buried region BL.

Epitaxial layer EP2 includes drain region DRA, source region SR, drift region DRI, body region BR, body contact region BCR, first region DIF1, second region DIF2 and third region DIF 3. In these respects, the semiconductor device according to the third embodiment is similar in configuration to the semiconductor device according to the first embodiment.

However, in the semiconductor device according to the third embodiment, as shown in fig. 29, both end positions of the second region DIF2 in the channel length direction are formed to coincide with both end positions of the third region DIF3 in the channel length direction. In this regard, the configuration of the semiconductor device according to the third embodiment is different from that of the semiconductor device according to the first embodiment.

(method of manufacturing semiconductor device according to third embodiment)

As shown in fig. 30, the method of manufacturing a semiconductor device according to the third embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a fourth ion implantation step S5, a fifth ion implantation step S6, a first insulating isolation film forming step S7, a gate dielectric film forming step S8, and a gate electrode forming step S9. The method of manufacturing a semiconductor device according to the third embodiment further includes a sixth ion implantation step S10, a sidewall spacer formation step S11, a seventh ion implantation step S12, an interlayer insulating film formation step S13, a second insulating spacer film formation step S14, a contact plug formation step S15, and a wiring formation step S16. In these respects, the method of manufacturing a semiconductor device according to the third embodiment is different from the method of manufacturing a semiconductor device according to the first embodiment.

However, the method of manufacturing a semiconductor device according to the third embodiment is different from the method of manufacturing a semiconductor device according to the first embodiment in that the method of manufacturing a semiconductor device according to the third embodiment does not include the third ion implantation step S4. In the semiconductor device according to the third embodiment, since both end positions of the second region DIF2 in the channel length direction coincide with both end positions of the third region DIF3 in the channel length direction, the second region DIF2 and the third region are formed using the same mask by changing the implantation depth in the first ion implantation step S2.

(Effect of the semiconductor device according to the third embodiment)

In the semiconductor device according to the third embodiment, the second region DIF2 and the third region DIF3 can be formed by ion implantation using the same mask, and the manufacturing process can be simplified.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, but various modifications can be made without departing from the gist thereof.