阅读说明：本技术 三维体声波谐振器及其制造方法 (Three-dimensional bulk acoustic wave resonator and method of manufacturing the same ) 是由 吴明 唐兆云 杨清华 赖志国 王家友 于 2020-04-20 设计创作，主要内容包括：本发明公开了一种三维(3D)体声波(BAW)谐振器,包括：压电膜阵列,包括在衬底与盖帽层之间垂直且水平分布的多个压电膜,垂直方向上相邻压电膜之间具有多个第一空腔,水平的第一方向上相邻压电膜之间具有共用的第二空腔,水平的第二方向上相邻压电膜之间具有共用的第三空腔；多个电极层,至少覆盖每个第一空腔的顶面和底面；电极互连层,沿第三空腔侧面依次连接所述多个电极层。依照本发明的3D BAW谐振器及其制造方法,采用CMOS兼容工艺制造了其中多个空腔包围压电膜的立体谐振器,减小了体积、增加了集成度,降低了成本。(The invention discloses a three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator, comprising: the piezoelectric film array comprises a plurality of piezoelectric films which are vertically and horizontally distributed between a substrate and a cap layer, wherein a plurality of first cavities are formed between adjacent piezoelectric films in the vertical direction, a shared second cavity is formed between adjacent piezoelectric films in the horizontal first direction, and a shared third cavity is formed between adjacent piezoelectric films in the horizontal second direction; a plurality of electrode layers covering at least the top and bottom surfaces of each first cavity; and the electrode interconnection layer is sequentially connected with the plurality of electrode layers along the side surface of the third cavity. According to the 3D BAW resonator and the manufacturing method thereof, the three-dimensional resonator in which the piezoelectric film is surrounded by the plurality of cavities is manufactured by adopting a CMOS compatible process, so that the volume is reduced, the integration level is increased, and the cost is reduced.)

1. A three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator, comprising:

the piezoelectric film array comprises a plurality of piezoelectric films which are vertically and horizontally distributed between a substrate and a cap layer, wherein a plurality of first cavities are formed between adjacent piezoelectric films in the vertical direction, a shared second cavity is formed between adjacent piezoelectric films in the horizontal first direction, and a shared third cavity is formed between adjacent piezoelectric films in the horizontal second direction;

a plurality of electrode layers covering at least the top and bottom surfaces of each first cavity;

and the electrode interconnection layer is sequentially connected with the plurality of electrode layers along the side surface of the third cavity.

2. The 3D BAW resonator of claim 1, wherein the plurality of first cavities increase in width in the second direction from top to bottom, and preferably only one side of any two adjacent first cavities are aligned; optionally, the second cavities are equal in width along the first direction; optionally, the third cavity comprises a plurality of sub-portions of unequal width in the second direction, and preferably any two adjacent sub-portions are of different depth.

3. The 3D BAW resonator of claim 1, wherein each first cavity has an electrode layer, a first isolation layer, and an electrode interconnect layer between the common third cavity; optionally, a second isolation layer and a first hermetic layer are provided between each first cavity and the common second cavity.

4. The 3D BAW resonator of claim 1 or 3, wherein the substrate and/or cap layer material is selected from the group consisting of silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and cap layer materials are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the first sealing layer material is titanium oxide, tantalum oxide, hafnium oxide, tungsten oxide.

5. The 3D BAW resonator of claim 1, wherein the cap layer has a driving transistor therein, electrically connected to the electrode interconnection layer through a rewiring layer in the interlayer insulating layer, and preferably electrically connected to the conductive bump through a pad in the passivation layer; optionally, the third cavity has a second sealing layer on top, preferably the second sealing layer is silicon nitride.

6. A method of fabricating a three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator, comprising the steps of:

forming a plurality of sacrificial layers and a plurality of piezoelectric layers alternately stacked on a substrate;

forming a cap layer on the sacrificial layer at the top, and forming a hard mask on the cap layer;

sequentially etching the layers until the substrate is exposed to form a plurality of first openings extending along a first direction;

forming a filling layer in each opening;

etching until the substrate is exposed, and forming a plurality of second openings extending along a second direction;

removing the plurality of sacrificial layers through the second openings, leaving a plurality of first cavities between adjacent piezoelectric layers;

forming a plurality of electrode layers at least on the top and bottom surfaces of the first cavity through the second opening;

an electrode interconnection layer sequentially connecting the plurality of electrode layers is formed in the first opening.

7. The method of fabricating a 3D BAW resonator of claim 6, wherein a width of the plurality of first cavities increases from top to bottom along the second direction, and preferably only one side of any two adjacent first cavities is aligned; optionally, the second openings are equal in width along the first direction; optionally, the first opening comprises a plurality of sub-portions of unequal width in the second direction, and preferably any two adjacent sub-portions are of different depth.

8. The 3D BAW resonator manufacturing method of claim 6, wherein an electrode layer, a first isolation layer, and an electrode interconnection layer are formed between each first cavity and the first opening; optionally, a second isolation layer and a first hermetic layer are formed between each first cavity and the second opening.

9. A method of fabricating a 3D BAW resonator as claimed in claim 6 or 8 wherein the substrate and/or capping layer material is selected from the group consisting of bulk Si, silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and capping layer materials are the same; optionally, the sacrificial layer material is a semiconductor material selected from SiGe, SiGeC, SiGeSn, SiGaN, SiGaP, SiGaAs, InSiN, InSiP, InSiAs, inssb, sisalas, or a non-semiconductor material selected from amorphous carbon, graphene oxide; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the first sealing layer material is titanium oxide, tantalum oxide, hafnium oxide, tungsten oxide.

10. The 3D BAW resonator manufacturing method of claim 6, wherein, after forming the electrode interconnection layer, forming the driving transistor in the cap layer, forming an interlayer insulating layer and a rewiring layer over the driving transistor to be electrically connected to the electrode interconnection layer, and preferably forming a passivation layer and a pad over the rewiring layer to be electrically connected to the conductive bump; optionally, a second sealing layer is formed on top of the first opening, preferably the second sealing layer is of silicon nitride.

Technical Field

The present invention relates to a three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator and a method of manufacturing the same, and more particularly, to a CMOS process compatible 3D BAW resonator and a method of manufacturing the same.

Background

In wireless communication, the rf filter is used as an intermediary for filtering signals with specific frequencies, and is used to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in the wireless transceiver. With the deployment of 4GLTE networks and the growth of the market, the design of the radio frequency front end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements on filtering performance. Because the film bulk acoustic resonator (FBAR, also called bulk acoustic wave, or "BAW") has the characteristics of small size, high working frequency, low power consumption, high quality factor (Q value), direct output of frequency signals, compatibility with CMOS process, etc., it has become an important device in the field of radio frequency communication and is widely used at present.

FBAR is a thin film device with a sandwich structure of electrodes-piezoelectric film-electrodes fabricated on a substrate material. The FBAR has a structure of a cavity type, a bragg reflection type (SMR), and a back surface etching type. The Q value of the cavity type FBAR is higher than that of the SMR type FBAR, the loss is small, and the electromechanical coupling coefficient is high; compared with the back etching FBAR, the back etching FBAR does not need to remove a large-area substrate, and has higher mechanical strength. Therefore, the cavity FBAR is the first choice for integration in CMOS devices.

However, due to the complexity of manufacturing, existing BAW filters and Bulk Acoustic Resonators (BARs) are manufactured as independent planar or two-dimensional (2D) layout devices. That is, the BAW filter and the Bulk Acoustic Resonator (BAR) are not provided as structures integrated with other CMOS, bicmos, SiGe HBT and/or passive devices, thereby resulting in higher manufacturing costs and increased manufacturing processes.

In addition, the 2D BAW resonator as an independent device has large volume and area and low integration level, is difficult to be manufactured on the same chip with a driving circuit thereof by adopting a CMOS process, and is further difficult to be integrated with 3D devices such as a FinFET and a NAND memory. If a plurality of 2D BAW resonators are stacked together by using a 3D packaging technology, although the integration level can be effectively improved, each chip needs to use bonding (bonding), grinding (grinding) and Through Silicon Via (TSV) technologies to reduce the packaging height, the process is complicated, extremely high alignment precision is required, and the manufacturing cost is high. In addition, such a 3D package has problems of complicated wiring and large parasitic impedance.

Disclosure of Invention

It is therefore an object of the present invention to provide a 3D BAW resonator and a method of manufacturing the same that overcomes the above technical obstacles.

The present invention provides a three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator comprising:

the piezoelectric film array comprises a plurality of piezoelectric films which are vertically and horizontally distributed between a substrate and a cap layer, wherein a plurality of first cavities are formed between adjacent piezoelectric films in the vertical direction, a shared second cavity is formed between adjacent piezoelectric films in the horizontal first direction, and a shared third cavity is formed between adjacent piezoelectric films in the horizontal second direction;

a plurality of electrode layers covering at least the top and bottom surfaces of each first cavity;

and the electrode interconnection layer is sequentially connected with the plurality of electrode layers along the side surface of the third cavity.

Wherein the width of the plurality of first cavities in the second direction increases from top to bottom, and preferably only one side of any two adjacent first cavities is aligned; optionally, the second cavities are equal in width along the first direction; optionally, the third cavity comprises a plurality of sub-portions of unequal width in the second direction, and preferably any two adjacent sub-portions are of different depth.

Wherein, an electrode layer, a first isolation layer and an electrode interconnection layer are arranged between each first cavity and the shared third cavity; optionally, a second isolation layer and a first hermetic layer are provided between each first cavity and the common second cavity.

Wherein the substrate and/or cap layer material is selected from the group consisting of silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and cap layer material are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the first sealing layer material is titanium oxide, tantalum oxide, hafnium oxide, tungsten oxide.

Wherein the cap layer is provided with a driving transistor therein, is electrically connected to the electrode interconnection layer through a rewiring layer in the interlayer insulating layer and is preferably electrically connected to the conductive bump through a welding pad in the passivation layer; optionally, the third cavity has a second sealing layer on top, preferably the second sealing layer is silicon nitride.

The present invention also provides a method of manufacturing a three-dimensional (3D) Bulk Acoustic Wave (BAW) resonator, comprising the steps of:

forming a plurality of sacrificial layers and a plurality of piezoelectric layers alternately stacked on a substrate;

forming a cap layer on the sacrificial layer at the top, and forming a hard mask on the cap layer;

sequentially etching the layers until the substrate is exposed to form a plurality of first openings extending along a first direction;

forming a filling layer in each opening;

etching until the substrate is exposed, and forming a plurality of second openings extending along a second direction;

removing the plurality of sacrificial layers through the second openings, leaving a plurality of first cavities between adjacent piezoelectric layers;

forming a plurality of electrode layers at least on the top and bottom surfaces of the first cavity through the second opening;

an electrode interconnection layer sequentially connecting the plurality of electrode layers is formed in the first opening.

Wherein the width of the plurality of first cavities in the second direction increases from top to bottom, and preferably only one side of any two adjacent first cavities is aligned; optionally, the second openings are equal in width along the first direction; optionally, the first opening comprises a plurality of sub-portions of unequal width in the second direction, and preferably any two adjacent sub-portions are of different depth.

Wherein an electrode layer, a first isolation layer and an electrode interconnection layer are formed between each first cavity and the first opening; optionally, a second isolation layer and a first hermetic layer are formed between each first cavity and the second opening.

Wherein the substrate and/or cap layer material is selected from the group consisting of silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and cap layer material are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the sacrificial layer material is a semiconductor material selected from SiGe, SiGeC, SiGeSn, SiGaN, SiGaP, SiGaAs, InSiN, InSiP, InSiAs, inssb, sisalas, or a non-semiconductor material selected from amorphous carbon, graphene oxide; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the first sealing layer material is titanium oxide, tantalum oxide, hafnium oxide, tungsten oxide.

Wherein, after the electrode interconnection layer is formed, the driving transistor is formed in the cap layer, an interlayer insulating layer and a rewiring layer are formed over the driving transistor to be electrically connected to the electrode interconnection layer, and a passivation layer and a pad are preferably formed over the rewiring layer to be electrically connected to the conductive bump; optionally, a second sealing layer is formed on top of the first opening, preferably the second sealing layer is of silicon nitride.

According to the 3D BAW resonator and the manufacturing method thereof, the three-dimensional resonator in which the piezoelectric film is surrounded by the plurality of cavities is manufactured by adopting a CMOS compatible process, so that the volume is reduced, the integration level is increased, and the cost is reduced.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

FIG. 1A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, FIG. 1B shows a cross-sectional view taken along line B-B 'of FIG. 1A, and FIG. 1C shows a cross-sectional view taken along line A-A' of FIG. 1A;

fig. 2A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 2B is a cross-sectional view taken along line B-B 'of fig. 2A, and fig. 2C is a cross-sectional view taken along line a-a' of fig. 2A;

fig. 3A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 3B is a cross-sectional view taken along line B-B 'of fig. 3A, and fig. 3C is a cross-sectional view taken along line a-a' of fig. 3A;

fig. 4A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 4B is a cross-sectional view taken along line B-B 'of fig. 4A, and fig. 4C is a cross-sectional view taken along line a-a' of fig. 4A;

fig. 5A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 5B is a sectional view taken along line B-B 'of fig. 5A, and fig. 5C is a sectional view taken along line a-a' of fig. 5A;

fig. 6A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 6B shows a cross-sectional view taken along line B-B 'of fig. 6A, and fig. 6C shows a cross-sectional view taken along line a-a' of fig. 6A;

fig. 7A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 7B shows a cross-sectional view taken along line B-B 'of fig. 7A, and fig. 7C shows a cross-sectional view taken along line a-a' of fig. 7A;

fig. 8A is a plan view illustrating a process of manufacturing a resonator according to an embodiment of the present invention, fig. 8B is a sectional view taken along line B-B 'of fig. 8A, and fig. 8C is a sectional view taken along line a-a' of fig. 8A;

fig. 9A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 9B shows a cross-sectional view taken along line B-B 'of fig. 9A, and fig. 9C shows a cross-sectional view taken along line a-a' of fig. 9A;

fig. 10A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 10B is a sectional view taken along line B-B 'of fig. 10A, and fig. 10C is a sectional view taken along line a-a' of fig. 10A;

fig. 11A is a plan view illustrating a process of manufacturing a resonator according to an embodiment of the present invention, fig. 11B is a sectional view taken along line B-B 'of fig. 11A, and fig. 11C is a sectional view taken along line a-a' of fig. 1A;

fig. 12A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 12B is a sectional view taken along line B-B 'of fig. 12A, and fig. 12C is a sectional view taken along line a-a' of fig. 12A;

fig. 13A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 13B is a sectional view taken along line B-B 'of fig. 13A, and fig. 13C is a sectional view taken along line a-a' of fig. 13A;

fig. 14A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 14B is a sectional view taken along line B-B 'of fig. 14A, and fig. 14C is a sectional view taken along line a-a' of fig. 14A;

fig. 15A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 15B is a sectional view taken along line B-B 'of fig. 15A, and fig. 15C is a sectional view taken along line a-a' of fig. 1A;

fig. 16A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 16B is a sectional view taken along line B-B 'of fig. 16A, and fig. 16C is a sectional view taken along line a-a' of fig. 16A;

fig. 17A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 17B is a sectional view taken along line B-B 'of fig. 17A, and fig. 17C is a sectional view taken along line a-a' of fig. 17A;

fig. 18A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 18B is a sectional view taken along line B-B 'of fig. 18A, and fig. 18C is a sectional view taken along line a-a' of fig. 18A;

fig. 19A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 19B is a sectional view taken along line B-B 'of fig. 19A, and fig. 19C is a sectional view taken along line a-a' of fig. 19A;

fig. 20A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 20B is a sectional view taken along line B-B 'of fig. 20A, and fig. 20C is a sectional view taken along line a-a' of fig. 20A;

fig. 21A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 21B is a sectional view taken along line B-B 'of fig. 21A, and fig. 21C is a sectional view taken along line a-a' of fig. 21A;

fig. 22A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 22B is a sectional view taken along line B-B 'of fig. 22A, and fig. 22C is a sectional view taken along line a-a' of fig. 22A;

fig. 23A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 23B is a sectional view taken along line B-B 'of fig. 23A, and fig. 23C is a sectional view taken along line a-a' of fig. 23A;

fig. 24A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 24B is a sectional view taken along line B-B 'of fig. 24A, and fig. 24C is a sectional view taken along line a-a' of fig. 24A;

FIG. 25 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the invention;

FIG. 26 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the invention;

FIG. 27 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention; and

fig. 28 shows a partial enlarged view of fig. 27.

Detailed Description

The features of the technical solution of the present invention and its technical effects are explained in detail below with reference to the accompanying drawings and in conjunction with exemplary embodiments, disclosing a 3D BAW resonator and a method for manufacturing the same. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.

As shown in fig. 1A to 1C, a stacked structure including at least one sacrificial layer 11A to 11D and at least one piezoelectric layer 12A to 12C alternately stacked in this order from bottom to top is formed on a substrate 10A, wherein the number of sacrificial layers is preferably one more than the number of piezoelectric layers. The substrate 10A may be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS processes and integrated with other digital and analog circuits, a compound semiconductor for MEMS, photoelectric devices, power devices such as GaN, GaAs, SiC, InP, GaP, etc., and a transparent insulating material for display panels such as glass, plastic, sapphire, etc. In a preferred embodiment of the present invention, the substrate 10A is a single crystal such as bulk Si to facilitate epitaxial growth of the stacked structure above.

At least one sacrificial layer 11A-11D (the number is not limited to four, but is any positive integer greater than or equal to 2) and at least one piezoelectric layer 12A-12C (the number is not limited to three, but is any positive integer greater than or equal to 1) alternately stacked are epitaxially grown on the substrate 10A in sequence by a conventional process such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, or the like. The sacrificial layer material may be a semiconductor material such as SiGe, SiGeC, SiGeSn, SiGaN, SiGaP, siggaas, InSiN, InSiP, InSiAs, InSiSb, and ingaas, or a non-semiconductor material such as amorphous carbon or (oxidized) graphene. Piezoelectric layer materials are ceramic materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and the like. Preferably, the number of sacrificial layers is one more than the number of piezoelectric layers. It is further preferable that the stacked structure further includes a cap layer 10B formed on the top sacrificial layer 11D, and the material of the cap layer is preferably the same as that of the substrate 10A, so as to serve as an upper cover plate of the topmost resonant cavity in the subsequent process.

As shown in fig. 2A-2C, a hard mask layer 13 is formed on top of the stacked structure to protect the stacked structure, and in particular, the cap layer 10B on top of the stacked structure, in subsequent processes. The hard mask layer 13 is deposited by LPCVD, PECVD, HDPCVD, etc., and is made of SiN, SiON, SiNC, SiNF, etc.

As shown in fig. 3A-3C, a photoresist pattern 14 is formed on top of the hard mask layer 13. The photoresist coating layer is formed by spin coating, spray coating, screen printing, etc., and is exposed and developed to form photoresist patterns 14, wherein the photoresist patterns extend along a first direction, i.e., a-a ', while leaving openings extending along the first direction between adjacent photoresist patterns (a second direction, i.e., B-B') to expose the hard mask layer 13.

As shown in fig. 4A-4C, the photoresist pattern 14 is used as a mask to sequentially etch the stack of the hard mask layer 13, the cap layer 10B, the sacrificial layer 11 and the piezoelectric film 12, stopping on the substrate 10A, and forming a plurality of openings vertically penetrating through the above layers until the substrate 10A is exposed. As shown, each opening is stepped in cross-section with at least three sub-portions, e.g., 14A, 14B, 14C, the opening sub-portions decreasing in width from top to bottom. Each sub-portion exposes the sacrificial layer 11 or the substrate 10A and does not expose the piezoelectric layer 12. In particular, the depth of the respective sub-portions of adjacent openings varies to expose different sacrificial layers. For example, the depth of the first sub-portion 14A 'of the central opening of fig. 4B is smaller to expose the sacrificial layer 11D, the depth of the first sub-portion 14A of the left and right openings is larger to expose the sacrificial layer 11C, the central second sub-portion 14B' exposes the sacrificial layer 11B, and the left and right second sub-portions 14B expose the sacrificial layer 11A. The etching process is preferably an anisotropic dry etching process, such as plasma dry etching or reactive ion etching using a fluorocarbon based etching gas.

As shown in fig. 5A-5C, the photoresist pattern 14 is removed. Preferably, a wet process is used to remove the organic photoresist with acid and/or an oxidizing agent. Leaving a plurality of first openings 14 distributed along a first direction.

As shown in fig. 6A-6C, an isolation layer 15 is formed over the entire device. The isolation layer 15 is preferably formed by a deposition process with good conformality, such as HDPCVD, MBE, ALD, etc., and is made of an insulating dielectric material different from the hard mask 13, such as SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG. The isolation layer 15 uniformly covers the first opening 14 and the top of the hard mask 13, and particularly covers the sidewalls of the sacrificial layer 11 and the piezoelectric layer 12 exposed in the first opening 14. The isolation layer 15 will subsequently act as an insulating isolation material between the individual sub-resonators of the 3D BAW.

As shown in fig. 7A-7C, the etch removes the horizontal portions of the spacers 15 while leaving only the vertical portions. The horizontal portions of the isolation layer 15 remaining on the sacrificial layers 11A, 11B, 11C, 11D, etc. are removed, while only the vertical portions remaining on the sidewalls of the stack of sacrificial layers and piezoelectric layers are removed, using an anisotropic dry etching process, such as plasma dry etching or reactive ion etching using a fluorocarbon-based etching gas. These vertical portions will eventually serve as insulating isolation films between adjacent resonator electrodes.

As shown in fig. 8A-8C, a filling layer 16 is formed in the first opening 14 and on the isolation layer 15. The filling layer is formed by LPCVD, PECVD, MOCVD, or the like, and the material of the filling layer is preferably different from that of the adjacent isolation layer 15 and hard mask layer 13, such as SiN, SiON, SiNC, SiNF, or the like, to improve the etching selectivity. The filler layer 16 serves to temporarily protect the sidewalls of the stack structure from lateral corrosion in later processes, while serving as a support structure during subsequent removal of the sacrificial layer. Preferably, the deposition process parameters of the fill layer 16, such as plasma generation power, temperature, pressure, etc., in the vacuum chamber are controlled such that the fill layer 16 has sufficient hardness to provide sufficient mechanical support capability. The filling layer 16 has a cross-sectional structure conformal to the first opening 14 (including a plurality of sub-portions, such as 14A, 14B, 14C, 14A ', 14B ', 14C ', etc.), that is, at least three sub-portions (not shown) with different widths are included and the sub-portions of the filling layer 16 in adjacent first openings 14 have different depths, thereby forming a stepped structure with gradually decreasing width downward as shown in the figure.

As shown in fig. 9A to 9C, the filling layer 16 is planarized by CMP or etch back until the hard mask layer 13 is exposed. At this time, the hard mask layer 13 has a plurality of elongated shapes extending in the first direction a-a', and a plurality of filling layer 16 patterns also extending in the first direction are interposed between adjacent hard mask layer patterns.

As shown in fig. 10A to 10C, a photoresist pattern 17 extending in a second direction (B-B' direction) is formed on the exposed hard mask layer 13 using a common paste coating, exposure, and development process. As shown in the drawing, the hard mask layer 13 patterns and the filling layer 16 patterns alternately arranged in the second direction B-B' are exposed between the adjacent photoresist patterns 17.

As shown in fig. 11A to 11C, with the photoresist pattern 17 as a mask, anisotropic dry etching is performed to sequentially etch down the stack of the hard mask layer 13/the filling layer 16, the cap layer 10B, the sacrificial layer 11 and the piezoelectric layer 12 to the substrate 10A, forming a second opening 17A exposing the top surface of the substrate 10A and the sidewalls of the above layers. The etching process is, for example, plasma dry etching or reactive ion etching using a fluorocarbon-based etching gas, and further, it is preferable to select a gas having a relatively large fluorocarbon ratio such as CFH₃、C₂F₃H₃、CF₂H₂And the like, so that during the etching process, C and elements such as Si, N and the like form a temporary protective layer on the side wall to inhibit lateral corrosion and ensure that the side wall of the second opening 17A has enough verticality.

As shown in fig. 12A to 12C, the photoresist pattern 17 is removed to re-expose the hard mask pattern 13 and the filling layer pattern 16. At this time, the regions not covered by the photoresist pattern 17 are etched until the substrate 10A is exposed, thereby leaving the rectangular hard mask patterns 13 and the rectangular filling layer patterns 16 alternately arranged in the second direction B-B' in the regions covered by the photoresist pattern 17. In other words, the sidewall of the filling layer pattern 16 in fig. 12B in the direction perpendicular to the paper surface is exposed in the second opening 17A in fig. 12C.

As shown in FIGS. 13A to 13C, all the sacrificial layers 11(11A to 11D, etc.) are completely removed by isotropic etching, leaving a plurality of piezoelectric layers supported by the filling layer pattern 16 on the substrateThe layer patterns 12(12A to 12C, etc.) have recesses 13A in the horizontal direction between the adjacent piezoelectric layer patterns in addition to the second openings 17A in the vertical direction. In a preferred embodiment of the present invention, the substrate 10A and the cap layer 10B are Si, the sacrificial layer 11 is SiGe, and wet etching is performed, and the etching solution is a combination of a strong oxidant, a strong inorganic acid and a weak organic acid to increase the etching selectivity of SiGe to Si. Wherein the strong oxidant is nitric acid, hydrogen peroxide, ozone and perchloric acid, the strong inorganic acid is hydrofluoric acid, hydrochloric acid and sulfuric acid, and the weak organic acid is acetic acid and oxalic acid, for example, the strong oxidant is 30-50 parts, the strong inorganic acid is 0.5-2 parts, the weak organic acid is 1-4 parts, and the solvent water is 40-70 parts (volume ratio). For example, for single crystal Si_0.8Ge_0.2And Si, 40:1:2:57 HNO may be used₃(70％):HF(49％):CH₃COOH(99.9％):H₂O, thereby achieving a 300:1 selection ratio. In another embodiment of the present invention, the sacrificial layer is a C-based material such as amorphous carbon (e.g. ta-C), graphene oxide, graphene, etc., and oxygen plasma dry etching or thermal oxidation may be selected so that the sacrificial layer reacts with oxygen to form a gas to be pumped out, at which time oxygen will form a thin oxide layer on the surface of the piezoelectric layer, and the thin oxide layer needs to be removed by using an etchant such as dHF, dBOE, etc.

As shown in fig. 14A-14C, a metal layer 18 is formed over the entire device using a well-conformal deposition process such as ALD, MBE, MOCVD, etc., to serve as a contact electrode for the piezoelectric layer 12. The material of the metal layer 18 includes, for example, a metal simple substance or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, etc., or a conductive oxide or a conductive nitride of these metals, or any combination of the above materials, that is, a seed layer or a barrier layer and a conductive layer. As shown in fig. 13C, in the cross-sectional view, the metal layer 18 not only surrounds the piezoelectric layer 12 (at least three sides, preferably four sides), but is also deposited on the substrate 10A, the cap layer 10B to serve as a contact layer for the bottom and top surfaces.

As shown in fig. 15A-15C, a plurality of photoresist patterns 19 extending along the second direction B-B' are formed, exposing the substrate 10A, i.e., leaving the second opening 17A, while covering only the hard mask layer 13 pattern and the fill layer 16 pattern. Then, with this photoresist pattern 19 as a mask, anisotropic dry etching is performed to remove the metal layer 18 of the side wall of the piezoelectric layer 12 through the second opening 17A, leaving a pattern of the metal layer 18 only on the top and bottom surfaces of the piezoelectric layer 12 and the top surface of the substrate 10A and the bottom surface of the cap layer 10B to serve as the top and bottom electrodes of the piezoelectric layer of the future resonator. The etching process is preferably anisotropic plasma dry etching, RIE.

As shown in fig. 16A to 16C, the photoresist pattern 19 is removed. Oxygen plasma dry ashing or acid etching liquid wet etching is preferred. Preferably, wet etching solutions such as dHF, dBOE, hot phosphoric acid, etc. are used to clean the exposed surfaces of the second opening 17A and the recess 13A, so as to remove the residual reaction deposits in the previous process and ensure the film growth quality in the subsequent process.

As shown in fig. 17A-17C, a second isolation layer 20 is deposited over the entire surface. The second isolation layer 20 is preferably formed by a deposition process with good conformality such as HDPCVD, MBE, ALD, etc., and the material of the second isolation layer is preferably the same as that of the isolation layer 15, such as SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG. As shown in fig. 17C, the second isolation layer 20 fills the bottom surface and the sidewall of the second opening 17A.

As shown in fig. 18A to 18C, the second isolation layer 20 is processed by a planarization process such as CMP, etch back, etc., until the hard mask layer 13 is exposed. Thus, the filling layer 16 is covered by the second spacer 20 along the first direction A-A 'sidewalls and by the (first) spacer 15 along the second direction B-B' sidewalls.

As shown in fig. 19A to 19C, a second opening sealing layer 21 is formed over the entire device, partially filling the second opening 17A. Using PVD, sputtering, evaporation, etc., an oxide such as titanium oxide, tantalum oxide, hafnium oxide, tungsten oxide, etc., is deposited not only covering the top of the hard mask layer 13, but further closing prematurely at the top due to step coverage effected by the top corners of the second opening 17A, so that the top, bottom and sidewalls of the second opening 17A are partially filled, leaving only a narrowed cavity 17A' that will serve as a resonant cavity for the sides of the future resonator.

As shown in fig. 20A to 20C, the seal layer 21 is planarized by CMP or etch back until the hard mask layer 13 is exposed.

As shown in fig. 21A-21C, the fill layer 16 is removed. The SiNx is removed by wet etching, such as hot phosphoric acid based etching, and the plurality of first openings 14 are re-exposed until the substrate 10A is exposed. At this time, the conductive layer 18 around the lateral recess 13A is exposed at each step of the stepped opening sub-portion to be subsequently in direct contact with the electrode interconnection layer to achieve vertical interconnection.

As shown in fig. 22A to 22C, an electrode interconnect layer 22 for vertically connecting a plurality of piezoelectric layer top electrodes is formed in the first opening 14 by a process with good conformality such as ALD. For example, the top electrode 18 of the piezoelectric layer 12B on the left side of fig. 22B is exposed in the second sub-portion 14B of the first opening 14 and electrically connected in contact with the electrode interconnect layer 22, whereby a drive signal can be transmitted to the top of the piezoelectric layer 12B. The electrode interconnection layer 22 is made of a simple metal or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, or any combination of these materials.

As shown in fig. 23A-23C, an opening sealing layer 23, such as SiNx material, is formed by a general conformal process such as LPCVD, PECVD, etc., and partially fills the top of the first opening 14, and the remaining portion of the first opening 14 will be used as a resonant cavity on the sidewall of the piezoelectric layer 12.

As shown in fig. 24A to 24C, the opening sealing layer 23 is planarized by CMP or etching back until the cap layer 10B is exposed. At this time, referring to the details of fig. 28, there is an array of a plurality of vertically distributed piezoelectric layer patterns 12 on the substrate 10A, the adjacent piezoelectric layers 12 sandwich the cavity 13A in the vertical direction, sandwich the cavity 17A ' in the horizontal first direction a-a ' and sandwich the cavity 14 in the horizontal second direction B-B ', and the cavity 14 has a step-like cross section and gradually decreases in width from top to bottom. The piezoelectric layer 12 and the cavity 13A have a metal layer 18 therebetween for upper and lower plates, the metal layer 18 of the vertically adjacent cavity 13A is electrically insulated by a segmented isolation layer 15, and an electrode interconnect layer 22 covers the side wall of the isolation layer 15 and a portion of the top of the metal layer 18 to electrically connect the respective plates of the resonator in turn.

As shown in fig. 25, a driving transistor, for example, including a source region S, a drain region D, and a gate stack G, is formed in the cap layer 10B using a CMOS process.

As shown in fig. 26, a re-wiring layer (RDL)24 and an interlayer Insulating Layer (ILD)25 are formed for inputting signals to the driving transistors.

As shown in fig. 27, a pad 27 and a passivation/solder resist layer 26 are formed. The bonding pad is made of a metal simple substance or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals. Passivation/solder mask layers such as silicon oxide, silicon nitride, silicon oxynitride, low k materials, organic encapsulation films, etc. The pads 27 are partially exposed beyond the layer 26 to form conductive bumps, such as solder balls or Cu pillars, thereon, which can reduce the overall resonator stack package height and improve device integration.

According to the 3D BAW resonator and the manufacturing method thereof, the three-dimensional resonator in which the piezoelectric film is surrounded by the plurality of cavities is manufactured by adopting a CMOS compatible process, so that the volume is reduced, the integration level is increased, and the cost is reduced.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.