阅读说明：本技术 信号处理方法和装置 (Signal processing method and device ) 是由 王昕宇 于 2020-06-08 设计创作，主要内容包括：本发明实施例基于数字信号产生的干扰噪声和输入信号特征强相关的特点,提出了一种在源头上把数字信号的干扰噪声降下来的方法和装置,从而把和输入信号特征强相关的干扰噪声变成弱相关,进而随机化干扰噪声,降低数字模块对芯片内其它模块的干扰。在该方法中,对数字信号进行位处理,通过位处理来随机化干扰噪声,随机化的干扰噪声对SOC芯片内的敏感模块的干扰基本上可以忽略,进而提升了SOC芯片的整体性能指标。(The embodiment of the invention provides a method and a device for reducing the interference noise of a digital signal at the source based on the characteristic that the interference noise generated by the digital signal is strongly correlated with the characteristics of an input signal, so that the interference noise strongly correlated with the characteristics of the input signal is changed into weak correlation, the interference noise is further randomized, and the interference of a digital module on other modules in a chip is reduced. In the method, the digital signal is subjected to bit processing, interference noise is randomized through the bit processing, the interference of the randomized interference noise on a sensitive module in the SOC chip can be basically ignored, and further the overall performance index of the SOC chip is improved.)

1. A signal processing apparatus, characterized by comprising:

the digital signal module is used for outputting an original digital signal;

and the bit processing module is used for receiving the original digital signal output by the digital signal module, and outputting the original digital signal after performing bit processing on the original digital signal.

2. The apparatus of claim 1, the bit processing comprising exclusive or processing or exclusive nor processing.

3. The apparatus of claim 1 or 2, wherein the raw digital signal comprises an N +1 bit raw digital output code, and wherein the bit processing module is configured to:

performing bit processing on an N-bit digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code, wherein the N-bit digital output code is a digital output code except the ith-bit digital output code in the N + 1-bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on an N +1-i bit digital output code by using an i-th bit digital output code in the N +1 bit original digital output code, wherein the N +1-i bit digital output code is a digital output code after the i-th bit digital output code in the N +1 bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on each bit of the N + 1-bit original digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code;

wherein i and N are positive integers, and i < N.

4. The apparatus of claim 3, wherein the ith digital output code is randomly flipped by thermal noise.

5. The apparatus of claim 3 or 4, wherein the i-th bit digital output code is a lowest-order digital output code of the N + 1-bit original digital output codes.

6. The apparatus of any of claims 1-5, further comprising:

and the digital processing output module is used for receiving the digital signals which are output by the bit processing module and are subjected to bit processing and carrying out parallel-to-serial processing on the digital signals.

7. The apparatus of any of claims 1-6, wherein the digital signal module is an analog-to-digital converter (ADC) analog module configured to quantize an analog input signal to generate the original digital signal.

8. A signal processing method, comprising:

receiving an original digital signal;

and carrying out bit processing on the original digital signal and then outputting the processed signal.

9. The method of claim 8, wherein bit processing the raw digital signal comprises:

and carrying out exclusive-OR processing or exclusive-OR processing on the original digital signals.

10. The method of claim 8 or 9, wherein the raw digital signal comprises an N +1 bit raw digital output code, and wherein bit processing the raw digital signal comprises:

performing bit processing on an N-bit digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code, wherein the N-bit digital output code is a digital output code except the ith-bit digital output code in the N + 1-bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on an N +1-i bit digital output code by using an i-th bit digital output code in the N +1 bit original digital output code, wherein the N +1-i bit digital output code is a digital output code after the i-th bit digital output code in the N +1 bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on each bit of the N + 1-bit original digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code;

wherein i and N are positive integers, and i < N.

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a signal processing method and apparatus.

Background

With the progress of semiconductor technology, the integration level of a single chip is higher and higher, and the functions that can be realized are more and more powerful, so that the system-on-chip has been rapidly developed. A System on Chip (SoC) is a System-level Chip that is rapidly developed under such a trend. The SoC chip can integrate a complete system and combine embedded software to achieve a special purpose, so the SoC chip is also an integrated circuit with a special purpose.

The SoC chip may include various modules, such as a core module including a microprocessor or a Central Processing Unit (CPU), a Digital Signal Processing (DSP) module, an embedded memory module, an interface module for communicating with the outside, an analog front end module including an Analog Digital Converter (ADC)/digital-to-analog converter (DAC), a power supply and power consumption management module, and the like. The wireless SoC chip can also comprise a radio frequency front-end module and the like.

Therefore, the SoC chip has a complex circuit structure, mutual interference between modules is a common phenomenon in the SoC chip, and particularly, interference of a module with high noise to a sensitive module often causes deterioration of the overall performance index of the SoC chip. For example, the digital module is relatively noisy, and its interference with the sensitive rf module or analog module will generate relatively large interference, resulting in degraded chip performance.

Interference noise is attenuated by conduction over a long distance, and therefore, at present, interference between modules is reduced by increasing the isolation distance between modules, but this method consumes a large area of a chip, and when the interference noise is large, the isolation effect is limited.

Disclosure of Invention

In view of the above, the present invention provides a signal processing method and apparatus to reduce interference between modules in a chip.

In one implementation, there is provided a signal processing apparatus, the apparatus comprising: the digital signal module is used for outputting an original digital signal; and the bit processing module is used for receiving the original digital signal output by the digital signal module, and outputting the original digital signal after performing bit processing on the original digital signal.

Further, the above-bit processing includes exclusive-or processing or exclusive-or processing.

Further, the original digital signal includes an N + 1-bit original digital output code, and the upper-bit processing module is specifically configured to:

performing bit processing on the N-bit digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code, wherein the N-bit digital output code is a digital output code except the ith-bit digital output code in the N + 1-bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on the N +1-i bit digital output code by using the i-th bit digital output code in the N +1 bit original digital output code, wherein the N +1-i bit digital output code is a digital output code behind the i-th bit digital output code in the N +1 bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on each bit of the N +1 bit original digital output code by using an ith bit digital output code in the N +1 bit original digital output code;

wherein i and N are positive integers, and i < N.

Further, the ith digital output code is randomly flipped by thermal noise.

Further, the ith digital output code is the lowest digital output code of the N +1 original digital output codes.

Further, the above apparatus further comprises: and the digital processing output module is used for receiving the digital signal which is output by the bit processing module and is subjected to bit processing and carrying out parallel-to-serial processing on the digital signal.

Further, the digital signal module is an analog-to-digital conversion (ADC) analog module for quantizing the analog input signal to generate an original digital signal.

In one implementation, a signal processing method is provided, the method comprising: outputting an original digital signal; and carrying out bit processing on the original digital signal and then outputting the processed signal.

Further, the bit processing is performed on the original digital signal, and the bit processing includes: and carrying out exclusive-or processing or exclusive-or processing on the original digital signal.

Further, the above original digital signal includes an N +1 bit original digital output code, and the bit processing is performed on the original digital signal, including:

performing bit processing on the N-bit digital output code by using an ith-bit digital output code in the N + 1-bit original digital output code, wherein the N-bit digital output code is a digital output code except the ith-bit digital output code in the N + 1-bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on the N +1-i bit digital output code by using the i-th bit digital output code in the N +1 bit original digital output code, wherein the N +1-i bit digital output code is a digital output code behind the i-th bit digital output code in the N +1 bit original digital output code; alternatively, the first and second electrodes may be,

performing bit processing on each bit of the N +1 bit original digital output code by using an ith bit digital output code in the N +1 bit original digital output code;

wherein i and N are positive integers, and i < N.

Further, the ith digital output code is randomly flipped by thermal noise.

Further, the ith digital output code is the lowest digital output code of the N +1 original digital output codes.

Further, the above method further comprises: and receiving the digital signal subjected to the bit processing, and performing parallel-to-serial processing on the digital signal.

Further, outputting the original digital signal, comprising: an analog input signal is received and quantized to produce an original digital signal.

The method and the device consider the characteristic that the interference noise generated based on the digital signal is strongly correlated with the input signal characteristic, and reduce the interference noise of the digital signal at the source, so that the interference noise strongly correlated with the input signal characteristic is changed into weak correlation, the interference noise is randomized, the interference of a digital module on other modules in a chip is reduced, the interference of the randomized interference noise on a sensitive module in the SOC chip can be basically ignored, and the overall performance index of the SOC chip is improved.

Drawings

The following description of the embodiments of the present invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a signal processing apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a randomized digital signal being restored to an original signal by bit operation according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating output and recovery of an original digital signal after an exclusive or process is performed on the original digital signal according to an embodiment of the present invention;

fig. 4 is a schematic diagram of another signal processing apparatus according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating an output and recovery of an original digital signal after an exclusive nor process is performed according to an embodiment of the present invention;

fig. 6 is a schematic diagram of another signal processing apparatus according to an embodiment of the present invention;

fig. 7 is a schematic diagram of another signal processing apparatus according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a conventional ADC circuit;

fig. 9 is a schematic structural diagram of an ADC circuit according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a signal processing method according to an embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort. For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product.

The SoC chip has a complex circuit structure, mutual interference between modules is a common phenomenon in the SoC chip, and particularly, interference of a digital module with high noise to a sensitive module often causes deterioration of the overall performance index of the SoC chip. The conventional method of reducing interference between modules by increasing the isolation distance between modules consumes a large area of a chip, and the isolation effect is limited when interference noise is large.

In view of the above technical problems, the embodiments of the present invention provide a method and an apparatus for reducing the interference noise of a digital signal at the source based on the characteristic that the interference noise generated by the digital signal (also referred to as digital output code) is strongly correlated with the input signal characteristic, so that the interference noise strongly correlated with the input signal characteristic is changed into weak correlation, and further the interference noise is randomized, and the interference of a digital module on other modules in a chip is reduced. In the method, the digital signal is subjected to bit processing, interference noise is randomized through the bit processing, the interference of the randomized interference noise on a sensitive module in the SOC chip can be basically ignored, and further the overall performance index of the SOC chip is improved.

Please refer to fig. 1, which is a schematic diagram of a signal processing apparatus according to an embodiment of the present invention. As shown in fig. 1, the signal processing apparatus 100 includes a digital signal module 110 and a bit processing module 120. The digital signal module 110 is configured to output an original digital signal, and the bit processing module 120 is configured to receive the original digital signal output by the digital signal module 110, perform bit processing on the original digital signal, and output the processed original digital signal.

The original digital signal outputted from the digital signal module 110 includes an (N +1) -bit original digital output code, and the bit processing or implementing manner of the (N +1) -bit original digital output code Dr < N:0> by the bit processing module 120 can be various, for example:

the first mode is as follows: and performing bit processing on the N-bit digital output code by using the ith-bit digital output code in the (N +1) -bit original digital output code, wherein the N-bit digital output code is the digital output code except the ith-bit digital output code in the (N +1) -bit original digital output code. In the first way, the bit processing module 120 does not perform bit processing on the ith digital output code, or performs bit processing on the ith digital output code by using 0 or 1.

The second mode is as follows: and performing bit processing on the (N +1-i) bit digital output code by using the ith bit digital output code in the (N +1) bit original digital output code, wherein the (N +1-i) bit digital output code is a digital output code behind the ith bit digital output code in the (N +1) bit original digital output code. In the second way, the bit processing module 120 does not perform bit processing on the digital output code before the ith bit digital output code, or performs bit processing on the digital output code before the ith bit digital output code by using 0 or 1. In addition, the ith digital output code may or may not be bit processed, or bit processing is performed on the ith digital output code by using 0 or 1.

The third mode is as follows: and performing bit processing on each bit of the (N +1) -bit original digital output code by using the ith-bit digital output code in the (N +1) -bit original digital output code.

I and N are positive integers, and i < N.

The ith digital output code is randomly flipped by the influence of thermal noise. After the bit operation is carried out on the digital output codes of other bits, the digital output codes of other bits also become randomized, so that the digital signals after the bit processing are weakly correlated with the input signals, and further, the generated interference noise is weakly correlated with the input signals, thereby becoming randomized interference noise. The interference of the randomized interference noise on sensitive modules in the SOC chip can be basically ignored, and the overall performance index of the SOC chip is improved.

For example, the relatively low-order output code in the original digital output code is affected by the thermal noise of the internal device, and after the random flipping and the bit operation of the relatively high-order digital output code, the digital output code becomes randomized, so that the digital signal after the bit processing is weakly correlated with the input signal, and the generated interference noise is weakly correlated with the input signal, thereby becoming randomized interference noise. The interference of the randomized interference noise on sensitive modules in the SOC chip can be basically ignored, and the overall performance index of the SOC chip is improved.

The embodiment of the invention does not limit the digit of the ith digit output code, and the lower the digit output code, the better the anti-interference effect. In one implementation, the lowest order bit may be selected or chosen from the 4 last bits. For example, a 16-bit ADC output data N <15:0>, if N <4> is not affected by thermal noise and will not flip randomly, and N <3 > is affected by thermal noise and will flip randomly, then i ≦ 3, i.e. the lower 4 bits will flip randomly, and all can be used for bit processing.

Further, the above bit processing may be exclusive or exclusive nor processing.

Several implementations are described below in conjunction with the following figures.

Referring to fig. 1, in an implementation manner shown by a dotted line in fig. 1, the original digital signal output by the digital signal module 110 includes an (N +1) -bit original digital output code Dr < N:0>, and each bit of the original digital output code Dr < N:1> and the least significant bit Dr <0> in the original digital signal are respectively processed to obtain Dp < N:1 >. If the lowest bit is not processed, then Dp <0> and Dr <0> have the same value, and finally the digital signal Dp < N:0> is obtained.

Taking the bit processing shown in fig. 1 as exclusive-or processing as an example, since the exclusive-or processing result of the number 0 is equivalent to nothing, 0 may be used as the input of the exclusive-or processing of the least significant bit Dr <0 >.

With further reference to FIG. 2, the randomized digital signal Dp < N:0> may be restored to the original signal Dr < N:0> by the bit operations shown in FIG. 2. The receiving module of the digital signal can recover the original signal Dr < N:0> if necessary by referring to the bit operation shown in fig. 2, and then perform the subsequent processing. Fig. 3 illustrates a 16-bit digital signal as an example, and shows an output and recovery example after performing xor processing on the 16-bit original digital signal.

Please refer to fig. 4, which is a schematic diagram of another signal processing apparatus according to an embodiment of the present invention. As shown in fig. 4, the signal processing apparatus 400 includes a digital signal module 410 and a bit processing module 420. The digital signal module 410 and the bit processing module 420 are the same as those described above, and are not described again.

In another implementation shown by the dotted line in fig. 4, the original digital signal output by the digital signal module 410 includes (N +1) -bit original digital output codes Dr < N:0>, and each bit of the original digital output codes Dr < N:1> and the lowest bit Dr <0> in the original digital signal are respectively processed to obtain Dp < N:1 >. If the lowest bit is not processed, then Dp <0> and Dr <0> have the same value, and finally the digital signal Dp < N:0> is obtained.

Taking the bit processing shown in fig. 4 as exclusive nor processing as an example, since the exclusive nor processing result of the number 1 is equivalent to nothing, 1 may be used as the input of the exclusive nor processing of the least significant bit Dr <0 >.

With continued reference to FIG. 4, the randomized digital signal Dp < N:0> may be restored to the original signal Dr < N:0> by the bit operations shown in FIG. 4. The receiving module of the digital signal can recover the original signal Dr < N:0> if necessary by referring to the bit operation shown in fig. 4, and then perform the subsequent processing. Fig. 5 takes a 16-bit digital signal as an example, and shows an example of output and recovery after performing exclusive nor processing on the 16-bit original digital signal.

Fig. 1 and 4 are described using the least significant bit as an example, and in other implementations, other bits, such as the second last bit, the third bit, or the fourth bit, may be used for bit processing as long as they satisfy random flipping under the influence of thermal noise.

Please refer to fig. 6 and 7, which are schematic diagrams of two other signal processing apparatuses according to embodiments of the present invention. As shown in fig. 6, the signal processing apparatus 600 includes a digital signal module 610 and a bit processing module 620; as shown in fig. 7, the signal processing apparatus 600 includes a digital signal module 710 and a bit processing module 720. The digital signal modules 610 and 710 and the bit processing modules 620 and 720 are the same as those described above and are not described again.

In another implementation manner shown by the dotted line box in fig. 6, the original digital signal output by the digital signal module 610 includes an (N +1) -bit original digital output code Dr < N:0>, and each bit of the original digital output code Dr < N:2> and the second last bit Dr <1> in the original digital signal are respectively subjected to xor processing to obtain Dp < N:2 >. The second last bit and the lowest bit are not processed or are processed with XOR with 0, then Dp <0> and Dr <0> have the same value, Dp <1> and Dr <1> have the same value, and finally the digital signal Dp < N:0> is obtained.

In another implementation shown by the dotted line box in fig. 7, the original digital signal output by the digital signal module 710 includes an (N +1) -bit original digital output code Dr < N:0>, and each bit of the original digital output code Dr < N:2> and the second last bit Dr <1> in the original digital signal are respectively subjected to the same or processing to obtain Dp < N:2 >. The second last bit and the lowest bit are not processed or are processed with the same or same as 1, then the values of Dp <0> and Dr <0> are the same, and the values of Dp <1> and Dr <1> are the same, finally the digital signal Dp < N:0> is obtained.

The receiving module of the digital signal can recover the original signal Dr < N:0> if necessary by referring to the bit operation shown in fig. 6 or fig. 7, and then perform the subsequent processing.

In the above embodiments, the digital signal module 110 is used to output a raw digital signal, which may be a signal source generating a digital signal or may be an ADC analog module converting an analog signal into a digital signal. The embodiment of the present invention is not limited as long as the digital signal can be output.

The following description will be made taking an ADC circuit as an example.

Please refer to fig. 8, which is a schematic diagram of a conventional ADC circuit. As shown in fig. …, the ADC circuit 800 includes an ADC analog module 810 and an ADC digital processing output module 820. The ADC analog module 810 quantizes the analog input signal Vin to generate an (N +1) -bit raw digital output code Dr < N:0>, N being a positive integer. The ADC digital processing output module 820 is coupled to the ADC analog module 810, receives the raw digital output code Dr < N:0> generated by the ADC analog module 810, i.e. the raw digital output code Dr < N:0> generated by the ADC analog module 810 is input to the ADC digital processing output module 820, and the ADC digital processing output module 820 performs output pre-processing (e.g. parallel to serial processing) on the raw digital output code Dr < N:0> to output the (M +1) -bit digital output code D < M:0 >.

The digital output codes Dr < N:0> and D < M:0> are digitized representations of the continuous-time input signal Vin of the ADC circuit 800, also referred to as digital signals. The digital output code is strongly correlated with the frequency amplitude of the analog input signal Vin, which is a continuous-time input signal. In the high-speed ADC circuit, the digital output code can be output at the same high speed by the high-speed ADC circuit, the disturbance of a power supply, a ground and a substrate can be caused when the digital circuit works normally, the disturbance is closely related to the characteristics of an input signal, and sensitive modules in a chip can be easily influenced by the transmission of the substrate through the power supply and the ground. Disturbance closely related to input signal characteristics is transmitted to the sensitive module to cause deterioration of key system indexes of the SOC chip, and overall performance indexes of the SOC chip are reduced.

The ADC circuit provided by the embodiment of the present invention can be obtained by applying the above bit processing method to the ADC circuit. Fig. 9 is a schematic structural diagram of an ADC circuit according to an embodiment of the invention. As shown in fig. 9, the ADC circuit 900 includes an ADC analog module 910, a bit processing module 920, and an ADC digital processing output module 930. The ADC analog module 910 and the ADC digital processing output module 930 are the same as those described above, and are not described herein again. The bit processing module 920 is coupled to the ADC analog module 910, and receives the original digital signal generated by the ADC analog module 910, for example, an (N +1) -bit digital output code Dr < N:0 >; and bit-processes the original digital signal to generate a bit-processed digital signal, taking an (N +1) -bit digital output code Dp < N:0> as an example. The ADC digital processing output module 930 is coupled to the bit processing module 920, and performs output pre-processing on the digital signal subjected to bit processing to output an analog-to-digital converted digital signal, for example, an (M +1) -bit digital output code D < M:0 >.

The bit processing mode of the bit processing module 920 is the same as that described above, and may adopt xor processing or xnor processing. And which bit is specifically adopted for bit processing, which is the same as the above description, and is not described herein again.

When the above modules can be implemented by hardware circuits, the modules may also be referred to as circuits, for example, the digital signal module 110 is referred to as a digital signal circuit.

The embodiment of the invention also provides a signal processing method. Referring to fig. 10, which is a schematic diagram of a signal processing method according to an embodiment of the present invention, as shown in fig. 10, the method is executed by a signal processing apparatus, and includes the following steps:

s101, receiving an original digital signal;

and S102, carrying out bit processing on the original digital signal and then outputting the processed signal.

The bit processing method is the same as the above description, and exclusive or processing may be adopted, or exclusive or processing may also be adopted. And which bit is specifically adopted for bit processing, which is the same as the above description, and is not described herein again.

Furthermore, the generation of the original digital signal is provided by different modules in different circuits, as in the above embodiments. For example, in one implementation, a signal processing device receives an analog input signal and quantizes the analog input signal to produce an original digital signal.

Optionally, before outputting the digital signal after the bit processing, output pre-processing is performed, for example, the digital signal after the bit processing is received, and the digital signal is processed from parallel to serial.

Therefore, the embodiment of the invention provides a method and a device for reducing the interference noise of the digital signal at the source based on the characteristic that the interference noise generated by the digital signal is strongly correlated with the characteristics of the input signal, so that the interference noise strongly correlated with the characteristics of the input signal is changed into weak correlation, the interference noise is further randomized, and the interference of a digital module on other modules in a chip is reduced. In the method, the digital signal is subjected to bit processing, interference noise is randomized through the bit processing, the interference of the randomized interference noise on a sensitive module in the SOC chip can be basically ignored, and further the overall performance index of the SOC chip is improved.

The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.