阅读说明：本技术 一种适用于跳频抗干扰系统高动态环境下的同步方法 (Synchronization method suitable for frequency hopping anti-interference system in high dynamic environment ) 是由 陈敬乔 王赛宇 王杨 于 2020-04-22 设计创作，主要内容包括：本发明公开了一种适用于跳频抗干扰系统高动态环境下的同步方法,它涉及跳频抗干扰系统中的高动态同步技术。本发明基于跳频帧结构中有限的同步序列,采用周期差值统计的方法对多普勒码偏进行估计与校正,消除多普勒码偏产生的时钟偏差。载波同步采用分段匹配滤波、基于分段累加的FFT频偏估计等方式,实现了大频偏搜索、频率动态补偿与跟踪。同步过程中,码偏和频偏的估计与校正二者相互配合,互为基础,使得机载等高动态平台的同步性能稳定可靠。特别适用于提高卫星跳频通信系统的抗多普勒能力。(The invention discloses a synchronization method suitable for a frequency hopping anti-interference system under a high dynamic environment, and relates to a high dynamic synchronization technology in the frequency hopping anti-interference system. The invention estimates and corrects the Doppler code offset by adopting a period difference value statistical method based on the limited synchronous sequence in the frequency hopping frame structure, and eliminates the clock offset generated by the Doppler code offset. The carrier synchronization adopts the modes of sectional matched filtering, FFT frequency deviation estimation based on sectional accumulation and the like, thereby realizing large frequency deviation search, frequency dynamic compensation and tracking. In the synchronization process, the estimation and correction of the code offset and the frequency offset are mutually matched and are mutually basic, so that the synchronization performance of the airborne equal-height dynamic platform is stable and reliable. The method is particularly suitable for improving the Doppler resistance of a satellite frequency hopping communication system.)

1. A synchronization method suitable for a frequency hopping anti-interference system under a high dynamic environment is characterized by comprising the following steps:

calculating the maximum frequency offset according to the flight speed of the high maneuvering platform, determining the length of a captured segment, and capturing a synchronous sequence in a frequency hopping frame structure by adopting a segmented sliding matched filtering mode; wherein the length of each section is not more than half of the length of the maximum frequency deviation period;

counting from 0 from the capture of the synchronous sequence, and calculating the number of clock cycles between the synchronous sequences with continuously set number; carrying out cycle statistics every time a set number of synchronous sequences are captured, and recording the number A of clock cycles contained in the counted number A;

thirdly, preliminarily judging the clock period number A captured for multiple times, and judging whether the clock period number A meets constraint conditions; wherein the constraint conditions are as follows: under a reference clock, setting the number of clock cycles contained in the synchronization sequences of the set number as B, if the absolute value of A-B is less than a threshold value, judging that the value of the clock cycles A obtained at the time is valid, and otherwise, judging that the value is invalid;

fourthly, calculating and averaging according to the obtained effective clock period number A to obtain clock deviation and adjusting local clock frequency; completing the correction of large clock skew;

acquiring the next synchronous sequence by taking a local clock as a reference, performing segmented matched filtering on the synchronous sequence to eliminate modulation information in the synchronous sequence, and performing frequency offset estimation by using the segmented accumulated value as FFT (fast Fourier transform); completing large frequency offset correction;

after correcting the large clock offset and the large frequency offset, entering a clock tracking stage, performing error estimation by adopting a delay locked loop, and performing local clock adjustment according to the error value to finish the accurate synchronization of the clock;

and the synchronization suitable for the high dynamic environment of the frequency hopping anti-interference system is completed.

Technical Field

The invention relates to a synchronization method suitable for a frequency hopping anti-interference system in a high dynamic environment in the field of satellite communication, which is suitable for high dynamic characteristics, supports various airborne platforms, and is particularly suitable for improving the large Doppler frequency offset and code offset resistance of a high-speed frequency hopping system in satellite communication.

Background

In recent years, extensive and intensive research has been carried out at home and abroad aiming at the synchronization problem of the communication receiver in the high dynamic environment, and some high dynamic receivers have been developed and produced. However, the research on the frequency hopping system synchronization technology under the condition of high dynamic environment is not much, and mature technologies and equipment for supporting the application of the combat aircraft platform are not available at present.

Because the signal time interval for synchronization in the frequency hopping system is long, which means that the synchronization rate is low, the time required for receiving the synchronization sequence is long, and the adjustment is slow, the requirements on the synchronization acquisition and tracking of the receiver in a high dynamic environment are high, and the realization is difficult.

Due to the complex battlefield environment, general communication equipment is difficult to adapt to a high maneuvering platform, so that battlefield viability faces serious threats. In order to improve the adaptability of the existing frequency hopping system and meet the requirement of high dynamic, a synchronization method based on the frequency hopping system is provided.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a high dynamic synchronization method capable of adapting to a frequency hopping anti-interference system, aiming at the above disadvantages in the background art.

The technical scheme adopted by the invention is as follows:

calculating the maximum frequency offset according to the flight speed of the high maneuvering platform, determining the length of a captured segment, and capturing a synchronous sequence in a frequency hopping frame structure by adopting a segmented sliding matched filtering mode; wherein the length of each section is not more than half of the length of the maximum frequency deviation period;

counting from 0 from the capture of the synchronous sequence, and calculating the number of clock cycles between the synchronous sequences with continuously set number; carrying out cycle statistics every time a set number of synchronous sequences are captured, and recording the number A of clock cycles contained in the counted number A;

thirdly, preliminarily judging the clock period number A and judging whether the clock period number A meets constraint conditions or not; wherein the constraint conditions are as follows: under a reference clock, setting the number of clock cycles contained in the synchronization sequences of the set number as B, if the absolute value of A-B is less than a threshold value, judging that the value of the clock cycles A obtained at the time is valid, and otherwise, judging that the value is invalid;

fourthly, calculating and averaging according to the obtained effective clock period number A to obtain clock deviation and adjusting local clock frequency; completing the correction of large clock skew;

acquiring the next synchronous sequence by taking a local clock as a reference, performing segmented matched filtering on the synchronous sequence to eliminate modulation information in the synchronous sequence, and performing frequency offset estimation by using the segmented accumulated value as FFT (fast Fourier transform); completing large frequency offset correction;

after correcting the large clock offset and the large frequency offset, entering a clock tracking stage, performing error estimation by adopting a delay locked loop, and performing local clock adjustment according to the error value to finish the accurate synchronization of the clock.

And completing the synchronization method suitable for the high dynamic environment of the frequency hopping anti-interference system.

Compared with the background technology, the invention has the following advantages:

1. the design of the invention is very suitable for the clock synchronization and the carrier synchronization of the high-speed frequency hopping signal and is suitable for being realized by adopting the FPGA.

2. The adaptive high dynamic range is large, the flight speed is Mach 2, the acceleration is 8g, the frequency deviation range is +/-80 kHz, and the frequency change rate range is +/-9.3 kHz/s.

3. The frame structure of the invention contains few synchronous sequences, the frame overhead is small, and the frame efficiency is high.

Drawings

Fig. 1 is a schematic diagram of the frequency hopping frame structure of the present invention.

Fig. 2 is a schematic diagram of the doppler code offset estimation method of the present invention.

Fig. 3 is a schematic diagram of the frequency hopping synchronization process of the present invention.

Detailed Description

Referring to fig. 1 to 3, a frequency hopping frame structure of a satellite communication system is shown in fig. 1, and a satellite communication system repeater transmits information according to the frequency hopping frame structure; the clock skew estimation method is as shown in fig. 2, and the clock skew is calculated according to the difference between the number of clock cycles between the N identical sequences and the number of reference clock cycles; the schematic diagram of the synchronization process is shown in fig. 3, after the ground station of the frequency hopping satellite communication system is started, the acquisition of the synchronization sequence is completed first, and then the clock offset estimation, the frequency offset estimation and the clock tracking are performed. The invention estimates and corrects the Doppler code offset by adopting a period difference value statistical method based on the limited synchronous sequence in the frequency hopping frame structure, and eliminates the clock offset generated by the Doppler code offset. The carrier synchronization adopts the modes of sectional matched filtering, FFT frequency deviation estimation based on sectional accumulation and the like, thereby realizing large frequency deviation search, frequency dynamic compensation and tracking. In the synchronization process, the estimation and correction of the code offset and the frequency offset are mutually matched and are mutually basic, so that the synchronization performance of the airborne equal-height dynamic platform is stable and reliable. The method is particularly suitable for improving the Doppler resistance of a satellite frequency hopping communication system.

The present invention will be further explained below.

The invention comprises the following steps:

-capturing a synchronization sequence in a frequency hopping frame structure. And calculating the maximum frequency deviation according to the flight speed of the high maneuvering platform, and determining the length of the captured segment. Because the frequency offset is large, a segmented sliding matched filtering mode is adopted, the length L of each segment is not greater than E, wherein E is half of the length of data contained in one period of the maximum frequency offset;

the segment length may typically be half the length of the frequency offset period or 1/4;

secondly, after the synchronous sequence is captured, a period difference value method is adopted to carry out clock offset estimation. The method comprises the following steps: counting from 0 from the capture to the synchronization sequence, calculating the number of clock cycles between 10 consecutive synchronization sequences; and counting every time 10 synchronization sequences are acquired, and periodically counting. Recording the number A of clock cycles contained in each 10 synchronous sequences for multiple times;

in practical applications, the length of the 10 synchronization sequences can be modified. If the number of clock cycles of the 10 synchronization sequences is not sufficient to accumulate an integer number of clock offsets, the value of 10 may be increased appropriately. This value is generally scaled in comparison to the highly dynamic conditions in the present process.

Thirdly, preliminarily judging the clock period number A and judging whether the clock period number A meets the constraint condition. Wherein the constraint conditions are as follows: the number B of clock cycles that should be included in the 10 synchronization sequences is the reference clock. If the absolute value of A-B is less than 200, the value of the obtained clock period number A is judged to be valid, otherwise, the value is judged to be invalid.

Since there may be mis-capture and miss-capture in the acquisition of the synchronization sequence, it is assumed that the clock period number a may have a deviation, and the estimation result a with a larger deviation needs to be discarded so as not to generate an error in the adjustment clock.

Fourthly, calculating and averaging according to the obtained clock period number A to obtain clock deviation and adjusting the local clock frequency; completing the correction of large clock skew;

averaging is equivalent to filtering the estimation results, which can improve accuracy.

Acquiring a next synchronous sequence by taking a local clock as a reference, performing segmented matched filtering by using the synchronous sequence to eliminate modulation information in the synchronous sequence, and performing frequency offset estimation by using a segmented accumulated value as FFT (fast Fourier transform); completing large frequency offset correction;

because the frequency offset is larger and the signal noise in actual work is lower, the energy of the data is improved in an accumulation mode, and then the accumulated data is used for FFT, so that the frequency offset estimation after FFT is more accurate.

After correcting large clock deviation and large frequency deviation, entering into clock tracking stage. And the traditional delay locked loop is adopted for error estimation, and the error value is sent to a local clock adjusting module to finish the accurate synchronization of the clock.

And completing the waveform design and demodulation suitable for high-speed frequency hopping.