阅读说明：本技术 用于s-fsk接收器的阈值计算电路、集成电路及其相关方法 (Threshold calculation circuit for S-FSK receiver, integrated circuit and related method thereof ) 是由 N·克莱默 A·M·阿克尔 A·A·帕特基 T·P·保莱蒂 于 2020-02-11 设计创作，主要内容包括：本申请题为“用于S-FSK接收器的阈值计算电路、集成电路及其相关方法”。阈值计算电路(100)包括输入电路(102)、最大滤波器电路(104)、最小滤波器电路(106)和运算电路(108)。输入电路(102)从数字滤波电路(112)接收离散频率信号(110)。离散频率信号(110)基于由与数字滤波电路(112)相关联的S-FSK接收器(101)接收的S-FSK波形(114)。离散频率信号(110)代表使用S-FSK调制以形成S-FSK波形(114)的一系列数据帧中的数字逻辑电平。最大滤波器电路(104)基于离散频率信号(110)和预定阈值(118)调整最大幅度参数(116)。最小滤波器电路(106)基于离散频率信号(110)和预定阈值(118)调整最小幅度参数(120)。运算电路(108)基于最大幅度参数(116)和最小幅度参数(120)调适用于下一个数据帧的预定阈值(118)。还公开了用于计算阈值的集成电路和方法。(The application provides a threshold calculation circuit for an S-FSK receiver, an integrated circuit and a related method thereof. The threshold calculation circuit (100) includes an input circuit (102), a maximum filter circuit (104), a minimum filter circuit (106), and an arithmetic circuit (108). An input circuit (102) receives a discrete frequency signal (110) from a digital filter circuit (112). The discrete frequency signal (110) is based on an S-FSK waveform (114) received by an S-FSK receiver (101) associated with a digital filtering circuit (112). The discrete frequency signal (110) represents digital logic levels in a series of data frames modulated using S-FSK to form an S-FSK waveform (114). The maximum filter circuit (104) adjusts the maximum amplitude parameter (116) based on the discrete frequency signal (110) and a predetermined threshold (118). The minimum filter circuit (106) adjusts the minimum amplitude parameter (120) based on the discrete frequency signal (110) and a predetermined threshold (118). The arithmetic circuit (108) adapts the predetermined threshold (118) for the next data frame based on the maximum amplitude parameter (116) and the minimum amplitude parameter (120). An integrated circuit and a method for calculating a threshold value are also disclosed.)

1. A threshold calculation circuit for an extended frequency shift keying (S-FSK) receiver, the threshold calculation circuit comprising:

an input circuit configured to receive a discrete frequency signal from a digital filter circuit, wherein the discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filter circuit, wherein the discrete frequency signal represents digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform, each data frame comprising a valid portion and a zero energy portion, wherein the valid portion comprises at least one data word and the zero energy portion comprises at least one zero energy word, wherein each data word and zero energy word comprises a plurality of bit periods;

a maximum filter circuit configured to dynamically and selectively adjust a maximum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and a predetermined threshold;

a minimum filter circuit configured to dynamically and selectively adjust a minimum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and the predetermined threshold; and

an operational circuit configured to adapt the predetermined threshold for a next data frame after a current data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

2. The threshold calculation circuit of claim 1, wherein the maximum filter circuit is configured to:

i) determining whether the discrete frequency signal is greater than the predetermined threshold during each bit period of the series of data frames,

ii) modifying the maximum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is greater than the predetermined threshold to form a next maximum amplitude parameter for the next data frame,

iii) counting each bit period of the current data frame, and

iv) changing the maximum amplitude parameter to be equal to the next maximum amplitude parameter after counting the bit periods of the current data frame.

3. The threshold calculation circuit of claim 2, wherein the maximum filter circuit is configured to modify the maximum magnitude parameter according to the following equation:

where i is a current bit period, max amp param (i +1) is the next maximum amplitude parameter for the next bit period, discrete frequency sig (i) is the discrete frequency signal for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and max amp param (i) is the maximum amplitude parameter for the current bit period.

4. The threshold calculation circuit of claim 2, wherein the maximum filter circuit is configured to vary the maximum magnitude parameter according to the following equation:

max amp param(i+1)＝max amp param

where i is the current bit period, max amp param (i +1) is the next maximum amplitude parameter for the next bit period, and max amp param is the maximum amplitude parameter for the next data frame.

5. The threshold calculation circuit of claim 1, wherein the minimum filter circuit is configured to:

i) determining whether the discrete frequency signal is less than the predetermined threshold during each bit period of the series of data frames,

ii) modifying the minimum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is less than the predetermined threshold to form a next minimum amplitude parameter for the next data frame,

iii) counting each bit period of the current data frame, and

iv) after counting the bit periods of the current data frame, changing the minimum amplitude parameter to be equal to the next minimum amplitude parameter.

6. The threshold calculation circuit of claim 5 wherein the minimum filter circuit is configured to modify the minimum magnitude parameter according to the following equation:

where i is a current bit period, min amp param (i +1) is the next minimum amplitude parameter for a next bit period, discrete frequency sig (i) is the discrete frequency signal for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and min amp param (i) is the minimum amplitude parameter for the current bit period.

7. The threshold calculation circuit of claim 5, wherein the minimum filter circuit is configured to change the minimum magnitude parameter according to the following equation:

min amp param(i+1)＝min amp param

where i is the current bit period, min amp param (i +1) is the next minimum amplitude parameter for the next bit period, and min amp param is the minimum amplitude parameter for the next data frame.

8. The threshold calculation circuit of claim 1, wherein the operational circuit is configured to:

i) computing an updated threshold value for the predetermined threshold value based on the maximum amplitude parameter and the minimum amplitude parameter after the current data frame, and

ii) modifying the predetermined threshold for the next data frame based on the updated threshold.

9. The threshold calculation circuit of claim 8, wherein the operation circuit is configured to operate the updated threshold according to the following equation:

wherein updated thresh val is the updated threshold value operated after the current data frame, max ampparam is the maximum amplitude parameter after the current data frame, and min amp param is the minimum amplitude parameter after the current data frame.

10. The threshold calculation circuit of claim 8, wherein the operational circuit is configured to modify the predetermined threshold according to the following equation:

updated thresh val＝predetermined thresh

wherein updated threshold val is the updated threshold value operated after the current data frame and predetermined threshold value is the predetermined threshold value for the next data frame.

11. The threshold calculation circuit of claim 1, further comprising:

a second input circuit configured to receive a second frequency signal from the digital filtering circuit, wherein the second frequency signal is based on the S-FSK waveform received by the S-FSK receiver, wherein the second frequency signal represents a second digital logic level in the series of data frames that are modulated using S-FSK to form the S-FSK waveform;

a second maximum filter circuit configured to dynamically and selectively adjust a second maximum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and a second predetermined threshold;

a second minimum filter circuit configured to dynamically and selectively adjust a second minimum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and the second predetermined threshold; and

a second operational circuit configured to adapt the second predetermined threshold for the next data frame after the current data frame based on the second maximum amplitude parameter and the second minimum amplitude parameter.

12. An integrated circuit, comprising:

a threshold calculation circuit, comprising:

an input circuit configured to receive a discrete frequency signal from a digital filtering circuit, wherein the discrete frequency signal is based on an extended frequency shift keying (S-FSK) waveform received by an S-FSK receiver associated with the digital filtering circuit, wherein the discrete frequency signal represents digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform, each data frame comprising a valid portion and a zero energy portion, wherein the valid portion comprises at least one data word and the zero energy portion comprises at least one zero energy word, wherein each data word and zero energy word comprises a plurality of bit periods;

a maximum filter circuit configured to dynamically and selectively adjust a maximum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and a predetermined threshold;

a minimum filter circuit configured to dynamically and selectively adjust a minimum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and the predetermined threshold; and

an operational circuit configured to adapt the predetermined threshold for a next data frame after a current data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

13. The integrated circuit of claim 12, the threshold calculation circuit further comprising:

a second input circuit configured to receive a second frequency signal from the digital filtering circuit, wherein the second frequency signal is based on the S-FSK waveform received by the S-FSK receiver, wherein the second frequency signal represents a second digital logic level in the series of data frames that are modulated using S-FSK to form the S-FSK waveform;

a second maximum filter circuit configured to dynamically and selectively adjust a second maximum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and a second predetermined threshold;

a second minimum filter circuit configured to dynamically and selectively adjust a second minimum amplitude parameter during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and the second predetermined threshold; and

a second operational circuit configured to adapt the second predetermined threshold for the next data frame after the current data frame based on the second maximum amplitude parameter and the second minimum amplitude parameter.

14. The integrated circuit of claim 13, further comprising:

the digital filter circuit, wherein the digital filter circuit is configured to receive the S-FSK waveform, process the S-FSK waveform to create the discrete frequency signal and the second frequency signal, and provide the discrete frequency signal and the second frequency signal to the threshold calculation circuit; and

a limiter circuit configured to receive the discrete frequency signal and the second frequency signal from the digital filter circuit, receive the maximum amplitude parameter, the minimum amplitude parameter, the predetermined threshold, the second maximum amplitude parameter, the second minimum amplitude parameter, and the second predetermined threshold from the threshold calculation circuit, and generating a digital data stream based on the discrete frequency signal and the second frequency signal, the maximum amplitude parameter, the minimum amplitude parameter, the predetermined threshold, the second maximum amplitude parameter, the second minimum amplitude parameter, and the second predetermined threshold, wherein the digital data stream represents at least one of the digital logic level and the second digital logic level in the series of data frames using S-FSK modulation to form the S-FSK waveform.

15. The integrated circuit of claim 14, further comprising:

a correlator circuit configured to receive the digital data stream from the slicer circuit, decode the digital data stream into code words, correlate the code words based on a predetermined protocol, and generate one or more intermediate control signals based on the code words and the predetermined protocol; and

keep-alive circuitry configured to receive the one or more intermediate control signals from the correlator circuitry, process the one or more intermediate control signals to generate one or more communication signals, and provide the one or more communication signals at an output terminal.

16. A method for calculating a threshold to distinguish digital data signals of an extended frequency shift keying (S-FSK) waveform, the method comprising:

receiving at a threshold calculation circuit a discrete frequency signal from a digital filter circuit, wherein the discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filter circuit, wherein the discrete frequency signal represents digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform, each data frame including a valid portion and a zero energy portion, wherein the valid portion includes at least one data word and the zero energy portion includes at least one zero energy word, wherein each data word and zero energy word includes a plurality of bit periods;

dynamically and selectively adjusting a maximum amplitude parameter at the threshold calculation circuit during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and a predetermined threshold;

dynamically and selectively adjusting a minimum amplitude parameter at the threshold calculation circuit during a bit period of the series of data frames, wherein the adjustment is based on the discrete frequency signal and the predetermined threshold; and

adapting the predetermined threshold for a next data frame after a current data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

17. The method of claim 16, the adjusting of the maximum amplitude parameter comprising:

determining whether the discrete frequency signal is greater than the predetermined threshold during each bit period of the series of data frames;

modifying the maximum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is greater than the predetermined threshold to form a next maximum amplitude parameter for the next data frame;

counting each bit period of the current data frame; and is

After counting the bit periods of the current data frame, changing the maximum amplitude parameter to be equal to the next maximum amplitude parameter.

18. The method of claim 16, the adjusting of the minimum amplitude parameter comprising:

determining whether the discrete frequency signal is less than the predetermined threshold during each bit period of the series of data frames;

modifying the minimum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is less than the predetermined threshold to form a next minimum amplitude parameter for the next data frame;

counting each bit period of the current data frame; and is

After counting the bit periods of the current data frame, changing the minimum amplitude parameter to be equal to the next minimum amplitude parameter.

19. The method of claim 16, the adapting of the predetermined threshold comprising:

calculating an updated threshold for the predetermined threshold based on the maximum amplitude parameter and the minimum amplitude parameter after the current data frame; and is

Modifying the predetermined threshold for the next data frame based on the updated threshold.

20. The method of claim 16, further comprising:

receiving a second frequency signal from the digital filtering circuit at the threshold calculation circuit, wherein the second frequency signal is based on the S-FSK waveform received by the S-FSK receiver, wherein the second frequency signal represents a second digital logic level in the series of data frames that are modulated using S-FSK to form the S-FSK waveform;

dynamically and selectively adjusting a second maximum amplitude parameter at the threshold calculation circuit during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and a second predetermined threshold;

dynamically and selectively adjusting a second minimum amplitude parameter at the threshold calculation circuit during a bit period of the series of data frames, wherein the adjustment is based on the second frequency signal and the second predetermined threshold; and

adapting the second predetermined threshold for the next data frame after the current data frame based on the second maximum amplitude parameter and the second minimum amplitude parameter.

Background

Spread-spectrum frequency-shift keying (S-FSK) is a modulation and demodulation technique that combines the advantages of conventional spread-spectrum systems (e.g., immunity to narrowband interference) with the advantages of conventional FSK systems (e.g., low complexity). The S-FSK transmitter outputs a tone at one of two frequencies depending on the value of the digital data bit. Frequency 1002 may be referred to as a "marker" frequency (f)_M)1004 and "spatial" frequency (f)_S)1006 (see spectrum 1000 of fig. 10). For example, an S-FSK transmitter may transmit a signal at the "spatial" frequency 1006 to represent an "OFF" data bit and at the "marker" frequency 1004 to represent an "ON" data bit. The difference between S-FSK and conventional FSK is f_MFrequencies 1004 and f_SFrequencies 1006 are farther away from each other ("spread"). By mixing f_S1006 is disposed away from f_M1004, the transmission quality of the two signals becomes independent. In other words, each frequency will have its own attenuation factor and local narrowband noise spectrum. Thus, the narrowband interferer affects only one of the two frequency signals.

The S-FSK receiver performs FSK demodulation at the transmitted "tag" frequency 1004 and "spatial" frequency 1006, producing two demodulated signals, f for the "tag" frequency 1004_MAnd f for "spatial" frequency 1006_S(see FIG. 10). The decision unit may decide the value of the digital data bit based on the demodulated signal having a higher reception quality if the average reception quality of the demodulated "marker" frequency signal and the demodulated "space" frequency signal are similar. However, if the average reception quality of one demodulated frequency signal is better than the quality of the other frequency signal, the decision unit may decide the value of the digital data bit on the basis of the demodulation of the better channelThe signal is compared to a threshold value (T). In other words, the S-FSK receiver may perform FSK demodulation if both channels are good, or may perform on-off keying (OOK) demodulation if one channel is poor. In this case, the decision unit ignores the demodulated signal having a lower quality. Depending on the application of the S-FSK modulation, there may be periods of zero energy in the transmitted frequency signal. The decision unit may interpret this condition as a zero energy state if the average reception quality of both demodulation frequencies is below a threshold (T). Higher level coding may be employed in an S-FSK transmitter to generate a bit stream representing code words or commands modulated in an S-FSK waveform.

For example, the "SunSpec interoperability Specification, Communication Signal for Rapid Shutdown, Version 34" describes an S-FSK Communication system for transmitting and receiving S-FSK waveforms with Barker codes (Barker codes) representing sequences of "ON" and "OFF" digital data bits that are modulated and demodulated based ON the "marker" and "space" frequencies of an S-FSK modulation scheme. This S-FSK communication system uses Power Line Communication (PLC) technology to exchange a sequence of barker codewords representing commands for controlling a Photovoltaic (PV) array. For example, a command may be used to implement a fast shutdown, or other commands may be used to keep the array active. FIG. 11 shows the PLC protocol requirements set forth in the SunSpec interoperability Spec Specification, communication signals for fast shutdown, 34 th edition.

Disclosure of Invention

Examples of a threshold calculation circuit for an extended frequency shift keying (S-FSK) receiver include an input circuit, a maximum filter circuit, a minimum filter circuit, and an arithmetic circuit. The input circuit receives a discrete frequency signal from the digital filter circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal represents the digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods. The maximum filter circuit dynamically and selectively adjusts the maximum amplitude parameter during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit dynamically and selectively adjusts the minimum amplitude parameter during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The arithmetic circuit adapts, after the current data frame, the predetermined threshold for the next data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

An example of an integrated circuit includes a threshold calculation circuit having an input circuit, a maximum filter circuit, a minimum filter circuit, and an arithmetic circuit. The input circuit receives a discrete frequency signal from the digital filter circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal represents the digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods. The maximum filter circuit dynamically and selectively adjusts the maximum amplitude parameter during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit dynamically and selectively adjusts the minimum amplitude parameter during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The arithmetic circuit adapts, after the current data frame, the predetermined threshold for the next data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

An example of a method for calculating a threshold to distinguish digital data signals of an S-FSK waveform receives a discrete frequency signal from a digital filter circuit at a threshold calculation circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal represents the digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods. The maximum amplitude parameter is dynamically and selectively adjusted at the threshold calculation circuit during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The minimum amplitude parameter is dynamically and selectively adjusted at the threshold calculation circuit during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. The predetermined threshold for the next data frame is adapted after the current data frame based on the maximum amplitude parameter and the minimum amplitude parameter.

Drawings

Fig. 1 is a block diagram of an example of a threshold calculation circuit.

Fig. 2 is a block diagram of an example of an integrated circuit including a threshold calculation circuit.

Fig. 3 is a block diagram of an example of an integrated circuit including an S-FSK receiver.

Fig. 4 is a block diagram of an example of an integrated circuit including a Photovoltaic (PV) array fast shutdown control circuit.

Fig. 5 is a flow chart of an example of a process for calculating a threshold to distinguish digital data signals of an S-FSK waveform.

Fig. 6 in conjunction with fig. 5 is a flow chart of another example of a process for calculating a threshold to distinguish digital data signals of an S-FSK waveform.

Fig. 7, in conjunction with fig. 5, is a flow chart of yet another example of a process for calculating a threshold to distinguish digital data signals of an S-FSK waveform.

Fig. 8, in conjunction with fig. 5, is a flow chart of yet another example of a process for calculating a threshold to distinguish digital data signals of an S-FSK waveform.

Fig. 9, in conjunction with fig. 5, is a flow chart of yet another example of a process for calculating a threshold to distinguish digital data signals of an S-FSK waveform.

FIG. 10 is a graph showing "flag" frequency (f)_M) And "spatial" frequency (f)_S) Spectrum diagram of (a).

Fig. 11 is a diagram of an example of an S-FSK communication frame, a code word, and a zero energy word.

Fig. 12 is a flowchart of an example of a process for calculating the maximum parameter of an S-FSK frequency signal.

Fig. 13 is a flowchart of an example of a process for calculating minimum parameters of an S-FSK frequency signal.

Fig. 14 is a block diagram of an example of an S-FSK receiver architecture.

Fig. 15 is a diagram showing the MAX parameter, MIN parameter, and threshold (T) value calculated from the start of the S-FSK waveform over a series of communication frames.

Detailed Description

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and claims, the terms "including," comprising, "" having, "" with, "" having, "or variants thereof, are intended to be inclusive in a manner similar to the term" comprising, "and thus should be interpreted as" including, but not limited to … ….

Referring to fig. 1, an example of a threshold calculation circuit 100 for an extended frequency shift keying (S-FSK) receiver 101 includes an input circuit 102, a maximum filter circuit 104, a minimum filter circuit 106, and an arithmetic circuit 108. The input circuit 102 is configured to receive a discrete frequency signal 110, for example, from a digital filter circuit 112. The discrete frequency signal 110 is based on an S-FSK waveform 114 received by the S-FSK receiver 101 associated with the digital filtering circuitry. The discrete frequency signal 110 represents digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform 114. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods.

The maximum filter circuit 104 is configured to dynamically and selectively adjust the maximum magnitude parameter 116 during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal 110 and the predetermined threshold 118. The minimum filter circuit 106 is configured to dynamically and selectively adjust the minimum magnitude parameter 120 during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal 110 and the predetermined threshold 118. The operational circuit 108 is configured to adapt the predetermined threshold 118 for a next data frame after the current data frame based on the maximum amplitude parameter 116 and the minimum amplitude parameter 120.

In another example of the threshold calculation circuit 100, the discrete frequency signal 110 is a "mark" frequency signal having a bit period representing an "ON" logic level. In yet another example, the active portion of the data frame includes three data words, each data word including 11 bit periods. In yet another example, the zero-energy portion of the data frame includes 16 zero-energy words, each zero-energy word including 11 bit periods. In yet another example, each data frame includes 109 bit periods.

In another example of the threshold calculation circuit 100, the active portion of the data frame includes three consecutive data words representing a triplet of code words, in accordance with the "SunSpec interoperability specification, fast-shut down communication signal". In this example, the zero-energy portion of the data frame includes 16 consecutive zero-energy words having a null representing zero energy, in accordance with the "SunSpec interoperability Spec fast-closure communication Signal".

In yet another example of the threshold calculation circuit 100, the maximum filter circuit 104 is configured to: i) determining whether the discrete-frequency signal 110 is greater than a predetermined threshold 118 during each bit period of a series of data frames, ii) modifying the maximum amplitude parameter 116 during each bit period of a current data frame in which the discrete-frequency signal 110 is greater than the predetermined threshold 118 to form a next maximum amplitude parameter 116 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the maximum amplitude parameter 116 to be equal to the next maximum amplitude parameter 116' after counting the bit periods of the current data frame.

In another example of the threshold calculation circuit 100, the maximum filter circuit 104 is configured to modify the maximum magnitude parameter 116 according to the following equation:

where i is the current bit period, max amp param (i +1) is the next maximum amplitude parameter 116' for the next bit period, discrete frequency sig (i) is the discrete frequency signal 110 for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and max amp param (i) is the maximum amplitude parameter 116 for the current bit period.

In another example of the threshold calculation circuit 100, the maximum filter circuit 104 is configured to vary the maximum magnitude parameter 116 according to the following equation:

max amp param(i+1)＝max amp param

where i is the current bit period, max amp param (i +1) is the next maximum amplitude parameter 116' for the next bit period, and max amp param is the maximum amplitude parameter 116 for the next data frame.

In yet another example of the threshold calculation circuit 100, the minimum filter circuit 106 is configured to: i) determining whether the discrete-frequency signal 110 is less than a predetermined threshold 118 during each bit period of a series of data frames, ii) modifying the minimum amplitude parameter 120 during each bit period of a current data frame in which the discrete-frequency signal 110 is less than the predetermined threshold 118 to form a next minimum amplitude parameter 120 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the minimum amplitude parameter 120 to be equal to the next minimum amplitude parameter 120' after counting the bit periods of the current data frame.

In another example of the threshold calculation circuit 100, the minimum filter circuit 106 is configured to modify the minimum magnitude parameter 120 according to the following equation:

where i is the current bit period, min amp param (i +1) is the next minimum amplitude parameter 120' for the next bit period, discrete frequency sig (i) is the discrete frequency signal 110 for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and min amp param (i) is the minimum amplitude parameter 120 for the current bit period.

In another example of the threshold calculation circuit 100, the minimum filter circuit 106 is configured to change the minimum magnitude parameter 120 according to the following equation:

min amp param(i+1)＝min amp param

where i is the current bit period, min amp param (i +1) is the next minimum amplitude parameter 120' for the next bit period, and min amp param is the minimum amplitude parameter 120 for the next data frame.

In yet another example of the threshold calculation circuit 100, the arithmetic circuit 108 is configured to: i) operate an updated threshold for the predetermined threshold 118 based on the maximum amplitude parameter 116 and the minimum amplitude parameter 120 after the current data frame, and ii) modify the predetermined threshold 118 for the next data frame based on the updated threshold.

In another example of the threshold calculation circuit 100, the operation circuit 108 is configured to operate the updated threshold according to the following equation:

where updated thresh val is the updated threshold value operated after the current data frame, max amp param is the maximum amplitude parameter 116 after the current data frame, and min amp param is the minimum amplitude parameter 120 after the current data frame.

In another example of the threshold calculation circuit 100, the arithmetic circuit 108 is configured to modify the predetermined threshold 118 according to the following equation:

updated thresh val＝predetermined thresh

where updated thresh val is the updated threshold value operated after the current data frame and predetermined thresh is the predetermined threshold value 118 for the next data frame.

In another example, the threshold calculation circuit 100 further includes a second input circuit 122, a second maximum filter circuit 124, a second minimum filter circuit 126, and a second arithmetic circuit 128. The second input circuit 122 is configured to receive the second frequency signal 130 from the digital filter circuit 112. The second frequency signal 130 is based on the S-FSK waveform 114 received by the S-FSK receiver 101. The second frequency signal 130 represents a second digital logic level in a series of data frames that are modulated using S-FSK to form the S-FSK waveform 114.

The second maximum filter circuit 124 is configured to dynamically and selectively adjust the second maximum magnitude parameter 132 during a bit period of a series of data frames. The adjustment is based on the second frequency signal 130 and a second predetermined threshold 134. The second minimum filter circuit 126 is configured to dynamically and selectively adjust the second minimum amplitude parameter 136 during a bit period of a series of data frames. The adjustment is based on the second frequency signal 130 and a second predetermined threshold 134. The second arithmetic circuit 128 is configured to adapt the second predetermined threshold 134 for a next data frame after the current data frame based on the second maximum amplitude parameter 132 and the second minimum amplitude parameter 136.

In another example of the threshold calculation circuit 100, the second frequency signal 130 is a "spatial" frequency signal having a bit period representing an "OFF" logic level.

In yet another example of the threshold calculation circuit 100, the second maximum filter circuit 124 is configured to: i) determining whether the second frequency signal 130 is greater than a second predetermined threshold 134 during each bit period of a series of data frames, ii) modifying the second maximum amplitude parameter 132 during each bit period of a current data frame in which the second frequency signal 130 is greater than the second predetermined threshold 134 to form a next second maximum amplitude parameter 132 'for a next data frame, iii) counting each bit period of the current data frame, and iv) after counting the bit periods of the current data frame, changing the second maximum amplitude parameter 132 to be equal to the next second maximum amplitude parameter 132'.

In yet another example of the threshold calculation circuit 100, the second minimum filter circuit 126 is configured to: i) determining whether the second frequency signal 130 is less than a second predetermined threshold 134 during each bit period of a series of data frames, ii) modifying the second minimum amplitude parameter 136 during each bit period of a current data frame in which the second frequency signal 130 is less than the second predetermined threshold 134 to form a next second minimum amplitude parameter 136 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the second minimum amplitude parameter 136 to be equal to the next second minimum amplitude parameter 136' after counting the bit periods of the current data frame.

In yet another example of the threshold calculation circuit 100, the second arithmetic circuit 128 is configured to: i) after the current data frame, an updated second threshold value is operated for the second predetermined threshold value 134 based on the second maximum amplitude parameter 132 and the second minimum amplitude parameter 136, and ii) the second predetermined threshold value 134 for the next data frame is modified based on the updated second threshold value.

With continued reference to fig. 1, an example of an S-FSK receiver 101 includes a digital filtering circuit 112, a threshold calculation circuit 100, and a slicer circuit 138. The digital filter circuit 112 may be configured to receive the S-FSK waveform 114, process the S-FSK waveform 114 to create the discrete frequency signal 110 and the second frequency signal 130, and provide the discrete frequency signal 110 and the second frequency signal 130 to the threshold calculation circuit 100. Various examples of the threshold calculation circuit 100 are described above. For example, the slicer circuit 138 is configured to receive the discrete frequency signal 110 and the second frequency signal 130 from the digital filter circuit 112, receive the maximum amplitude parameter 116, the minimum amplitude parameter 120, the predetermined threshold 118, the second maximum amplitude parameter 132, the second minimum amplitude parameter 136, and the second predetermined threshold 134 from the threshold calculation circuit 100, generate a digital data stream 140 based on the received signals, parameters, and thresholds, and output the digital data stream 140. For example, the digital data stream 140 represents at least one of a digital logic level and a second digital logic level in a series of data frames that are modulated using S-FSK to form the S-FSK waveform 114.

With further reference to fig. 1, an example of a Photovoltaic (PV) array rapid shutdown control circuit 141 includes a digital filter circuit 112, a threshold calculation circuit 100, a limiter circuit 138, a correlator circuit 142, and a keep alive circuit 144. Various examples of the digital filter circuit 112, the threshold calculation circuit 100, and the limiter circuit 138 are described above. For example, the correlator circuit 142 is configured to receive the digital data stream 140 from the slicer circuit 138, decode the digital data stream 140 into codewords, correlate the codewords based on a predetermined protocol, and generate one or more intermediate control signals 146 based on the codewords and the predetermined protocol. For example, the keep-alive circuit 144 is configured to receive one or more intermediate control signals 146 from the correlator circuit 142, process the one or more intermediate control signals 146 to generate one or more communication signals 148, and output the one or more communication signals 148. For example, one or more communication signals 148 may be used to communicate with the PV system to support rapid shutdown of one or more PV arrays in the PV system.

Referring to fig. 2, an example of an integrated circuit 200 includes the threshold calculation circuit 100 (see also fig. 1). The threshold calculation circuit 100 includes an input circuit 102, a maximum filter circuit 104, a minimum filter circuit 106, and an arithmetic circuit 108. The input circuit 102 is configured to receive a discrete frequency signal 110 (see fig. 1), for example, from a digital filter circuit 112. The discrete frequency signal 110 is based on an S-FSK waveform 114 (see fig. 1) received by the S-FSK receiver 101 (see fig. 1) associated with a digital filter circuit 112. The discrete frequency signal 110 represents digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform 114. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods.

The maximum filter circuit 104 is configured to dynamically and selectively adjust the maximum magnitude parameter 116 during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal 110 and the predetermined threshold 134. The minimum filter circuit 106 is configured to dynamically and selectively adjust the minimum magnitude parameter 120 during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal 110 and the predetermined threshold 118. The operational circuit 108 is configured to adapt the predetermined threshold 118 for a next data frame after the current data frame based on the maximum amplitude parameter 116 and the minimum amplitude parameter 120.

In another example of the integrated circuit 200, the maximum filter circuit 104 is configured to: i) determining whether the discrete-frequency signal 110 is greater than a predetermined threshold 118 during each bit period of a series of data frames, ii) modifying the maximum amplitude parameter 116 during each bit period of a current data frame in which the discrete-frequency signal 110 is greater than the predetermined threshold 118 to form a next maximum amplitude parameter 116 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the maximum amplitude parameter 116 to be equal to the next maximum amplitude parameter 116' after counting the bit periods of the current data frame.

In yet another example of the integrated circuit 200, the minimum filter circuit 106 is configured to: i) determining whether the discrete-frequency signal 110 is less than a predetermined threshold 118 within each bit period of a series of data frames, ii) modifying the minimum amplitude parameter 120 during each bit period of a current data frame in which the discrete-frequency signal 110 is less than the predetermined threshold 118 to form a next minimum amplitude parameter 120 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the minimum amplitude parameter 120 to be equal to the next minimum amplitude parameter 120' after counting the bit periods of the current data frame.

In another example of the integrated circuit 200, the operational circuitry 108 is configured to: i) operate an updated threshold for the predetermined threshold 118 based on the maximum amplitude parameter 116 and the minimum amplitude parameter 120 after the current data frame, and ii) modify the predetermined threshold 118 for the next data frame based on the updated threshold.

In yet another example of the integrated circuit 200, the threshold calculation circuit 100 further includes a second input circuit 122, a second maximum filter circuit 124, a second minimum filter circuit 126, and a second arithmetic circuit 128. The second input circuit 122 is configured to receive a second frequency signal 130, for example, from the digital filter circuit 112. The second frequency signal 130 is based on the S-FSK waveform 114 received by the S-FSK receiver 101. The second frequency signal 130 represents a second digital logic level in a series of data frames that are modulated using S-FSK to form the S-FSK waveform 114.

The second maximum filter circuit 124 is configured to dynamically and selectively adjust the second maximum magnitude parameter 132 during a bit period of a series of data frames. The adjustment is based on the second frequency signal 130 and a second predetermined threshold 134. The second minimum filter circuit 126 is configured to dynamically and selectively adjust the second minimum amplitude parameter 136 during a bit period of a series of data frames. The adjustment is based on the second frequency signal 130 and a second predetermined threshold 134. The second arithmetic circuit 128 is configured to adapt the second predetermined threshold 134 for a next data frame after the current data frame based on the second maximum amplitude parameter 132 and the second minimum amplitude parameter 136.

In another example of the integrated circuit 200, the second maximum filter circuit 124 is configured to: i) determining whether the second frequency signal 130 is greater than a second predetermined threshold 134 during each bit period of a series of data frames, ii) modifying the second maximum amplitude parameter 132 during each bit period of a current data frame in which the second frequency signal 130 is greater than the second predetermined threshold 134 to form a next second maximum amplitude parameter 132 'for a next data frame, iii) counting each bit period of the current data frame, and iv) after counting the bit periods of the current data frame, changing the second maximum amplitude parameter 132 to be equal to the next second maximum amplitude parameter 132'.

In another example of the integrated circuit 200, the second minimum filter circuit 126 is configured to: i) determining whether the second frequency signal 130 is less than a second predetermined threshold 134 during each bit period of a series of data frames, ii) modifying the second minimum amplitude parameter 136 during each bit period of a current data frame in which the second frequency signal 130 is less than the second predetermined threshold 134 to form a next second minimum amplitude parameter 136 'for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the second minimum amplitude parameter 136 to be equal to the next second minimum amplitude parameter 136' after counting the bit periods of the current data frame.

In yet another example of the integrated circuit 200, the second operational circuitry 128 is configured to: i) operate an updated second threshold for the second predetermined threshold 134 based on the second maximum amplitude parameter 132 and the second minimum amplitude parameter 136 after the current data frame, and ii) modify the second predetermined threshold 134 for the next data frame based on the updated second threshold.

Referring to fig. 3, another example of an integrated circuit 300 includes the digital filter circuit 112, the threshold calculation circuit 100, and the slicer circuit 138. The digital filter circuit 112 is configured to receive the S-FSK waveform 114 via the positive (+) and negative (-) input terminals, process the S-FSK waveform 114 to create the discrete frequency signal 110 and the second frequency signal 130, and provide the discrete frequency signal 110 and the second frequency signal 130 to the threshold calculation circuit 100. Various examples of threshold calculation circuit 100 are described above with reference to fig. 1. The slicer circuit 138 is configured to receive the discrete frequency signal 110 and the second frequency signal 130 from the digital filter circuit 112, receive the maximum amplitude parameter 116, the minimum amplitude parameter 120, the predetermined threshold 118, the second maximum amplitude parameter 132, the second minimum amplitude parameter 136, and the second predetermined threshold 134 from the threshold calculation circuit 100, generate a digital data stream 140 based on the received signals, parameters, and thresholds, and provide the digital data stream 140 at an output terminal. For example, the digital data stream 140 represents at least one of a digital logic level and a second digital logic level in a series of data frames that are modulated using S-FSK to form the S-FSK waveform 114.

Referring to fig. 4, another example of an integrated circuit 400 includes the digital filter circuit 112, the threshold calculation circuit 100, the slicer circuit 138, the correlator circuit 142, and the keep-alive circuit 144. Various examples of digital filter circuit 112 are described above with reference to fig. 3. Various examples of threshold calculation circuit 100 are described above with reference to fig. 1. Various examples of the limiter circuit 138 are described above with reference to fig. 3. The correlator circuit 142 is configured to receive the digital data stream 140 from the slicer circuit 138, decode the digital data stream 140 into codewords, correlate the codewords based on a predetermined protocol, and generate one or more intermediate control signals 146 based on the codewords and the predetermined protocol. The keep-alive circuit 144 is configured to receive one or more intermediate control signals 146 from the correlator circuit 142, process the one or more intermediate control signals 146 to generate one or more communication signals 148, and provide the one or more communication signals 148 at an output terminal. For example, one or more communication signals 148 may be used to communicate with the PV system to support rapid shutdown of one or more PV arrays in the PV system.

Referring to fig. 5, an example of a process 500 for calculating a threshold to distinguish digital data signals of an S-FSK waveform begins at 502, where a discrete frequency signal is received at a threshold calculation circuit from a digital filter circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal represents the digital logic levels in a series of data frames that are modulated using S-FSK to form an S-FSK waveform. Each data frame includes a significant portion and a zero energy portion. The significant portion comprises at least one data word and the zero energy portion comprises at least one zero energy word. Each data word and zero energy word comprises a plurality of bit periods. At 504, a maximum amplitude parameter is dynamically and selectively adjusted at a threshold calculation circuit during a bit period of a series of data frames. The adjustment is based on the discrete frequency signal and a predetermined threshold. Next, the minimum amplitude parameter is dynamically and selectively adjusted at the threshold calculation circuit during the bit period of a series of data frames (506). The adjustment is based on the discrete frequency signal and a predetermined threshold. At 508, a predetermined threshold for a next data frame is adapted after the current data frame based on the maximum amplitude parameter and the minimum amplitude parameter. In another example of process 500, the discrete frequency signal is a "mark" frequency signal having a bit period representing an "ON" logic level.

Reference is made to fig. 6, which is another example of the process 500 of fig. 5 for calculating a threshold to distinguish digital data signals of an S-FSK waveform. The example in fig. 6 includes additional features with respect to adjusting the maximum amplitude parameter at 504 in fig. 5. In this example, adjusting the maximum amplitude parameter includes determining whether the discrete frequency signal is greater than a predetermined threshold during each bit period of a series of data frames at 602. At 604, the maximum amplitude parameter is modified during each bit period of the current data frame in which the discrete frequency signal is greater than the predetermined threshold to form a next maximum amplitude parameter for a next data frame. At 606, each bit period of the current data frame is counted. At 608, after counting the bit periods of the current data frame, the maximum amplitude parameter is changed to be equal to the next maximum amplitude parameter.

In another example of process 500, the maximum amplitude parameter is modified according to the following equation:

where i is the current bit period, max amp param (i +1) is the next maximum amplitude parameter for the next bit period, discreterreq sig (i) is the discrete frequency signal for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and max amp param (i) is the maximum amplitude parameter for the current bit period.

In another example of process 500, the maximum amplitude parameter is changed according to the following equation:

max amp param(i+1)＝max amp param

where i is the current bit period, max amp param (i +1) is the next maximum amplitude parameter for the next bit period, and max amp param is the maximum amplitude parameter for the next data frame.

Fig. 7 shows another example of the process 500 of fig. 5. This example includes additional features with respect to adjusting the minimum amplitude parameter at 506 in fig. 5. In this example, adjusting the minimum amplitude parameter includes determining, at 702, whether the discrete frequency signal is less than a predetermined threshold during each bit period of a series of data frames. At 704, the minimum amplitude parameter is modified during each bit period of the current data frame in which the discrete frequency signal is less than the predetermined threshold to form a next minimum amplitude parameter for a next data frame. At 706, each bit period of the current data frame is counted. At 708, after counting the bit periods of the current data frame, the minimum amplitude parameter is changed to be equal to the next minimum amplitude parameter.

In yet another example of the process 500, the minimum amplitude parameter is modified according to the following equation:

where i is the current bit period, min amp param (i +1) is the next minimum amplitude parameter for the next bit period, discrete frequency sig (i) is the discrete frequency signal for the current bit period, m is less than twice the expected number of bit periods per data frame when the logic level is "ON", and min amp param (i) is the minimum amplitude parameter for the current bit period.

FIG. 7 shows another example of a process 500 in which the minimum amplitude parameter is varied according to the following equation:

min amp param(i+1)＝min amp param

where i is the current bit period, min amp param (i +1) is the next minimum amplitude parameter for the next bit period, and min amp param is the minimum amplitude parameter for the next data frame.

Fig. 8 shows another example of the process 500 of fig. 5. This example includes additional features regarding the adaptation of the predetermined threshold of fig. 5. In this example, adapting the predetermined threshold includes operating an updated threshold for the predetermined threshold based on the maximum amplitude parameter and the minimum amplitude parameter after the current data frame at 802. At 804, the predetermined threshold for the next data frame is modified based on the updated threshold.

In yet another example of process 500, the updated threshold is operated according to the following equation:

where updated thresh val is the updated threshold value operated after the current data frame, max ampparam is the maximum amplitude parameter after the current data frame, and min amp param is the minimum amplitude parameter after the current data frame.

In another example of process 800, the predetermined threshold is modified according to the following equation:

updated thresh val＝predetermined thresh

where updated threshold val is the updated threshold that is operated after the current data frame and predetermined threshold is the predetermined threshold for the next data frame.

Fig. 9 illustrates another example of the process 500 of fig. 5, which continues at 902 from adaptation of the predetermined threshold at 508 in fig. 5, where the second frequency signal is received at the threshold calculation circuit from the digital filter circuit. The second frequency signal is based on an S-FSK waveform received by the S-FSK receiver. The second frequency signal represents a second digital logic level in a series of data frames modulated using S-FSK to form an S-FSK waveform. At 904, a second maximum amplitude parameter is dynamically and selectively adjusted at the threshold calculation circuit during a bit period of a series of data frames. The adjustment is based on the second frequency signal and a second predetermined threshold. At 906, a second minimum amplitude parameter is dynamically and selectively adjusted at the threshold calculation circuit during a bit period of a series of data frames. The adjustment is based on the second frequency signal and a second predetermined threshold. At 908, a second predetermined threshold for a next data frame is adapted after the current data frame based on the second maximum amplitude parameter and the second minimum amplitude parameter. In yet another example of process 900, the second frequency signal is a "spatial" frequency signal having a bit period representing an "OFF" logic level.

In another example of process 500, the adjustment of the second maximum magnitude parameter at 904 includes: i) determining whether the second frequency signal is greater than a second predetermined threshold during each bit period of a series of data frames, ii) modifying the second maximum amplitude parameter during each bit period of a current data frame in which the second frequency signal is greater than the second predetermined threshold to form a next second maximum amplitude parameter for a next data frame, iii) counting each bit period of the current data frame, and iv) changing the second maximum amplitude parameter to be equal to the next second maximum amplitude parameter after counting the bit periods of the current data frame.

In yet another example of process 500, the adjusting of the second minimum magnitude parameter at 906 includes: i) determining whether the second frequency signal is less than a second predetermined threshold during each bit period of a series of data frames; ii) modifying the second minimum amplitude parameter during each bit period of the current data frame in which the second frequency signal is less than the second predetermined threshold to form a next second minimum amplitude parameter for the next data frame, iii) counting each bit period of the current data frame, and iv) changing the second minimum amplitude parameter to be equal to the next second minimum amplitude parameter after counting the bit periods of the current data frame.

In yet another example of the process 500, adapting 908 the second predetermined threshold includes: i) after the current data frame, operating an updated second threshold for a second predetermined threshold based on the second maximum amplitude parameter and the second minimum amplitude parameter, and ii) modifying the second predetermined threshold for a next data frame based on the updated second threshold.

The "SunSpec interoperability specification, fast shut-down communication signals, release 34" requires monitoring both the "marker" frequency signal and the "spatial" frequency signal to maintain tracking signal quality. For example, SINR is the average of ("ON" power) ("OFF" power). The specification also requires the use of a "quality threshold" that controls the demodulation behavior, and establishes a threshold (T) based on the current SINR in order to decide the value of the digital data bits. For example, T1/2 [ ("ON" power) average value- ("OFF" power) ] is used to establish a threshold between the "ON" and "OFF" values. The specification also requires a zero energy period, which may be considered in determining the SINR and the threshold (T).

Referring to fig. 12 and 13, an example of a process for operating the maximum, minimum and threshold values (T) for a given frequency signal considers the following:

RX output data at ith time increment (on specific tag/space output): rxout (i);

state of min/max filter at ith time increment: smin (i), smax (i); and

threshold value: sthr (i)

In this example, the threshold level is not fixed. The threshold is calculated based on the data itself during transmission at one of a plurality of frequencies and during quiescent periods. In each cycle, the minimum and maximum values are computed by tracking the received signal. The threshold value will then be updated for the next cycle based on the MIN and MAX values of the previous cycle.

With further reference to fig. 12, an example of a process 1200 for computing a maximum value for a given frequency signal begins by comparing rxout (i) of the frequency signal to sthr (i) of a threshold (1202). If Rxout (i) is greater than Sthr (i), then the process continues to 1204; otherwise, the process bypasses 1204 and continues to 1206. At 1204, the intermediate maximum value (Smax (I +1)) is set equal to Rxout (I)/m + (1-I/m) Smax (I) and the counter is set to 209. At 1206, the counter is decremented. Next, the counter is compared 1208 to zero (0). If the counter is greater than zero (0), the process continues to 1210; otherwise, the counter is zero (0) and the process continues to 1212. At 1210, the intermediate maximum value (Smax (i +1)) is set equal to Smax (i), and the process returns to 1202. At 1212, the intermediate maximum (Smax (i +1)) is set equal to (1-1/m) Smax (i) and the process returns to 1202.

With further reference to fig. 13, an example of a process 1300 for calculating a minimum value for a given frequency signal begins by comparing rxout (i) of the frequency signal to sthr (i) of a threshold (1302). If Rxout (i) is less than Sthr (i), then the process continues to 1304; otherwise, the process bypasses 1304 and continues to 1306. At 1304, the median minimum value (Smin (i +1)) is set equal to rxout (i)/m + (1-1/m) Smin (i) and the counter is set to 209. At 1306, the counter is decremented. Next, the counter is compared to zero (0) (1308). If the counter is greater than zero (0), the process continues to 1310; otherwise, the counter is zero (0) and the process continues to 1312. At 1310, the intermediate minimum value (Smin (i +1)) is set equal to Smin (i) and the process returns to 1302. At 1312, the intermediate minimum value (Smin (I +1)) is set equal to (sthr (I)/m +1-I/m) Smin (I) and the process returns to 1302.

Referring to fig. 14, an example of an S-FSK receiver architecture 1400 is shown for f_MFrequency signal sum f_SEach of the frequency signals implements the circuits of the flow diagrams of fig. 12 and 13. Front-end digital filter circuit 1042 will f_MFrequency signal sum f_SThe frequency signal is provided to a threshold calculation circuit 1404 and to a slicer and correlator 1406. The calculation circuit 1404 converts f_MFrequency signal sum f_SThe MAX, MIN and threshold (T)1408 values for both frequency signals are provided to the slicer and correlator 1406. Slicer and correlator 1406 may use the MAX value, MIN value, and threshold (T)1408 to determine f_MFrequency signal sum f_SThe value of a digital data bit in the frequency signal.

Various examples of the threshold calculation circuit 1404 describe a solution with a practical approach of low complexity for computing decision thresholds in FSK and OOK systems. The threshold does not require any a priori channel statistics or transmit/receive signal power levels. The threshold calculation is automatically adapted to the variations in channel/noise and transmit/receive signal power levels. The threshold calculation circuit 1404 avoids the use of Automatic Gain Control (AGC) techniques to adjust the signal power level. This reduces the complexity of the front-end digital filter circuit 1402 as well as the threshold calculation circuit 1404. Threshold calculation circuit 1404 operates with a dynamically varying signal amplitude and a dynamically varying SNR. The threshold calculation circuit 1404 processes periods of zero energy in the frequency signal by not adjusting the MIN value and the MAX value when the signal has zero energy, and thus does not adjust the threshold during the periods of zero energy.

The threshold calculation circuit 1404 allows the smart slicer 1406 to determine f based on an adaptive threshold calculation_MFrequency signal sum f_SThe value of a digital data bit in the frequency signal. In other words, the average of the threshold T-1/2 [ ("ON" power) ("OFF" power) may be adapted at each cycle (e.g., each S-FSK frame) using the threshold T dynamically computed by the threshold computation circuit 1404 and the MAX and MIN values parameter 1408]. For example, the threshold calculation circuit 1404 may be advantageous for implementation of a circuit designed to comply with "Sun Spec Interoperability Specification, Communication Signal for Rapid Shutdown, Version 34 ".

Referring again to fig. 11, according to the SunSpec interoperability specification, an S-FSK frame 1100 is composed of three words 1102 with 11 bit periods 1104 during the active portion 1106 and 16 words 1108 with 11 bit periods 1110 during the zero energy portion 1112. During the active portion 1106, each word 1114 includes approximately 50% +1 and approximately 50% -1. For example, five or six bits are +1, and six or five bits are-1. During the zero energy portion 1108, each word 1116 includes 11 bits that are all 0's.

On separate "marker" and "spatial" frequency signals, this means that per frame 1100:

3 x11x0.5-16 1; and is

(e.g., the number of 0 s is 12 times 1).

The threshold calculation circuit may update the threshold using an averaging filter obtained by setting t ═ m × TS, m ═ 2 k:

the threshold solution may take into account turning conditions such as large interferers on one or both channels, and sudden changes in received SNR. At the initial start of communication, the threshold value calculated by the threshold value calculation circuit may become stable for several S-FSK frames (for example, four to six frames) to reduce the startup time. In the case of 16 1's per frame, m is chosen to be no greater than 32, so as to be at about three time constants (which is 6 framesSeconds)) after which the threshold is stabilized. For example, the graph 1500 of fig. 15 shows the MAX parameter 1502, MIN parameter 1504, and threshold (T)1506 stable after six S-FSK frames 1508. An S-FSK frame is reflected in fig. 15 by an absolute value representation 1510 of the frequency signal during the active portion 1512 of the frameA peak occurs and decreases to a noise level during the zero energy portion 1514 of the frame. The threshold (T)1506 in fig. 15 is a curve that reaches 3000 to 3500 after four to six frames 1508.

During the extension period of zero, the threshold value remains (relatively) stable. This means that the filter will not react to the time constant during the zero period because it will last many time constants (e.g., 192/16-12 time constants) and the threshold will decay completely, forcing the subsequent frame to equate to a completely new start-up of the threshold calculation. Therefore, the threshold calculation circuit does not update the filter state when no upper/lower threshold samples appear on the corresponding frequency signal.

The threshold calculation circuit may include no updating of the filter states for the zero energy portion to simplify the algorithm for operating the MAX and MIN parameters and the threshold. In order to prepare for the first data bit in the active portion of the next S-FSK frame, the threshold calculation circuit may include a timeout associated with not updating the filter state. To accommodate signal amplitude variations, the non-updating filter period may be time limited. The hold may be limited to one frame. For example, if there are no updates for more than one frame duration (e.g., 209 samples), the hold may be released. This may be done for the MAX filter and MIN filter. If the blocker passes the Goertzel algorithm in the front-end digital filter circuit, it is possible that no other samples fall below the threshold, which would prevent the MIN filter from being updated unless a timeout is provided.

Modifications in the described examples are possible, and other examples are possible, within the scope of the claims. The various circuits described above may be implemented using any suitable combination of discrete components, integrated circuits, processors, memory, storage, and firmware.