Evaluation device for semiconductor device

文档序号:1256570 发布日期:2020-08-21 浏览:10次 中文

阅读说明:本技术 半导体装置的评价装置 (Evaluation device for semiconductor device ) 是由 大泷智久 水野贵之 平野辽 藤村彻 加藤茂彦 奈良安彦 大木克夫 影山晃 古森正明 于 2018-02-06 设计创作,主要内容包括:随着半导体器件的微细化而具有晶圆上的划线区域也减少的倾向。因此,划线区域所配置的TEG也需要减小,并且需要高效地配置供探针接触用的电极焊垫。因此,需要使电极焊垫的高效布局与探针对应。本发明的目的是提供一种使容易进行电气特性评价的TEG的电极焊垫的布局、与探针对应的技术。在本发明的半导体装置的评价装置中,通过具备呈扇状排列的多个探针、或者以MEMS(Micro Electro Mechanical Systems:微机电系统)技术制造的探针来解决上述的课题。(With the miniaturization of semiconductor devices, the scribe line area on the wafer tends to decrease. Therefore, the TEG disposed in the scribe line region also needs to be reduced, and an electrode pad for probe contact needs to be disposed efficiently. Therefore, it is required to make efficient layout of the electrode pads correspond to the probes. The purpose of the present invention is to provide a technique for adapting the layout of electrode pads of a TEG and probes, which facilitates the evaluation of electrical characteristics. The evaluation device for a semiconductor device of the present invention includes a plurality of probes arranged in a fan shape or a probe manufactured by a Micro Electro Mechanical Systems (MEMS) technology, thereby solving the above-described problems.)

1. An evaluation apparatus for a semiconductor device, comprising:

an electron source; and

a plurality of probes are arranged on the base plate,

the plurality of probes are arranged in a fan shape.

2. The evaluation apparatus of a semiconductor device according to claim 1,

there are four such probes.

3. The evaluation apparatus of a semiconductor device according to claim 2,

the front ends of the four probes are arranged in a fan shape.

4. The evaluation apparatus of a semiconductor device according to claim 1,

a plurality of the probes are tungsten probes.

5. The evaluation apparatus of a semiconductor device according to claim 1,

having a sample holder for holding a sample to be tested,

the sample holder fixes a semiconductor wafer by electrostatic clamping.

6. An evaluation apparatus for a semiconductor device, characterized in that,

comprises an electron source and a probe,

the probe has on one side of the cantilever: a protrusion having a first metal face; and a first wiring connected to the first metal surface,

and the probe has a conductive layer on the other side of the cantilever.

7. The evaluation apparatus for a semiconductor device according to claim 6,

the protrusion has: a second metal face electrically separated from the first metal face; and a second wiring connected to the second metal surface.

8. The evaluation apparatus for a semiconductor device according to claim 7,

the first metal surface and the second metal surface are in contact with an electrode pad.

9. The evaluation apparatus for a semiconductor device according to claim 7,

the protrusion has: a third metal surface electrically separated from the first metal surface and the second metal surface; and a third wiring connected to the third metal surface.

10. The evaluation apparatus for a semiconductor device according to claim 6,

a piezoresistive element is formed in the cantilever.

11. The evaluation apparatus for a semiconductor device according to claim 6,

the metal is tungsten.

12. The evaluation apparatus for a semiconductor device according to claim 6,

having a sample holder for holding a sample to be tested,

the sample holder fixes a semiconductor wafer by electrostatic clamping.

Technical Field

The present invention relates to the manufacture of semiconductor devices.

Background

In the manufacture of semiconductor devices, a technology for managing manufacturing processes is important to improve the yield and yield of products. Some inspection apparatuses for process control perform electrical characteristic evaluation by directly contacting a probe with a sample.

Patent document 1 discloses a technique of: by measuring a plurality of Test Element groups (hereinafter referred to as TEGs) for evaluation arranged in a scribe region of a semiconductor wafer, the yield of semiconductor devices can be improved. Patent document 2 discloses a technique of: the probe coarse image acquiring apparatus is provided with a sample exchange chamber connected to the sample chamber and temporarily storing a sample, and a transport unit for transporting the sample between the sample exchange chamber and the sample chamber, and the probe coarse image acquiring apparatus and the electron optical system apparatus are arranged in parallel, and the sample stage and the probe unit are moved in the horizontal direction between a position in the vertical direction of the probe coarse image acquiring apparatus and a position in the vertical direction of the electron optical system apparatus. Patent document 3 discloses a semiconductor inspection apparatus including: a charged particle optical system device for irradiating a sample wafer with a charged particle beam; a sample stage that freely moves in the sample chamber; a probe stage on which a probe provided with a probe is mounted and which moves freely in the sample chamber; a coarse image acquisition component that acquires an optical image of the sample wafer as the position of the probe is coarsely approached; a charged particle image acquisition unit that acquires a charged particle image based on a detection signal of secondary charged particles emitted from a sample wafer when the charged particle beam is irradiated while being scanned; a current/voltage detection unit for detecting a current or voltage obtained from the probe; and a control computer.

Disclosure of Invention

Problems to be solved by the invention

With the miniaturization of semiconductor devices, the scribe line area on the wafer tends to be reduced. Therefore, the TEG disposed in the scribe line region also needs to be reduced, and an electrode pad for probe contact needs to be efficiently disposed. Therefore, it is required to correspond the probes to the effective layout of the electrode pads. In the techniques disclosed in patent documents 1 to 3, since the probes are mounted independently, it takes time to control the contact between the probes and the electrode pads.

The purpose of the present invention is to provide a technique for matching the layout of electrode pads of a TEG, which is easy to evaluate electrical characteristics, with probes.

Means for solving the problems

The evaluation device for a semiconductor device of the present invention includes a plurality of probes arranged in a fan shape or a probe manufactured by a Micro Electro Mechanical Systems (MEMS) technology, thereby solving the above-described problems.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, the layout of the electrode pads of the TEG, which is easy to evaluate the electrical characteristics, can be made to correspond to the probes. Further, productivity of a pre-process of manufacturing a semiconductor device can be improved.

Drawings

Fig. 1 is a schematic diagram of an electrical characteristic evaluation device according to an embodiment of the present invention.

FIG. 2 is a schematic view of a probe module according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a semiconductor wafer of a sample.

Fig. 4(a) is a diagram showing an example of arrangement of the electrode pads of fetpeg in the scribe line region.

Fig. 4(b) is a diagram showing an example of arrangement of electrode pads of the minute fetpeg on the scribe line region.

Fig. 5 is a diagram showing an example of arrangement of the probe modules.

Fig. 6(a) is a diagram showing an example of arrangement of the electrode pads of fetpeg in the scribe line region.

Fig. 6(b) is a diagram showing a modification of the arrangement of the electrode pads of fetpeg in the scribe line region.

Fig. 6(c) is a diagram showing a modification of the arrangement of the electrode pads of fetpeg in the scribe line region.

Fig. 7(a) is a perspective view schematically showing a probe module with MEMS probes mounted thereon according to an embodiment of the present invention.

Fig. 7(b) is a plan view schematically showing a probe module with MEMS probes mounted thereon according to an embodiment of the present invention.

Fig. 8(a) is a perspective view of the probe cassette according to the embodiment of the present invention, the side opposite to the side facing the sample.

Fig. 8(b) is a perspective view of the sample-facing side of the probe cassette according to the embodiment of the present invention.

Fig. 8(c) is a perspective view of the sample-facing side of the probe cassette according to the embodiment of the present invention.

FIG. 9 is an overall perspective view of a MEMS probe of an embodiment of the present invention.

FIG. 10 is a perspective view of a cantilever of a MEMS probe in accordance with an embodiment of the present invention.

FIG. 11 is a top view of a MEMS probe in accordance with an embodiment of the invention.

FIG. 12 is a cross-sectional view of a MEMS probe in accordance with an embodiment of the invention.

FIG. 13 is a flow chart of the fabrication of a MEMS probe according to an embodiment of the present invention.

Fig. 14(a) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(b) is a diagram illustrating a manufacturing process of the MEMS probe according to the embodiment of the present invention.

Fig. 14(c) is a diagram illustrating a manufacturing process of the MEMS probe according to the embodiment of the present invention.

Fig. 14(d) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(e) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(f) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(g) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(h) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(i) is a diagram illustrating a manufacturing process of a MEMS probe according to an embodiment of the present invention.

Fig. 14(j) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 14(k) is a diagram illustrating a manufacturing process of the MEMS probe according to the embodiment of the present invention.

Fig. 14(l) is a diagram illustrating a manufacturing process of the MEMS probe according to the embodiment of the present invention.

Fig. 14(m) is a diagram illustrating a manufacturing process of the MEMS probe according to the embodiment of the present invention.

FIG. 15 is a top view of a MEMS probe of an embodiment of the invention.

FIG. 16 is a top view of a MEMS probe in accordance with an embodiment of the invention.

FIG. 17 is a top view of a MEMS probe of an embodiment of the invention.

FIG. 18 is a top view of a MEMS probe of an embodiment of the invention.

FIG. 19 is a perspective view of a cantilever of a MEMS probe in accordance with an embodiment of the present invention.

FIG. 20 is a perspective view of a cantilever of a MEMS probe in accordance with an embodiment of the present invention.

FIG. 21 is a cross-sectional view of a MEMS probe of an embodiment of the invention.

FIG. 22 is an overall perspective view of a MEMS probe of an embodiment of the invention.

FIG. 23 is a top view of a MEMS probe of an embodiment of the invention.

FIG. 24 is a cross-sectional view of a MEMS probe in accordance with an embodiment of the invention.

FIG. 25 is a cross-sectional view of a MEMS probe of an embodiment of the invention.

FIG. 26 is a flow chart of the fabrication of a MEMS probe according to an embodiment of the present invention.

Fig. 27(a) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(b) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(c) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(d) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(e) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(f) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(g) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 27(h) is a diagram illustrating a process for manufacturing a MEMS probe according to an embodiment of the present invention.

Fig. 28(a) is a schematic view showing a state where a probe is in contact with an electrode pad of a TEG.

Fig. 28(b) is a schematic view showing a state where the probe is in contact with the electrode pad of the TEG.

Fig. 29(a) is a diagram showing an example of arrangement of FETTEG in the scribe line region.

Fig. 29(b) is a diagram showing an example of arrangement of FETTEG in the scribe line region.

Fig. 30 is a schematic view of an example of an electrode pad for confirming the normality of each probe of a probe cassette.

Fig. 31 is a diagram showing an example of a flowchart for evaluating electrical characteristics using a probe cassette.

Fig. 32(a) is a diagram showing an example of measuring electrical characteristics by irradiation with a charged particle beam.

Fig. 32(b) is a diagram showing an example of measuring electrical characteristics in a state where the charged particle beam is not irradiated.

Fig. 33 is a diagram showing an example of an absorption current image.

Fig. 34 is a diagram showing an example of a pre-process flow in a semiconductor device manufacturing process.

Fig. 35 is a view showing an example of a manufacturing process of a semiconductor device of the present invention.

Detailed Description

In the following embodiments, the description will be made by dividing the embodiments into a plurality of sections or embodiments as necessary for convenience, but unless otherwise stated explicitly, they are not independent of each other, and have a relationship of some or all of modifications, details, supplementary descriptions, and the like, one of which is the other. In the drawings for describing the embodiments below, the same reference numerals are given to the same functional elements in principle, and redundant description is omitted. Embodiments of the present invention will be described in detail below with reference to the drawings.

52页详细技术资料下载
上一篇:一种医用注射器针头装配设备
下一篇:硅层的评价方法和硅外延晶片的制造方法

网友询问留言

已有0条留言

还没有人留言评论。精彩留言会获得点赞!

精彩留言,会给你点赞!

技术分类