阅读说明：本技术 多电平升压转换器 (Multi-level boost converter ) 是由 於波 占金祥 傅电波 于 2019-01-04 设计创作，主要内容包括：一种直流-直流转换器使用多电平升压转换器拓扑。除了将输入电压(107)通过与一对二极管(141,142)串联的升压电感器(112)连接到输出节点外,桥式电路在飞跨电容器(151)的一侧上生成多电平波形,所述飞跨电容器的另一侧连接在所述串联的二极管(141,142)之间。在所述输出节点发生异常的情况下,所述升压转换器拓扑在其组件上保持低电压应力,并允许对所述飞跨电容器(151)进行简单的预充电。(A dc-dc converter uses a multi-level boost converter topology. In addition to connecting the input voltage (107) to the output node through a boost inductor (112) in series with a pair of diodes (141, 142), the bridge circuit generates a multi-level waveform on one side of a flying capacitor (151) whose other side is connected between the series-connected diodes (141, 142). In the event of an anomaly at the output node, the boost converter topology maintains low voltage stress on its components and allows for simple pre-charging of the flying capacitor (151).)

1. A dc-dc voltage converter, comprising:

an input voltage node for receiving an input voltage;

an output voltage node for providing an output voltage;

an inductor connected between the input node and the output node;

a first diode and a second diode connected in series between the inductor and the output node for causing current to flow from the inductor to the output voltage node;

a first capacitor having a first plate and a second plate, wherein the first plate is connected to a node between the first diode and the second diode, and the second plate is connected to an internal node;

a third diode connected between the internal node and an intermediate voltage node for passing current from the internal node to the intermediate voltage node;

a first switch connected between the internal node and a node between the inductor and the second and third diodes;

a second switch connected between the internal node and ground, wherein the first switch and the second switch are configured to generate a multi-level waveform on the internal node.

2. The dc-dc converter according to claim 1, further comprising:

a fourth diode connected in parallel with the first diode and the second diode between the inductor and the output node for causing current to flow from the inductor to the output voltage node.

3. The dc-dc converter according to claim 1 or 2, further comprising:

a third switch for connecting the second plate of the first capacitor to the internal node.

4. The dc-dc converter according to claim 1, further comprising:

a second capacitor connected between the output node and the intermediate voltage node;

a third capacitor connected between the intermediate voltage node and ground.

5. The DC-DC converter according to any of claims 1 to 4, wherein the first switch and the second switch are NMOS transistors.

6. The DC-DC converter according to any one of claims 1 to 5, further comprising:

a control circuit to provide first and second non-overlapping control waveforms to the first and second switches, respectively.

7. The dc-dc converter of claim 6, wherein the control circuit is further configured to receive the output voltage, and to vary duty cycles of the first and second control waveforms to adjust a level of the output voltage.

8. The dc-dc converter according to claim 6, further comprising:

a third switch to connect the second plate of the first capacitor to the internal node, wherein the control circuit is to turn on the third switch while providing the first and second switches with the first and second non-overlapping control waveforms.

9. The dc-dc converter according to claim 8, wherein the control circuit is further configured to perform a precharge operation, wherein the precharge operation comprises simultaneously turning off the first switch, the second switch, and the third switch.

10. A dc-dc voltage conversion system, comprising:

a dc-dc conversion circuit comprising:

an inductor connected between an input node and an output node;

a first diode and a second diode connected in series between the inductor and the output node for causing current to flow from the inductor to the output node;

a bridge circuit connected between a node connecting the inductor to the first diode and the second diode and ground, wherein the bridge circuit is configured to generate a multi-level waveform on an internal node;

a capacitor having a first plate and a second plate, wherein the first plate is connected to a node between the first diode and the second diode, and the second plate is connected to the internal node;

a third diode connected between the internal node and an intermediate voltage node for passing current from the internal node to the intermediate voltage node;

a control circuit coupled to the bridge circuit, wherein the control circuit is configured to provide a first non-overlapping control waveform and a second non-overlapping control waveform to the bridge circuit to generate an output voltage at the output node from an input voltage at the input node.

11. The dc-dc voltage conversion system according to claim 10, wherein the bridge circuit comprises:

a first switch connected between the internal node and the node connecting the inductor to the first diode and the second diode for receiving a first control waveform;

a second switch connected between the internal node and ground for receiving a second control waveform.

12. The dc-dc voltage conversion system according to claim 10 or 11, wherein the dc-dc conversion circuit further comprises:

a fourth diode connected in parallel with the first and second diodes between the inductor and the output node for causing current to flow from the inductor to the output node.

13. The dc-dc voltage conversion system according to any of claims 10-12, wherein the control circuit is further configured to receive the output voltage, and to vary duty cycles of the first and second control waveforms to adjust a level of the output voltage.

14. The dc-dc voltage conversion system according to claim 10, wherein the dc-dc conversion circuit further comprises:

a third switch to connect the second plate of the capacitor to the internal node, wherein the control circuit is to turn on the third switch while providing the first and second switches with the first and second non-overlapping control waveforms.

15. The dc-dc voltage conversion system of claim 14, wherein the control circuit is further configured to perform a precharge operation, wherein the precharge operation comprises simultaneously opening the first switch, the second switch, and the third switch.

16. A method, comprising:

receiving an input voltage at an input node;

generating an output voltage at an output node from the input voltage, wherein generating the output voltage comprises:

generating a first non-overlapping control waveform and a second non-overlapping control waveform;

applying the first non-overlapping waveform and the second non-overlapping waveform to a bridge circuit;

the bridge circuit generates multi-state waveforms from the first non-overlapping waveform and the second non-overlapping waveform at an internal node of a dc-to-dc voltage converter, wherein the dc-to-dc voltage converter includes:

an inductor connected between the input node and the output node;

a first diode and a second diode connected in series between the inductor and the output node for causing current to flow from the inductor to the output voltage node;

a first capacitor having a first plate and a second plate, wherein the first plate is connected to a node between the first diode and the second diode, and the second plate is connected to the internal node;

a third diode connected between the internal node and an intermediate voltage node for passing current from the internal node to the intermediate voltage node, wherein,

the bridge circuit is connected between a node connecting the inductor to the first diode and the second diode and ground.

17. The method of claim 16, wherein generating the output voltage at the output node further comprises:

varying duty cycles of the first non-overlapping control waveform and the second non-overlapping control waveform to regulate the output voltage.

18. The method of claim 16, wherein the bridge circuit comprises: a first switch connected between the internal node and the node connecting the inductor to the first diode and the second diode for receiving the first control waveform; a second switch connected between the internal node and ground for receiving the second control waveform.

19. The method of claim 18, wherein the dc-to-dc voltage converter further comprises a third switch for connecting the second plate of the capacitor to the internal node, and wherein the method further comprises:

performing a precharge operation prior to generating the output voltage at the output node, wherein the precharge operation comprises:

receiving the input voltage at the input node while turning off the first switch, the second switch, and the third switch.

20. The method of claim 19, wherein generating the output voltage at the output node further comprises: turning on the third switch.

Technical Field

The present application relates generally to the field of dc-dc converters, and more particularly to boost converters.

Prior Art

This application claims benefit of U.S. provisional application No. 15/863,002 entitled "Multi-level boost converter" filed on 5.1.2018, which is hereby incorporated by reference.

Disclosure of Invention

According to one aspect of the invention, an apparatus is provided that includes a dc-to-dc voltage converter. The dc-dc voltage converter has an input voltage node for receiving an input voltage, an output voltage node for providing an output voltage, and an inductor connected between the input node and the output node. A first diode and a second diode are connected in series between the inductor and the output node for causing current to flow from the inductor to the output voltage node. A first capacitor has a first plate connected to a node between the first diode and the second diode and a second plate connected to an internal node. A third diode is connected between the internal node and an intermediate voltage node for causing current to flow from the internal node to the intermediate voltage node. A first switch is connected between the internal node and a node between the inductor and the second and third diodes. A second switch is connected between the internal node and ground, wherein the first switch and the second switch are configured to generate a multi-level waveform on the internal node.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes a fourth diode connected in parallel with the first and second diodes between the inductor and the output node for causing current to flow from the inductor to the output voltage node.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes a third switch for connecting the second plate of the first capacitor to the internal node.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes: a second capacitor connected between the output node and the intermediate voltage node; a third capacitor connected between the intermediate voltage node and ground.

Optionally, in other embodiments of the foregoing aspect, the first switch and the second switch are NMOS transistors.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes: a control circuit to provide first and second non-overlapping control waveforms to the first and second switches, respectively.

Optionally, in another embodiment of the foregoing aspect, the control circuit is further configured to receive the output voltage, and to change duty cycles of the first control waveform and the second control waveform, thereby adjusting a level of the output voltage.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes: a third switch to connect the second plate of the first capacitor to the internal node, wherein the control circuit is to turn on the third switch while providing the first and second switches with the first and second non-overlapping control waveforms.

Optionally, in another implementation of the foregoing aspect, the control circuit is further configured to perform a precharge operation, wherein the precharge operation includes opening the first switch, the second switch, and the third switch simultaneously.

According to another aspect of the present invention, a system is provided that includes a dc-to-dc voltage conversion system. The DC-DC voltage conversion system comprises a DC-DC conversion circuit and a control circuit. The DC-DC conversion circuit includes: an inductor connected between an input node and an output node; a first diode and a second diode connected in series between the inductor and the output node for causing current to flow from the inductor to the output node. A bridge circuit is connected between a node connecting the inductor to the first diode and the second diode and ground, wherein the bridge circuit is configured to generate a multi-level waveform on an internal node. The dc-dc conversion circuit further includes: a capacitor having a first plate and a second plate, wherein the first plate is connected to a node between the first diode and the second diode, and the second plate is connected to the internal node. A third diode is connected between the internal node and an intermediate voltage node for causing current to flow from the internal node to the intermediate voltage node. The control circuit is coupled to the bridge circuit for providing the bridge circuit with a first non-overlapping control waveform and a second non-overlapping control waveform to generate an output voltage at the output node from an input voltage at the input node.

Optionally, in another embodiment of the foregoing aspect, the bridge circuit includes a first switch and a second switch. The first switch is connected between the internal node and the node connecting the inductor to the first diode and the second diode for receiving a first control waveform. The second switch is connected between the internal node and ground for receiving a second control waveform.

Optionally, in another embodiment of the foregoing aspect, the dc-dc converter further includes: a fourth diode connected in parallel with the first and second diodes between the inductor and the output node for causing current to flow from the inductor to the output node.

Optionally, in another embodiment of the foregoing aspect, the control circuit is further configured to receive the output voltage, and to change duty cycles of the first control waveform and the second control waveform, thereby adjusting a level of the output voltage.

Optionally, in another implementation of the foregoing aspect, the control circuit is further configured to perform a precharge operation, wherein the precharge operation includes opening the first switch, the second switch, and the third switch simultaneously.

According to another aspect of the invention, there is provided a method comprising: receiving an input voltage at an input node; an output voltage is generated at an output node from the input voltage. Generating the output voltage includes: generating a first non-overlapping control waveform and a second non-overlapping control waveform; applying the first non-overlapping waveform and the second non-overlapping waveform to the bridge circuit; the bridge circuit generates multi-state waveforms from the first non-overlapping waveform and the second non-overlapping waveform at an internal node of the dc-to-dc voltage converter. The DC-DC voltage converter includes: an inductor connected between the input node and the output node; a first diode and a second diode connected in series between the inductor and the output node for causing current to flow from the inductor to the output voltage node; a first capacitor having a first plate and a second plate, wherein the first plate is connected between the first diode and the second diode, and the second plate is connected to the internal node; a third diode connected between the internal node and an intermediate voltage node for flowing current from the internal node to the intermediate voltage node, wherein the bridge circuit is connected between a node connecting the inductor to the first and second diodes and ground.

Optionally, in another embodiment of the foregoing aspect, generating the output voltage at the output node further comprises: varying duty cycles of the first non-overlapping control waveform and the second non-overlapping control waveform to regulate the output voltage.

Optionally, in another embodiment of the foregoing aspect, the bridge circuit includes a first switch and a second switch. The first switch is connected between the internal node and the node connecting the inductor to the first diode and the second diode for receiving a first control waveform. The second switch is connected between the internal node and ground for receiving a second control waveform.

Optionally, in another embodiment of the foregoing aspect, the dc-dc voltage converter further includes: a third switch for connecting the second plate of the capacitor to the internal node. Performing a precharge operation prior to generating an output voltage at the output node, wherein the precharge operation comprises: receiving an input voltage at the input node while turning off the first switch, the second switch, and the third switch.

Optionally, in another embodiment of the foregoing aspect, generating an output voltage at the output node further comprises: turning on the third switch.

Drawings

Fig. 1 shows a prior art example of a boost converter.

FIG. 2A presents one embodiment of a multi-level boost converter circuit.

Fig. 2B illustrates an embodiment of a dc-to-dc converter system including a multi-level boost converter circuit such as that shown in fig. 2A.

Fig. 2C is a block diagram of a control circuit block that provides switching waveforms for the dc-dc converter system of fig. 2B.

Fig. 2D shows a set of waveforms for a dc-dc conversion system 2B having the multi-state boost converter of fig. 2A.

Fig. 2E and 2F show a high voltage NMOS device and a high voltage insulated gate bipolar transistor, respectively, that may be used for the switch of fig. 2A.

Fig. 3A to 3D show the multi-level boost converter of fig. 2A at respective stages a to D of fig. 2D.

Fig. 4A and 4B illustrate voltage clamping behavior of the multi-level boost converter of fig. 2A in response to abnormal grid interaction.

Fig. 5 illustrates a precharge operation in fig. 2A.

Fig. 6A presents another embodiment of a multi-level boost converter circuit.

Fig. 6B to 6D correspond to fig. 3B, 4B and 5, respectively, but this is for the embodiment of fig. 6A and not for the embodiment of fig. 3A.

Fig. 7 is a flowchart illustrating an operation of the multi-level boost converter in fig. 2A or 6A.

Detailed Description

Examples of boost converters with multilevel operation are presented below, which place components at lower stress voltages and allow the use of smaller boost inductors. The boost inductor is connected to the output through a pair of diodes in series, with the flying capacitor connected between the diodes on one side and the bridge circuit generated multi-state waveform on the internal node on the other side. The internal node is connected to the capacitive divider through a diode to protect the circuit from voltage surges on the output node. The boost converter includes a pre-charge path for the flying capacitor. Another diode in parallel with the series diode is connected in parallel to reduce conduction losses.

The presented embodiments of a multi-level boost converter may be used over a wide range of voltage levels, including high voltage levels. For example, they may be applied to power supply systems that require a stable output voltage level, where the input voltage comes from a photovoltaic converter of a solar power supply system, ranging from 200 volts to 1000 volts, and is output to a grid of 480 volts to 1200 volts. Other examples may include battery charging circuits having input and output voltages that may take on values in the hundreds of voltage ranges, such as battery chargers for electric vehicles. These applications are by way of example only. It should be understood that the multilevel hybrid converter of the present technology may be used in other applications.

Fig. 2A presents one embodiment of a multi-level boost converter circuit 100. In the example of the multi-level boost converter circuit 100, the input voltage source Vin 107 is connected at ground (or, more generally, the lower bus voltage level V)_bus-) and boost inductor L112. Boost inductor L112 is connected to upper bus voltage level V by a pair of series connected diodes D1141 and D2142_bus+An output node of (c). Diodes D1141 and D2142 are used to pass current from inductor L112 to V_bus+And (4) nodes. The load is represented by R109 and is connected to V_bus+And V_bus-In the meantime. For example, the input voltage may be a photovoltaic converter at 200V, V_bus+And V_bus-Is the high line and the ground line of the power grid at 480V.

Flying capacitor C_fly151 has one plate connected to the node between diodes D1141 and D2142, the second plate of which is connected to internal node X. One side of the internal node X is connected to the capacitor C_bus+152 and C_bus-153 and the other side is connected between switches T1131 and T2132. Capacitor C_bus+152 and C_bus-153 are connected in series at V_bus+And V_bus-In between, a capacitive voltage divider is formed. In one set of embodiments, assume capacitor C_bus+152 and C_bus-153 have the same capacitance, capacitor C_bus+152 and C_bus-The level at the node between 153 is 1/2V_bus+The following steps.

The bridge circuit including switches T1131 and T2132 is connected between boost inductor L112 and series diodes D1141 and D2142 on one side and to ground on the other side. A bridge circuit may be used to generate a multi-level waveform on node X when switch S133 is closed. (switch S133 will be discussed further below in connection with precharging.) according to this embodiment, the switches T1131, T2132, and S133 may be implemented as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), bipolar junction transistors (bipolar transistors or BJTs), or other actively controlled power semiconductors. For example, FIG. 2E shows a high voltage NMOS device, and FIG. 2F shows a high voltage IGBT, which may be used forT1131, T2132 and S133, wherein the diode shown is an intrinsic body diode of the device, rather than a separate element. Control voltage V of the device_TApplied to the control gate of the device and corresponding to V for T1131, T2132 and S133 respectively_T1、V_T2And V_s。

When switch T1131 is on (closed) and switch T2132 is off (open), node X will be at V_inThe following steps. When switch T1131 is open (open) but switch T2132 is conductive (closed), node X will be at ground voltage. When switches T1131 and T2132 are both open, node X will be at 1/2V_bus+The following steps. This results in a multi-level waveform on node X. The switches T1131 and T2132 have non-overlapping control waveforms so that the switches T1131 and T2132 do not conduct simultaneously. Thus, elements L112, D1141, D2142, T1131, and T2132 need not support V_inOr V_bus+Such that these elements have a lower voltage stress level than the elements of the topology shown in fig. 1. For example, the voltage of T2132 is not greater than 1/2V_bus+. A smaller size boost inductor L112 and smaller, cheaper devices may be used since other components may have lower voltages.

An embodiment of a multi-level boost converter may include switch S133. Through the switch, C_flyThe plate at node X of 151 is connected to the node between switches T1131 and T2132. During normal operation, when V is generated from Vin 107_bus+When S133 is closed (on), but can be opened (off), so that C is passed_fly151 provide a precharge path to improve the start-up operation without introducing additional precharge circuitry, as further described in fig. 5.

Embodiments of the multi-level boost converter may also include a diode D3143. Through the diode, C at node X_fly151 is connected to C_bus+152 and C_bus-153, respectively, is the middle node of the capacitive divider. This may help to prevent V_bus+To the voltage surge of C_fly151. For example, if V_bus+And V_bus-For high and low lines of the grid, then the inclusion of D3143 may help to prevent thisComponent damage caused by transmission of power-like surges back to the boost converter 100, as further described in fig. 4A and 4B.

Embodiments of the multi-level boost converter may also include a diode D4144 in parallel with the series-connected diodes D1141 and D2142. Diode D4144 provides the voltage from boost inductor 112 to supply V_bus+The output node of (a). The additional path through D4144 has lower conduction loss than the paths through D1141 and D2142, as further discussed in fig. 3A-3D. Other embodiments may not include a path with diode D4144, as described below with respect to fig. 6A-6D.

Fig. 2B illustrates an embodiment of a dc-dc converter system 180. The dc-dc converter system includes a control block 190 and a multi-level boost converter circuit 100, as shown in fig. 2A. The converter 100 is connected to a voltage source V_in107 and generates an output voltage V_bus+The output voltage may be connected to drive a resistive load R109. Multi-level boost converter 100 is connected to receive a set of control signals from control block 190. The control signal may be used to regulate the output voltage V_bus+. The circuit of the control block 190 may be connected to receive the output voltage V_bus+And in some embodiments receives the input voltage Vin, based on its level or based on V_bus+Output level V is adjusted by ratio of/Vin_bus+. For example, control block 190 may be adjusted based on user input to generate a control signal for the multi-level boost converter to adjust the output voltage level.

Fig. 2C is a block diagram of an embodiment of a control circuit block 190 for providing switching waveforms to control switches T1131, T2132, and S133 of dc-dc converter system 180 in fig. 2B. According to this embodiment, the control circuit may be implemented by hardware, software, firmware, or a combination thereof. In some embodiments, switches T1131, T2132, and S133 may be implemented as: a MOSFET, as shown for the NMOS device in FIG. 2E; an Insulated Gate Bipolar Transistor (IGBT), as shown in fig. 2F; a bipolar junction transistor (bipolar transistor or BJT); or other actively controlled power semiconductors. Will control signal waveform V_T1、V_T2And V_SA control gate for a corresponding switch, as shown in fig. 2E or fig. 2F. In generating V_bus+If V of the controller signal during operation_SHigh, S133 is on and V of the controller signal_T1And V_T2Is a non-overlapping waveform, thereby generating a multi-level waveform and V on a node X_bus+. During the precharge mode, if V_T1And V_T2Lower, T1131 and T2132 are disconnected, and if V is_SLow, S133 is open, as discussed further below in fig. 5.

Fig. 2D shows a set of waveforms for a dc-dc conversion system 2B having the multi-state boost converter of fig. 2A. The top is a set of control waveforms V_T1And V_T2As generated by control circuit 190 in fig. 2C according to one set of embodiments. V_T1And V_T2Is a non-overlapping waveform having a period T, where V is shown in the figure_T1Higher in the first half cycle, and V_T2Higher in the second half cycle. In this example, V_T1And V_T2Are all symmetrical with the same duty cycle DT. During operation, when V is generated from Vin_bus+When the switch S133 is on, and V_SAnd correspondingly higher, but not shown in fig. 2D. V_T1And V_T2Below the control waveform is the current i through boost inductor L112_LAnd a voltage V generated by a bridge circuit of T1131, T2132 at the internal node X_X. The different phases a, b, c, d are marked at the bottom and correspond respectively to: v_T1Higher but V_T2The lower the cost; v_T1And V_T2Are all low; v_T1Lower but V_T2Higher; v_T1And V_T2Are all low. The configuration of the multi-level boost converter in fig. 2A at these stages a, b, c and D is shown in fig. 3A to 3D, respectively.

Fig. 3A to 3D show the booster circuit of the embodiment of fig. 2A, wherein the switches T1131 and T2132 are configured according to the control signals of the control circuit of fig. 2C at stages a to D of fig. 2D, respectively. In fig. 3A to 3D and fig. 4A, 4B and 5, the more closely related circuit paths are represented by larger line weights.

Fig. 3A corresponds to phase a of fig. 2D, in which switch T1131 is closed and switch T2132 is open. Current i through L112_LContinues to rise and flows through T1131 to internal node X. Node X is at Vin and the main current flows through D2142 to V_bus+And (c) a lower output node. Fig. 3B corresponds to phase B of fig. 2D, in which both switches T1131 and T2132 are open. Node X is at 1/2V_bus+The following steps. Current i_LFlow continues through L112 but tapers off and can flow through diodes D1141 and D2142 in series or through diode D4144 in parallel with D1141 and D2142. The path through the single diode D4144 will have a lower voltage drop and is from i_LThe main current path to the load. Thus, including a single diode path through D4144 reduces conduction losses.

Fig. 3C corresponds to phase C of fig. 2D, in which switch T1131 is open and switch T2132 is closed. Node X is thus connected to V_bus-The wires are connected to ground. Current i_LRise again and current flows through D1141 to pair C_fly151 are charged. FIG. 3D corresponds to stage D of FIG. 2D, where switches T1131 and T2132 are both open again and node X is at 1/2V_bus+The following steps. As shown in fig. 3B, the main current again passes through the single diode D4144, reducing conduction losses. The system then returns to stage a, causing node X to rise back to Vin.

The control circuit may regulate the output V by varying the duty cycle D, the period T, or both_bus+. When aiming at V_T1And V_T2Is increased to 50%, V_bus+Becomes Vin. With decreasing duty cycle, V_bus+Increased, but lower current. Thus, the control circuit 190 of fig. 2B and 2C may regulate the output of the boost converter, where V is according to this embodiment_bus+The level may be adjusted based on user input or automatically adjusted.

FIGS. 4A and 4B illustrate the multi-level boost converter response V of FIG. 2A_bus+Voltage clamping behavior of the voltage surge at the output node. For example, if the circuit of FIG. 2B is used to power a power grid and the grid spikes due to lightning strikes or other accidents, feedback may be providedInto the components of the converter and damage the circuit. Without diode D3143, if V_bus+Surge to C_fly143 cannot follow in time, T2132 may be subjected to an over-voltage stress. The maximum voltage stress of T2132 is clamped at V by including diode D3143_bus+Lower, C_flyThe voltage on 151 may follow this increase. This is shown in fig. 4A and 4B.

Fig. 4A shows the multi-state boost converter configured at stage a in fig. 2D, where T1131 (and S133) is closed and T2132 is open. With D3 not in place, a voltage surge on the grid would feed through C_fly151 node X on the bottom plate. This results in a sharp increase in the level at node X and places greater stress on T2132 and L112. By including D3, node X is clamped at 1/2V_bus+To obtain V_bus+To maintain any spikes on the grid from node X. Fig. 4B shows the multi-state boost converter configured as stages B and D in fig. 2D, with both T1131 and T2132 turned on. Diode D3143 again retains any spike from node X. Clamp the node at 1/2V_bus+To obtain V_bus+The adjustment value of (2). Diodes D1141 and D4144 prevent V_bus+Any surge below follows the top of the graph from V_bus+Along a parallel path to L122. Thus, the inclusion of D3143 may provide a very reliable solution for abnormal grid interactions.

In a structure having a structure such as C in FIG. 2A_fly151, precharging the flying capacitor at start-up is often a problem. In the above discussion regarding normal operation, switch S133 has been closed and not discussed. However, the inclusion of switch S133 provides pair C_fly151 performs a simple solution for pre-charging.

Fig. 5 shows a multi-state boost converter configured to perform a precharge operation, which may be performed for a few milliseconds, for example, to initialize the circuit before normal operation begins. The switch S133 and the switches T1131 and T2132 are opened. Thus, current may flow through boost inductor L112 through D1141 and to C_fly151 top polePlate, put it under Vin and pull node X high. Since current can also flow to the output node through D4144, pair C will also be_bus+152 and C_bus-153 is initialized. Thus, the circuit is precharged without requiring the cost and complexity of a special precharge element.

The embodiment of fig. 2A includes switch S133, which may be used for the precharge process described in fig. 5, with a path of diode D4144 in parallel with series connected diodes D1141 and D2142, and on diode D3143. One or a combination of these elements may be omitted in alternative embodiments. For example, fig. 6A shows an alternative embodiment that does not include D4144.

Fig. 6A presents another embodiment of a multi-level boost converter circuit 100 incorporating the dc-dc conversion system of fig. 2B. In this example, the input voltage source Vin 107 is again connected at ground (or, more generally, the lower bus voltage level V_bus-) And boost inductor L112. Boost inductor L112 is connected to upper bus voltage level V by a pair of series connected diodes D1141 and D2142_bus+An output node of (c). Diodes D1141 and D2142 are used to pass current from inductor L112 to V_bus+And (4) nodes. With respect to the embodiment of fig. 2A, the path through D4 parallel to D1141, D2142 is not included in fig. 6A. The load is represented by R109 and is connected to V_bus+And V_bus-In the meantime. For example, the input voltage may be a photovoltaic converter at 200V, V_bus+And V_bus-Is the high line and the ground line of the power grid at 480V.

The arrangement of the other elements of FIG. 6A is similar to the illustrated embodiment of FIG. 2A, except that D4144 is not included. Flying capacitor C_fly151 has one plate connected to the node between diodes D1141 and D2142, the second plate of which is connected to internal node X. One side of the internal node X is connected to the capacitor C_bus+152 and C_bus-153 and the other side is connected between switches T1131 and T2132. Capacitor C_bus+152 and C_bus-153 are connected in series at V_bus+And V_bus-In between, a capacitive voltage divider is formed. In one set of embodiments, assume capacitor C_bus+152 and C_bus-153 have the same capacitance, capacitor C_bus+152 and C_bus-The level at the node between 153 will be at 1/2V_bus+The following steps.

In fig. 6A, the bridge circuit is also composed of switches T1131 and T2132. One side of which is connected between the boost inductor L112 and the series diodes D1141 and D2142, and the other side is grounded. A bridge circuit may be used to generate a multi-level waveform on node X when switch S133 is closed. The switch S133 may be opened again at the time of precharging. According to this embodiment, the switches T1131, T2132 and S133 may be implemented as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), bipolar junction transistors (bipolar transistors or BJTs) or other actively controlled power semiconductors. For example, fig. 2E shows a high voltage NMOS device and fig. 2F shows a high voltage IGBT that can be used for T1131, T2132, and S133, where the diode shown is the intrinsic body diode of the device, rather than a separate element. Control voltage V of the device_TApplied to the control gate of the device and corresponding to V for T1131, T2132 and S133 respectively_T1、V_T2And V_S。

The operation of the system using the embodiment of fig. 6A may be as also described in fig. 2B-2D. When switch T1131 is on (closed) but switch T2132 is off (open), node X will be at V_inThe following steps. When switch T1131 is open (open) but switch T2132 is conductive (closed), node X will be at ground voltage. When switches T1131 and T2132 are both open, node X will be at 1/2V_bus+The following steps. This results in a multi-level waveform on node X. The switches T1131 and T2132 have non-overlapping control waveforms so that the switches T1131 and T2132 do not conduct simultaneously.

Fig. 2D also shows a set of waveforms for a dc-dc conversion system 2B having the multi-state boost converter of fig. 6A. During phases a and C, the circuit in fig. 6A will be as shown in fig. 3A and 3C, respectively, but with the path through D4144 removed. However, in phases b and D, boost inductors L112 and V are no longer available since the D4 path is no longer available_bus+The main path between the nodes will pass through the diode pair D1141, D2142, as compared to the path in FIG. 6BThe heavy line is heavy.

The embodiment of the multilevel boost converter in fig. 6A also comprises a diode D3143. Through this diode, the bottom plate of Cfly 151 at node X is connected to C_bus+152 and C_bus-153, respectively, is the middle node of the capacitive divider. As with the embodiment of FIG. 2A, this may help prevent V_bus+To the voltage surge of C_fly151. For example, if V_bus+And V_bus-High and low lines of the grid, D3143 may help prevent damage to components caused by the transmission of such power surges back to the boost converter 100. When switch T1131 is closed but switch T2132 is open, the case of the embodiment of fig. 6A is as described above with respect to fig. 4A, but the path through D4144 is omitted.

Fig. 6C shows the multi-state boost converter of fig. 6A configured as stages b and D of fig. 2D, with both T1131 and T2132 open. Diode D3143 again retains any spike from node X. Clamping node at 1/2V_bus+To obtain V_bus+The adjustment value of (2). Diodes D1141 and D2142 prevent V_bus+Any surge in (v) is fed back along the path to L122. Thus, the inclusion of D3143 may provide a very reliable solution for abnormal grid interactions.

Fig. 6D shows a multi-state boost converter configured for the precharge operation of the embodiment of fig. 6A, corresponding to fig. 5 for the embodiment of fig. 2A. The precharge phase may last for a few milliseconds, for example, to initialize the circuit before normal operation begins. The switch S133 and the switches T1131 and T2132 are opened. Thus, current may flow through boost inductor L112 through D1141 and to C_fly151, which places it under Vin and pulls node X high. Since current can also flow to the output node through D1141 and D2142, pair C_bus+152 and C_bus-153 is initialized. Thus, the circuit of FIG. 6A is precharged without requiring the cost and complexity of a special precharge element.

Fig. 7 is a flow chart illustrating operation of the systems of fig. 2B-2F using either of fig. 2A or fig. 6A as an embodiment of a dc-dc converter. The precharge phase begins in 700. As shown in fig. 5, in 701, the switches T1131, T2132 and S133 are opened (opened), and the circuit is precharged by the input voltage Vin in 703. Once precharged, switch S133 is turned on (closed), and then an output voltage is generated at 710.

At 710, an output voltage V is generated_bus+The method comprises the following steps: an input dc voltage Vin is received at 711. In 713, the control circuit 190 of the block generates control waveforms for the bridge circuit. For embodiments of bridge circuits such as switches T1131 and T2132, one example is a first non-overlapping waveform V as shown by the top two traces of FIG. 2D_T1And a second non-overlapping waveform V_T2. Then, at 715, the first non-overlapping waveform V is applied_T1And a second non-overlapping waveform V_T2Bridge circuits for T1131 and T2132. In 717, a multi-level waveform is generated on node X of fig. 2A or fig. 6A. At 719, the multi-level waveform is applied sequentially on node X to generate the output voltage V_bus+。

When the output voltage V is generated at 710_bus+At 720, the control circuit 190 may regulate the output voltage. This embodiment may adjust the output by changing the duty cycle of the control waveform, the period of the control waveform, or a combination thereof. In the embodiment of fig. 7, the output voltage is adjusted by varying the duty cycle of the control waveform in step 720. The control circuit 190 may receive the output voltage V_bus+An input voltage of Vin may also be received. Based on these levels, control circuit 190 may vary the duty cycle (and/or period) of the control signal and the bridge, thereby adjusting V_bus+Value of or V_bus+The ratio of/Vin. The adjusted value may be set by user input. This may be manual or automatic. The control circuitry may be implemented in hardware, software, firmware, or a combination thereof.

Thus, the embodiments presented above present topologies and operating/control strategies for dc-dc conversion systems using boost converters. Embodiments improve efficiency by using the multi-level operation, provide a simple solution to pre-charging of the topological flying capacitor by protecting components from abnormal conditions by only subjecting the components to low stress in such cases.

For the purposes of this document, it should be noted that the dimensions of the various features depicted in the drawings are not necessarily drawn to scale.

For the purposes of this document, the specification may refer to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" to describe different embodiments or the same embodiment.

For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., through one or more other components). In some cases, when an element is described as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element through the relevant element. When an element is described as being directly connected to another element, there is no element in question between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that an electronic signal can be transmitted between them.

For the purposes of this document, the term "based on" may be understood as "based at least in part on".

For the purposes of this document, unless otherwise specified, the use of numerical terms such as "first" object, "second" object, and "third" object are used for identification purposes to identify different objects, and do not imply an ordering of the objects.

For the purposes of this document, the term "set" of objects may refer to a "set" of one or more objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter claimed herein to the precise form(s) disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the disclosed technology and its practical application, to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.