阅读说明：本技术 存储器控制器及其操作方法 (Memory controller and operating method thereof ) 是由 边谕俊 于 2019-10-23 设计创作，主要内容包括：本文描述了存储器控制器及其操作方法。一种被配置为控制存储器装置的存储器控制器可以包括：映射数据确定单元,被配置为从存储器装置接收位图信息,位图信息指示与位图信息中包括的位相对应的并且包括多个扩展映射数据的映射段是否已被存储在存储器装置中；以及映射数据管理单元,被配置为基于位图信息输出关于多个扩展映射数据的生成的信息。多个扩展映射数据中的每一个可以包括逻辑块地址和物理块地址之间的映射信息。(Memory controllers and methods of operating the same are described herein. A memory controller configured to control a memory device may include: a map data determination unit configured to receive bitmap information from the memory device, the bitmap information indicating whether a map segment corresponding to a bit included in the bitmap information and including a plurality of extension map data has been stored in the memory device; and a map data management unit configured to output information on generation of the plurality of extended map data based on the bitmap information. Each of the plurality of extended mapping data may include mapping information between a logical block address and a physical block address.)

1. A memory controller, comprising:

a map data determination unit configured to receive bitmap information from a memory device, the bitmap information indicating whether a map segment has been stored in the memory device, the map segment corresponding to a bit included in the bitmap information and including a plurality of extension map data; and

a mapping data management unit configured to output information regarding generation of the plurality of extended mapping data based on the bitmap information,

wherein each of the plurality of extended mapping data includes mapping information between a logical block address and a physical block address.

2. The memory controller of claim 1, wherein each of the plurality of extension map data comprises a logical block address of a thermal data region determined according to a frequency of host access to the logical block address.

3. The memory controller according to claim 1, wherein each of the plurality of extension map data further includes additional field information including information on a number of times the mapping relationship between the logical block address and the physical block address has been updated.

4. The memory controller of claim 1, wherein each of the plurality of extension map data further comprises additional field information, the additional field information comprising information for error correction.

5. The memory controller according to claim 1, wherein based on the bitmap information, the map data management unit determines to output the plurality of extended map data generated if the plurality of extended map data have all been generated, and determines to generate the plurality of extended map data if the plurality of extended map data have not all been generated.

6. The memory controller according to claim 1, wherein the mapping data management unit outputs a command for generating a bitmap of a mapping segment corresponding to the plurality of extended mapping data to the memory device.

7. The memory controller according to claim 5, wherein when the memory device is in a power sleep mode during generation of the plurality of extension map data, the map data management unit generates the plurality of extension map data based on the bitmap information after the power sleep mode ends.

8. The memory controller according to claim 5, wherein when all of the plurality of expanded mapping data corresponding to the mapping segment is generated, the mapping data management unit outputs a command for storing the plurality of expanded mapping data corresponding to the mapping segment to the memory device.

9. The memory controller according to claim 8, wherein when all of the plurality of expanded mapping data corresponding to the mapping segment is generated, the mapping data management unit outputs a response indicating that the plurality of expanded mapping data corresponding to the mapping segment has been generated to the memory device.

10. The memory controller according to claim 5, wherein the mapping data management unit outputs a command for updating the bitmap corresponding to the mapping segment to the memory device when all of the plurality of extension mapping data corresponding to the mapping segment is generated.

11. The memory controller according to claim 1, wherein the mapping data management unit outputs a command for outputting the plurality of extension mapping data to a host to the memory device based on the bitmap information.

12. The memory controller according to claim 1, wherein when the plurality of extension map data are not stored in the memory device, the map data management unit outputs a generation incomplete response indicating that the plurality of extension map data are not stored in the memory device.

13. A method of operating a memory controller, the method comprising:

receiving a request from a host to generate extended mapping data;

receiving bitmap information of a map segment corresponding to a plurality of extension map data from a memory device in response to the request;

determining whether to generate a bitmap based on the bitmap information; and

generating the plurality of extended mapping data,

wherein each of the plurality of extended mapping data includes mapping information between a logical block address and a physical block address.

14. The method of claim 13, further comprising: outputting a generate complete response to the host when the plurality of extension mapping data have been generated.

15. The method of claim 13, further comprising: outputting, to the memory device, a command to store the plurality of extension map data in the memory device when all of the plurality of extension map data have been generated.

16. The method of claim 15, wherein generating the plurality of extension mapping data comprises: regenerating a plurality of mapping data corresponding to an associated mapping segment until all of the plurality of mapping data corresponding to the mapping segment is generated.

17. The method of claim 13, further comprising: outputting a command to update the bitmap to the memory device when all of the plurality of extension map data have been generated.

18. A method of operating a memory controller, the method comprising:

receiving a request from a host to output extension mapping data to the host;

receiving bitmap information of a map segment corresponding to a plurality of extension map data from a memory device in response to the request; and

determining whether to output the plurality of extension mapping data based on the bitmap information,

wherein each of the plurality of extended mapping data includes mapping information between a logical block address and a physical block address.

19. The method of claim 18, wherein determining whether to output the plurality of extension mapping data comprises: determining whether to output a plurality of expanded mapping data corresponding to the mapping segment.

20. The method of claim 18, further comprising: when the plurality of extension mapping data does not exist, outputting a generate incomplete response to the host.

Technical Field

Various embodiments of the present disclosure relate generally to electronic devices and, more particularly, to memory controllers and methods of operating memory controllers.

Background

Typically, the storage device stores data under the control of a host device such as a computer, smart phone or smart tablet. Examples of the storage device may be classified into a device such as a Hard Disk Drive (HDD) that stores data in a magnetic disk and a device such as a Solid State Drive (SSD) or a memory card that stores data in a semiconductor memory (particularly, a nonvolatile memory) according to the type of the device provided to store data.

The memory device may include a memory device in which data is stored and a memory controller configured to store the data in the memory device. Memory devices can be classified into volatile memory and non-volatile memory. Representative examples of non-volatile memory may include read-only memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change random access memory (PRAM), magnetic ram (mram), resistive ram (rram), and ferroelectric ram (fram).

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory controller capable of efficiently generating mapping data and a method of operating the memory controller.

Embodiments of the present disclosure may provide a memory controller configured to control a memory device, the memory controller including: a map data determination unit configured to receive bitmap information from the memory device, the bitmap information indicating whether a map segment including a plurality of extension map data has been stored in the memory device; and a mapping data management unit configured to output information regarding generation of a plurality of extended mapping data based on the bitmap information, wherein each of the plurality of extended mapping data may include mapping information between a logical block address and a physical block address and additional field information.

Embodiments of the present disclosure may provide a method for operating a memory controller configured to control a memory device, the method comprising: receiving a request from a host to generate extended mapping data; receiving bitmap information of a map segment corresponding to the plurality of extension map data from the memory device in response to the request; determining whether to generate a bitmap based on the bitmap information; and generating a plurality of extension mapping data, wherein each of the plurality of extension mapping data includes mapping information between a logical block address and a physical block address.

Embodiments of the present disclosure may provide a method of operating a memory controller configured to control a memory device, the method comprising: receiving a request from a host to output extension mapping data to the host; receiving bitmap information of a map segment corresponding to the plurality of extension map data from the memory device in response to the request; and determining whether to output a plurality of extension mapping data based on the bitmap information, wherein each of the plurality of extension mapping data includes mapping information between a logical block address and a physical block address.

Embodiments of the present disclosure may provide a storage apparatus, including: a memory device including a plurality of regions for storing data; and a controller adapted to control the memory device, wherein the controller receives bitmap information from the memory device, the bitmap information including a plurality of bits, each bit corresponding to a plurality of mapping data in the mapping section, and determines whether each of the plurality of mapping data is generated based on the bitmap information.

Embodiments of the present disclosure may provide a storage apparatus, including: a memory device including a plurality of regions for storing data; and a controller adapted to control the memory device, wherein the controller receives bitmap information from the memory device, the bitmap information including a plurality of bits, each bit corresponding to a plurality of mapping data in the mapping section, and determines whether each of the plurality of mapping data is generated based on the bitmap information, wherein the controller generates the plurality of mapping data when it is determined that the plurality of mapping data is not generated.

Drawings

Fig. 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating the memory controller of fig. 1.

Fig. 3A and 3B are diagrams illustrating normal mapping data and extended mapping data according to an embodiment of the present disclosure.

Fig. 4A and 4B are diagrams illustrating bitmaps to be stored in a memory device according to an embodiment of the present disclosure.

FIG. 5 is a diagram illustrating the operation of a memory controller after generation of mapping data corresponding to a mapping segment has been completed according to an embodiment of the present disclosure.

Fig. 6A and 6B are diagrams illustrating updates on a bitmap according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

Fig. 8 is a diagram illustrating a method of outputting mapping data corresponding to a request of a host according to an embodiment of the present disclosure.

Fig. 9 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

Fig. 10 is a block diagram illustrating the memory device of fig. 1.

Fig. 11 is a diagram illustrating an example of the memory cell array of fig. 10.

Fig. 12 is a circuit diagram illustrating a memory block of a plurality of memory blocks according to an embodiment of the present disclosure.

Fig. 13 is a circuit diagram illustrating a memory block of a plurality of memory blocks according to an embodiment of the present disclosure.

Fig. 14 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

Fig. 15 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

Fig. 16 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

Fig. 17 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

Fig. 18 is a block diagram illustrating a memory card system including a storage device according to an embodiment of the present disclosure.

Fig. 19 is a block diagram illustrating a Solid State Drive (SSD) system including a storage device according to an embodiment of the disclosure.

Fig. 20 is a block diagram illustrating a user system including a storage device according to an embodiment of the present disclosure.

Detailed Description

The specific structural and functional descriptions of the embodiments of the present disclosure that are incorporated in this specification or application are intended to describe the embodiments of the present disclosure only. The description should not be construed as limited to the embodiments described in the specification or the application.

The present disclosure is described in detail based on examples. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein but should be construed to cover modifications, equivalents, or alternatives falling within the spirit and scope of the present disclosure. It should be understood, however, that the description is not intended to limit the disclosure to those exemplary embodiments, and the disclosure is not intended to cover the exemplary embodiments but rather, to cover various alternatives, modifications, equivalents, and other embodiments, which may fall within the spirit and scope of the disclosure.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element may also be referred to as a first element.

It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present. Other expressions describing a relationship between elements (e.g., "between", "directly between", "adjacent to" or "directly adjacent to") should be interpreted in the same manner.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

A detailed description of functions and configurations well known to those skilled in the art will be omitted so as not to obscure the subject matter of the present disclosure. This is intended to omit unnecessary description in order to make the subject matter of the present disclosure clear.

Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the disclosure are shown, so that those skilled in the art can easily implement the technical ideas of the disclosure.

Fig. 1 is a block diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200.

The storage device 50 may be a device configured to store data under the control of a host 300, such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a Television (TV), a tablet Personal Computer (PC), or a vehicle infotainment system.

The storage device 50 may be manufactured as any of various types of storage devices according to a host interface as a communication system for communicating with the host 300. For example, the data storage device 50 may be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC, or micro-MMC type multimedia cards, SD, mini-SD, micro-SD type secure digital cards, Universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card type storage devices, Peripheral Component Interconnect (PCI) card type storage devices, PCI-express (PCI-E) type storage devices, Compact Flash (CF) cards, smart media cards, and memory sticks.

The memory device 50 may be manufactured in any of a variety of package types. For example, the storage device 50 may be manufactured in the form of any of various package types such as a Package On Package (POP) type, a System In Package (SIP) type, a System On Chip (SOC) type, a multi-chip package (MCP) type, a Chip On Board (COB) type, a wafer-level manufacturing package (WFP) type, and a wafer-level stack package (WSP) type.

The memory controller 200 may control the overall operation of the memory device 50.

When power is supplied to the storage device 50, the memory controller 200 may execute the firmware. In the case where the memory device 100 is a flash memory device, the memory controller 200 may execute firmware, such as a Flash Translation Layer (FTL), for controlling communication between the host 300 and the memory device 100.

The memory controller 200 may include a mapping data determination unit 210. The mapping data determining unit 210 may receive the mapping data generation request MG _ REQ from the host pc 300. The mapping data generation request MG _ REQ may be an extended mapping data request. The extended mapping data request may be a request to generate or read extended mapping data. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the mapping relationship between the logical block address LBA and the physical block address PBA has been updated and/or information for extending error correction of the mapping data. The extension map data may be data including a logical block address LBA of the hot data area. The hot data area may be determined based on the access frequency of the host 300 to the logical block address LBA. For example, when the access frequency for a certain logical block address is relatively high (or greater than a threshold), the area corresponding to the certain logical block address may be a hot data area. In contrast, when the access frequency for a certain logical block address is relatively low, the area corresponding to the certain logical block address may be a cold data area.

The mapping data determination unit 210 may receive the bitmap information BM _ INF of the mapping segment corresponding to the plurality of extended mapping data based on an internal operation of the memory controller 200 or a data generation request MG _ REQ received from the host 300. In various embodiments, the mapping data determination unit 210 may receive the bitmap information BM _ INF of the mapping segment to which the extended mapping data corresponding to the internal operation of the memory controller 200 or the data generation request MG _ REQ received from the host 300 belongs. Each mapping segment may include a plurality of extension mapping data. The bitmap information BM _ INF may include information on the mapped segment. That is, the bitmap information BM _ INF may include information on a plurality of extension map data corresponding to the map segment. In various embodiments, the bitmap information BM _ INF may include information on whether the generation of the plurality of extension map data is completed and a location where the extension map data is stored. The mapping data determining unit 210 may output the bitmap information BM _ INF to the mapping data managing unit 220.

The mapping data managing unit 220 may determine whether to generate or output a plurality of extension mapping data based on the bitmap information BM _ INF. Further, the mapping data management unit 220 may output a response corresponding to the mapping data generation request MG _ REQ based on the bitmap information BM _ INF.

In various embodiments, if the request received from the host 300 is a request for generating a plurality of extension mapping data, the mapping data management unit 220 may generate and output the plurality of extension mapping data. Alternatively, if the request received from the host 300 is a request for reading a plurality of extension mapping data, the mapping data management unit 220 may read the plurality of extension mapping data from the memory device 100 and output them to the host 300.

The memory device 100 may store data therein. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells configured to store data therein. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In one embodiment, each page may be a unit of storing data in the memory device 100 or reading stored data from the memory device 100. Each memory block may be a unit of erase data.

In one embodiment, memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4(LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a low power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, Resistive Random Access Memory (RRAM), phase change memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or spin transfer torque random access memory (STT-RAM). In this specification, the memory device 100 is a NAND flash memory.

In one embodiment, the memory device 100 may be embodied as a three-dimensional array structure. The present disclosure can be applied not only to a flash memory in which a charge storage layer is formed of a conductive Floating Gate (FG) but also to a charge trap flash memory (CTF) in which a charge storage layer is formed of an insulating layer.

In one embodiment, each memory cell in memory device 100 may be formed of a Single Level Cell (SLC) capable of storing one bit of data. Alternatively, each memory cell included in the memory device 100 may be formed of a multi-level cell (MLC) capable of storing two-bit data, a three-level cell (TLC) capable of storing three-bit data, or a four-level cell (QLC) capable of storing four-bit data.

The memory device 100 may receive a command and an address from the memory controller 200 and access a region of the memory cell array selected by the address. In other words, the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write (or program) operation, a read operation, and an erase operation. During a programming operation, the memory device 100 may program data to a region selected by an address. During a read operation, the memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data from the area selected by the address.

The memory device 100 may perform a program operation or an erase operation using a set operation voltage under the control of the memory controller 200.

Memory device 100 may include a mapping data storage unit 130. The mapping data storage unit 130 may receive the extended mapping data generated by the mapping data management unit 220. The extension mapping data may be mapping data generated in response to an internal operation of the memory controller 200 or a mapping data generation request of the host 300. The mapping data storage unit 130 may receive the extended mapping data corresponding to the mapping segment from the mapping data management unit 220. The number of expanded mapping data corresponding to a mapping segment may vary. In other words, if the mapping data managing unit 220 generates all of the plurality of extended mapping data in the mapping segment, the extended mapping data in the mapping segment may be stored in the mapping data storage unit 130.

In various embodiments, if the mapping data managing unit 220 generates all of the plurality of extended mapping data corresponding to the mapping segment, the mapping data storage unit 130 may receive the plurality of extended mapping data corresponding to the mapping segment from the mapping data managing unit 220. The mapping data storage unit 130 may store the received extended mapping data.

The map data storage unit 130 may output a plurality of extension map data in the map data storage unit 130 in response to a request of the memory controller 200. The plurality of expanded mapping data may be data corresponding to a mapping segment. In one embodiment, if all of the plurality of expanded mapped data in one mapped segment is output, a plurality of expanded mapped data in a subsequent mapped segment may be output.

The memory device 100 may include a bitmap storage unit 150. The bitmap storage unit 150 may store a bitmap. The bitmap may be set for each mapped segment. That is, a bitmap may exist for each map segment including a plurality of extension map data. The bitmap storage unit 150 may include decision bits corresponding to a plurality of corresponding mapped segments. During initial operation of memory device 100, the decision bit may be stored in bit map storage unit 150. The decision bit may be set to a default value. Thereafter, if the mapping data in a mapping segment is allocated, the corresponding decision bit may be updated after the mapping data corresponding to the associated mapping segment has been generated.

The bitmap may include information about the decision bit and the storage location. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated. The storage location may indicate a location where a plurality of extension mapping data corresponding to the mapping segment has been stored.

If the bitmap corresponding to the mapping segment is not already stored in the bitmap storage unit 150, the bitmap storage unit 150 may generate the bitmap in response to a request of the memory controller 200. The bitmap generated in the initial stage may be set to a default value for each mapped segment. The default value may be set to a logic low level "0" or a logic high level "1". Accordingly, in a case where the memory controller 200 has generated all of the plurality of extended mapping data in the mapping segment corresponding to the request of the host 300, the bitmap can be updated. In various embodiments, the decision bit may be changed from a default value to a particular value. Additionally, the storage location may be changed to indicate an address for a memory block and a corresponding page in the memory block in which the plurality of extension map data has been stored.

In one embodiment, the memory controller 200 may receive data and a logical block address LBA from the host 300, and convert the logical block address LBA to a physical block address PBA indicating an address of a memory unit in which the data is to be stored, the memory unit being included in the memory device 100. Additionally, the memory controller 200 may store mapping information indicating a mapping relationship between the logical block addresses LBA and the physical block addresses PBA in a buffer memory (not shown). In one embodiment, the buffer memory may be implemented within memory controller 200.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a programming operation, the memory controller 200 may provide a program command, a physical block address PBA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a physical block address PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a physical block address PBA to the memory device 100.

In one embodiment, the memory controller 200 may autonomously generate and transmit program commands, addresses, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

In one embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory device 100 in an interleaved manner to enhance the operation performance.

The host 300 may communicate with the storage device 50 using AT least one of various communication methods, such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and reduced load DIMM (lrdimm) communication methods.

Host 300 may include host memory 310. The host memory 310 may store a plurality of extension mapping data received from the mapping data management unit 220. The plurality of extension map data may be data that has been stored in the memory device 100 or read from the memory device 100 by the memory controller 200 in response to a request of the host 300. In various embodiments, after the plurality of expansion map data are stored in the memory device 100 based on the internal operation of the memory controller 200 or the map data generation request MG _ REQ of the host 300, the plurality of expansion map data in the memory device 100 may be stored in the host memory 310 based on the map data read request MR _ REQ of the host 300.

A plurality of extension map data to be stored in the host memory 310 may be stored based on the map segment. The mapping segment may correspond to a plurality of extension mapping data. That is, each map segment may include a plurality of extension map data. In one embodiment, if multiple extents of mapping data corresponding to one mapped segment are stored in host memory 310, multiple extents of mapping data corresponding to subsequent mapped segments may be stored in host memory 310.

Fig. 2 is a diagram illustrating a memory controller (e.g., memory controller 200 of fig. 1) according to an embodiment of the present disclosure.

Referring to fig. 2, the memory controller 200 may include a mapping data determination unit 210 and a mapping data management unit 220.

The mapping data determination unit 210 may receive the mapping data generation request MG _ REQ (r) from the host pc 300. The mapping data generation request MG _ REQ may be an extended mapping data request. The extended mapping data request may be a request to generate or read extended mapping data. The map data generation request MG _ REQ may be a request for generating single or multiple pieces of expanded map data. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the extension mapping data has been updated and/or information for error correction of the extension mapping data. The information for error correction may include error correction bits. The error correction bits may be parity bits. The parity bit may be a bit added to check whether an error has occurred during the information transmission process.

The mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100 based on the mapping data generation request MG _ REQ received from the host 300 (c). The mapping data determining unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ ((c)), and determine whether to generate extended mapping data based on the bitmap information BM _ INF.

In various embodiments, to receive the bitmap information BM _ INF for determining whether to generate the extended mapping data based on the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ, the mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100. The bitmap information BM _ INF may comprise decision bits and storage locations. The decision bit may indicate whether a plurality of expanded mapping data corresponding to the mapping segment has been generated. The storage location may indicate an address where a plurality of extension mapping data corresponding to a request of the host 300 is stored in the memory device 100. The bitmap information BM _ INF may be stored in the memory device 100 based on the mapping section. The map segment may be a unit corresponding to a plurality of extension map data. Each mapping segment may include a plurality of extension mapping data. The number of expanded mapping data in each mapping segment may vary.

The memory device 100 may output bitmap information BM _ INF corresponding to the mapped segment ((c)). The map segment may include a plurality of extension map data. In one embodiment, the map segment may include extended map data corresponding to a request received from the host 300. In one embodiment, the map segment may include extended map data corresponding to internal operations of the memory controller 200.

The bitmap information BM _ INF may include information on a bitmap stored in the bitmap storage unit 150. The bitmap may include decision bits corresponding to each of the plurality of mapped segments. The decision bit may indicate whether all of the plurality of extended mapping data in the corresponding mapping section has been generated. In one embodiment, the decision bit may be a logic low level "0" or a logic high level "1".

In various embodiments, the decision bit may be "0" in the case where all of the plurality of extended mapping data in the mapping segment have not been stored in the memory device 100. Alternatively, the determination bit may be "1" in the case where all of the plurality of extended mapping data in the mapping segment have been stored in the memory device 100.

In the case where the determination bit is "0", the determination bit may be updated from "0" to "1". In one embodiment, if the default value of the decision bit is "1", the decision bit may be updated from "1" to "0" after all of the plurality of extended mapping data included in the mapping section have been generated.

In this figure, bitmap information BM _ INF received from the memory device 100 indicates that all of the plurality of extension map data in the map section have not been stored. The extended mapping data may be mapping data corresponding to a request received from the host pc 300. Alternatively, the extended mapping data may be mapping data generated without a request of the host 300.

The mapping data determining unit 210 may output the generation information GE _ INF based on the bitmap information BM _ INF received from the memory device 100 (r). The generation information GE _ INF may include information for generating the bitmap information BM _ INF and the extension map data.

In various embodiments, in a case where the bitmap information BM _ INF indicates that all of the plurality of extension map data corresponding to the map segment have not been generated, the map data determination unit 210 may output the generation information GE _ INF for generating the bitmap. In addition, in the case where the bitmap information BM _ INF indicates that all of the plurality of extension map data corresponding to the map segment have not been generated, the generation information GE _ INF may include information for generating the plurality of extension map data. In contrast, in the case where the bitmap information BM _ INF indicates that all of the plurality of extension map data corresponding to the map segment have been generated, the generation information GE _ INF may include information indicating that the plurality of extension map data have been generated.

The mapping data managing unit 220 may receive the generation information GE _ INF from the mapping data determining unit 210 (r). The mapping data managing unit 220 may generate bitmap and/or extended mapping data based on the generation information GE _ INF.

In one embodiment, in the case where the bitmap information BM _ INF has not been received from the memory apparatus 100, the mapping data managing unit 220 may output a bitmap generation command BG _ CMD for generating a bitmap to the memory apparatus 100(s). The memory device 100 may generate a bitmap corresponding to the bitmap generation command BG _ CMD. In various embodiments, memory device 100 may generate a bitmap that includes decision bits and storage locations. When generating the bitmap, the predicate bits and the storage locations may each have a default value. The default value may be "0" or "1".

The mapping data managing unit 220 may generate extended mapping data after the bitmap has been generated. In various embodiments, the mapping data management unit 220 may generate extended mapping data based on the mapping segments. The map segment may include a plurality of extension map data. If a plurality of extension mapping data in the mapping section are generated, the mapping data management unit 220 may output the generated extension mapping data to the memory device 100.

Fig. 3A and 3B are diagrams illustrating normal mapping data and extended mapping data generated in response to a request of a host (e.g., the host 300 of fig. 1 and 2) according to an embodiment of the present disclosure.

Referring to fig. 3A and 3B, the mapping data may be generated by the memory controller 200 in response to a request of the host 300. The type of the mapping data may be any one of normal mapping data and extended mapping data. Fig. 3A illustrates an example of normal mapping data. Fig. 3B illustrates an example of expanding the mapping data.

Referring to fig. 3A, normal mapping data may be generated in response to the mapping data generation request MG _ REQ of the host 300. The normal mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA. The normal mapping data may not include additional field information.

The first and second Mapping DATA Mapping _ DATA1 and 2 may be normal Mapping DATA. In other words, the Mapping DATA managing unit 220 of fig. 2 may generate the first Mapping DATA Mapping _ DATA1 and the second Mapping DATA Mapping _ DATA2 based on the Mapping DATA generation request MG _ REQ received from the host 300. In one embodiment, the number of normal mapping data generated by the mapping data managing unit 220 may be increased.

Each of the first Mapping DATA Mapping _ DATA1 and the second Mapping DATA Mapping _ DATA2 may include Mapping information indicating a Mapping relationship between a logical block address LBA and a physical block address PBA. In one embodiment, the first Mapping DATA Mapping _ DATA1 may include Mapping information indicating a Mapping relationship between the first logical block address LBA1 and the first physical block address PBA 1. The second Mapping DATA Mapping _ DATA2 may include Mapping information indicating a Mapping relationship between the second logical block address LBA2 and the second physical block address PBA 2.

Referring to fig. 3B, the expansion map data may be generated in response to an internal operation of the memory controller 200 or a map data generation request MG _ REQ of the host 300. The mapping data generation request MG _ REQ may be received from the host pc 300 based on thermal data information about a thermal data area. The hot data area may be determined based on the access frequency of the host 300 to the logical block address LBA. For example, when the access frequency for a certain logical block address is relatively high (or greater than a threshold), the area corresponding to the certain logical block address may be a hot data area. In contrast, when the access frequency for a certain logical block address is relatively low, the area corresponding to the certain logical block address may be a cold data area. The map data generation request MG _ REQ may be a request for generating expanded map data.

The map data management unit 220 may generate the expanded map data based on the map data generation request MG _ REQ. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The normal mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA. In other words, the extended mapping data may be data including normal mapping data and additional field information.

The extension mapping data may be output to the host 300. The host 300 may store the expansion map data in the host memory 310. Thereafter, the host 300 may output the operation request and the extension map data corresponding to the operation request to the memory controller 200. The memory controller 200 may control an operation to be performed in the memory device 100 based on the operation request and the extension map data corresponding to the operation request.

In one embodiment, the third Mapping DATA Mapping _ DATA3 and the fourth Mapping DATA Mapping _ DATA4 may be extended Mapping DATA. That is, the Mapping DATA managing unit 220 may generate the third Mapping DATA Mapping _ DATA3 and the fourth Mapping DATA Mapping _ DATA4 based on the Mapping DATA generation request MG _ REQ received from the host 300. In one embodiment, the number of extended mapping data generated by the mapping data management unit 220 may be increased.

Each of the third Mapping DATA Mapping _ DATA3 and the fourth Mapping DATA Mapping _ DATA4 may include Mapping information indicating a Mapping relationship between a logical block address LBA and a physical block address PBA, and additional field information k3, k 4. In one embodiment, each of the third and fourth Mapping DATA Mapping _ DATA3 and 4 may include normal Mapping DATA and additional field information.

The third Mapping DATA Mapping _ DATA3 may include Mapping information indicating a Mapping relationship between the third logical block address LBA3 and the third physical block address PBA3, and additional field information k 3. The fourth Mapping DATA Mapping _ DATA4 may include Mapping information indicating a Mapping relationship between the fourth logical block address LBA4 and the fourth physical block address PBA4, and additional field information k 4. The additional field information k3 and k4 in the third Mapping DATA Mapping _ DATA3 and the fourth Mapping DATA Mapping _ DATA4 may each store the number of updates of Mapping information between logical block addresses and physical block addresses or DATA for error correction (e.g., Bose-Chaudhuri-Hocquenghem code (BCH code), low density parity check code (LDPC code, etc.)). The data for error correction may include error correction bits. The error correction bits may be parity bits. The parity bit may be a bit added to check whether an error has occurred during the information transmission process.

In one embodiment, in the case where the number of times the extended mapping data has been updated is stored in the additional field information, the mapping data managing unit 220 may determine the mapping data to be output to the memory device 100 based on the data in the additional field information. In one embodiment, in a case where data for correcting an error in the extension map data is included in the additional field information, the memory controller 200 may perform an operation of correcting an error that has occurred in the extension map data based on the data in the additional field information.

Fig. 4A and 4B are diagrams illustrating bitmaps to be stored in the memory device 100 of fig. 2 according to an embodiment of the present disclosure.

Fig. 4A illustrates a bitmap initially stored in the memory device 100. Fig. 4B illustrates an initial storage location of the bitmap stored in the memory device 100. The bitmap and the storage location may each correspond to a mapped segment. The map segment may include a plurality of extension map data. Further, the host performance enhancer (HPB) map data may include a plurality of map segments.

In one embodiment, the default value for the decision bit may be included in a bitmap initially stored in the memory device 100. The default value of the decision bit may be "0" or "1". In this figure, the default value of the decision bit is "0".

Fig. 4B illustrates an initial location where a plurality of extended mapping data in a mapping segment is stored. The value of the storage location corresponding to the mapped segment may be a default value prior to generation of the plurality of expanded mapping data in the mapped segment. In FIG. 4B, the default value of the storage location is "0".

In one embodiment, in a case where the bitmap information BM _ INF has not been received from the memory apparatus 100, the mapping data management unit 220 may output a bitmap generation command BG _ CMD for generating a bitmap to the memory apparatus 100. Fig. 4A illustrates an initial bitmap generated by the memory device 100 in response to the bitmap generation command BG _ CMD.

In various embodiments, a bitmap may be generated based on the mapped segments. Fig. 4A and 4B illustrate initial generation of bitmaps corresponding to the first Map Segment Map _ Segment1 and the second Map Segment Map _ Segment 2. In one embodiment, the memory device 100 may receive a bitmap generation command BG _ CMD and generate a bitmap corresponding to a greater number of mapping segments based on the bitmap generation command BG _ CMD.

The map segment may be a unit including a plurality of extension map data. In various embodiments, each mapping segment may include at least two or more extension mapping data. In one embodiment, based on the number of extended mapping data corresponding to the mapping data generation request received from the host pc 300, a mapping segment including the extended mapping data may be set. In other words, the map segment may be set based on the number of extension map data to be generated by the memory controller 200.

In one embodiment, bitmaps corresponding to the first Map Segment Map _ Segment1 and the second Map Segment Map _ Segment2, respectively, may be generated. The determination bit may indicate whether extended mapping data corresponding to an internal operation of the memory controller 200 or a mapping data generation request MG _ REQ received from the host 300 has been generated.

The decision bit in the bitmap generated based on the bitmap generation command BG _ CMD may be set to a default value at an initial stage. The default value may be "0" or "1". In fig. 4A, the default value is "0".

The decision bit may be updated if all of the plurality of expanded mapping data corresponding to the mapping segment has been generated. In various embodiments, the decision bit may be updated from "0" to "1" if all of the plurality of expanded mapping data in the mapping segment has been generated. In one embodiment, if the default value of the decision bit is "1", the decision bit may be updated from "1" to "0" after all of the plurality of extended mapping data in the mapping segment have been generated.

In one embodiment, the storage locations corresponding to the mapped segments may be stored in the memory device 100. For example, the storage location may be stored in a non-volatile memory as the memory device 100. The storage location may indicate an address where the extended mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 is stored. The address where the extension map data is stored may be an address of a memory block and a page in the memory block.

The storage location may indicate a location in the mapping segment where the plurality of extended mapping data has been stored. The storage location may be updated if all of the plurality of expanded mapping data in the mapping segment has been generated.

In one embodiment, the memory location generated based on the bitmap generation command BG _ CMD may be set to a default value. The default value may be "0" or "1". In fig. 4B, the default value is "0". Thereafter, if all of the plurality of expanded mapping data corresponding to the mapping segment has been generated, the storage location may be updated.

In various embodiments, if all of the plurality of extended mapping data in the mapping segment has been generated, the storage location may be updated to an address of a memory block in which the extended mapping data has been stored and an address of a corresponding page in the memory block. The storage location may include information on a location of a memory block in which the extension map data has been stored and a location of a corresponding page in the memory block among a plurality of memory blocks in the memory cell array.

Fig. 5 is a diagram illustrating the operation of the memory controller 200 after generation of mapping data corresponding to a mapping segment has been completed according to an embodiment of the present disclosure.

Referring to fig. 5, the memory controller 200 may include a mapping data management unit 220. In the figure, the mapping data determining unit 210 in the memory controller 200 is omitted.

For example, fig. 5 illustrates an operation after a plurality of expansion map data corresponding to the map data generation request MG _ REQ received from the host 300 or the internal operation of the memory controller 200 have been generated. In one embodiment, the mapping data management unit 220 may generate extended mapping data based on the mapping segments. If a plurality of extension mapping data in the mapping section are generated, the mapping data management unit 220 may perform an operation of storing the plurality of extension mapping data in the memory device 100.

In one embodiment, the mapping data management unit 220 may output a mapping segment program command MSP _ CMD to the memory device 100. The map section program command MSP _ CMD may be a command for storing a plurality of extended map data generated by the map data management unit 220 in the memory device 100.

In various embodiments, if the generation of the plurality of extended mapping data is completed, the mapping data management unit 220 may output the mapping segment program command MSP _ CMD to the memory device 100. Each time generation of the extended mapping data in the mapping segment is completed, a command for storing the extended mapping data corresponding to the mapping segment may be output. In one embodiment, if the generation of the expanded mapping data in one mapping segment is completed, the expanded mapping data corresponding to the mapping segment is stored in the memory device 100. Subsequently, the mapping data managing unit 220 may generate extended mapping data corresponding to the subsequent mapping segment.

In one embodiment, the mapping data management unit 220 may output a bitmap program command BMP _ CMD to the memory device 100. The bitmap program command MSP _ CMD may be output after all of the plurality of extension mapping data corresponding to the mapping segment program command BMP _ CMD has been stored in the memory device 100. The bitmap program command BMP _ CMD may be output after the mapped segment program command MSP _ CMD is output. The memory device 100 may receive a bitmap program command BMP _ CMD and update the bitmap.

In various embodiments, the bitmap may be updated to indicate that all of the plurality of extended mapping data corresponding to the mapping segment has been stored. If the memory device 100 receives the bitmap program command BMP _ CMD, the bitmap corresponding to the map segment stored in the memory device 100 may be updated. In one embodiment, the decision bits in the bitmap may be updated from a default value to a particular value. Further, information on where the plurality of extended mapping data corresponding to the mapping segment are stored may be updated.

If the bitmap stored in the memory device 100 is updated, the mapping data managing unit 220 may output a response to the host 300 indicating that the generation of the plurality of extended mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 is completed. Each time all of the plurality of extension map data corresponding to one map segment is generated, a corresponding response may be output to the host pc 300. The response output from the mapping data management unit 220 may be a generation completion response GC _ RES. After the generation completion response GC _ RES has been received, the host 300 may output a request for reading a plurality of extension map data stored in the memory device 100 to the memory controller 200.

Fig. 6A and 6B are diagrams illustrating updates on a bitmap according to an embodiment of the present disclosure.

FIG. 6A illustrates a bitmap including decision bits corresponding to mapped segments. FIG. 6B illustrates storage locations corresponding to mapped segments stored in memory device 100. The map segment may include a plurality of extension map data. Further, the host performance enhancer (HPB) map data may include a plurality of map segments.

In one embodiment, a plurality of extended map data in the map segment may be generated based on an internal operation of the memory controller 200 or a map data generation request MG _ REQ received from the host 300.

In one embodiment, in a case where extension map data corresponding to an internal operation of the memory controller 200 or a request received from the host 300 is not already stored in the memory device 100, a map segment for generating the extension map data may be set. The number of mapped segments may be determined according to the maximum number of extended mapped data that can be included in each mapped segment. The number of mapped segments may be determined according to the number of extended mapping data generated in response to a request received from the host 300.

The number of expanded mapping data corresponding to a mapping segment may vary. For example, one map segment includes four extension map data. Further, a bit included in the bitmap information corresponds to one mapping segment. That is, the four extension map data correspond to one bit included in the bitmap information.

In fig. 6A and 6B, the number of expanded mapping data corresponding to each mapping segment is four. Therefore, if the number of expanded map data to be generated in response to the map data generation request MG _ REQ received from the host pc 300 is eight, the number of map segments may be set to two.

The mapping data managing unit 220 may receive the generation information GE _ INF from the mapping data determining unit 210 and generate extended mapping data. The generation information GE _ INF may include information indicating that extension mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 is not yet stored in the memory device 100. Based on the generation information GE _ INF, the mapping data management unit 220 may generate extended mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ.

In one embodiment, the map data generation request MG _ REQ internally operated by the memory controller 200 or received from the host 300 may be a request for sequentially generating a plurality of map data. In various embodiments, the mapping data generation request MG _ REQ received from the host 300 may be a request for generating random mapping data. In the case where the request received from the host 300 is a request for generating random mapping data, the mapping segments for generating extended mapping data may be set in the requested order.

The mapping data managing unit 220 may generate extended mapping data corresponding to the first mapping Segment Map _ Segment 1. After the plurality of extension Map data corresponding to the first Map Segment Map _ Segment1 has been generated, a plurality of extension Map data corresponding to the second Map Segment Map _ Segment2 may be generated.

If the mapping data managing unit 220 generates all of the plurality of extended mapping data corresponding to the first mapping Segment Map _ Segment1, the bitmap may be updated. In various embodiments, if all of the plurality of extension Map data corresponding to the first Map Segment Map _ Segment1 are generated, the Map data management unit 220 may output a Map Segment program command MSP _ CMD for storing extension Map data corresponding to the first Map Segment Map _ Segment1 in the memory device 100 to the memory device 100.

After all of the plurality of extension Map data corresponding to the first Map Segment Map _ Segment1 are stored in the memory device 100, the Map data management unit 220 may output a bitmap program command BMP _ CMD to the memory device 100 to update the bitmap corresponding to the first Map Segment Map _ Segment 1. The memory device 100 may receive a bitmap program command BMP _ CMD and update the bitmap. In one embodiment, the decision bits and storage locations included in the bitmap may be updated.

The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated. Further, the storage location may indicate a location where a plurality of extension map data corresponding to the map segment has been stored.

Referring to fig. 6A, in order to indicate that all of the plurality of extended mapping data corresponding to the first mapping Segment Map _ Segment1 has been generated, the determination bit may be changed from a default value to a specific value.

For example, since the default value of the decision bit is "0", the decision bit corresponding to the first Map Segment Map _ Segment1 may be updated to "1" after all of the plurality of Map data corresponding to the first Map Segment Map _ Segment1 have been generated.

Referring to fig. 6B, the storage location of the extended Map data corresponding to the first Map Segment Map _ Segment1 may be updated. The storage location may be updated from the default value of "0" to an address where the extended mapping data corresponding to the first mapping Segment Map _ Segment1 has been stored. In fig. 6A and 6B, the address of the extension Map data corresponding to the first Map Segment Map _ Segment1 is the first Page1 of the zeroth memory Block 0.

After all of the plurality of extension Map data corresponding to the first Map Segment Map _ Segment1 have been generated and stored in the memory device 100 and the bitmap has been updated, the Map data management unit 220 may generate extension Map data corresponding to the second Map Segment Map _ Segment 2.

In fig. 6A and 6B, all of the plurality of extension Map data corresponding to the second Map Segment Map _ Segment2 have not been generated. The information on the decision bit and the storage location in the bitmap may be set to a default value of "0". If all of the plurality of extension Map data corresponding to the second Map Segment Map _ Segment2 have been generated, the bitmap corresponding to the second Map Segment Map _ Segment2 may be updated.

In one embodiment, the storage device 50 may operate in the power sleep mode while the mapping data management unit 220 generates the extended mapping data in response to an internal operation of the memory controller 200 or a request of the host 300. The power sleep mode may mean that the memory device 50 operates in a low power state. If the storage device 50 is operating in a power sleep mode, the extended mapping data being generated by the mapping data management unit 220 may be deleted. However, the extension map data is stored in the memory device 100 whenever the extension map data corresponding to the map segment is generated. Accordingly, the mapping data management unit 220 may generate extension mapping data other than the extension mapping data stored in the memory device 100.

In one embodiment, when the storage device 50 operates in the power sleep mode, the mapping data that is being generated by the mapping data management unit 220 and included in the second mapping Segment Map _ Segment2 may be deleted. However, since all of the plurality of extension Map data corresponding to the first Map Segment Map _ Segment1 have been generated and stored in the memory device 100, the Map data management unit 220 may generate only the extension Map data corresponding to the second Segment. That is, the mapping data managing unit 220 may omit the generation of the extended mapping data corresponding to the first mapping Segment Map _ Segment 1.

Accordingly, if the power sleep mode of the storage device 50 ends, the mapping data management unit 220 may receive bitmap information BM _ INF regarding the bitmap stored in the memory device 100 and determine whether to generate the extended mapping data based on the decision bits in the bitmap.

Since the decision bit of the bitmap indicates whether all of the plurality of extended mapping data corresponding to the mapping segment has been generated, the mapping data managing unit 220 may determine whether to generate the extended mapping data based on the decision bit. Thus, in the case where the generation of the expanded mapped data in the mapped segment has not been completed, the expanded mapped data in the corresponding mapped segment may be generated again.

Accordingly, after the mapping data managing unit 220 has generated the plurality of extended mapping data in the second mapping Segment Map _ Segment2 again, the bitmap corresponding to the second mapping Segment Map _ Segment2 may be updated.

Fig. 7 is a diagram illustrating the operation of the memory controller 200 in a case where mapping data corresponding to a mapping segment has been generated according to an embodiment of the present disclosure.

Referring to fig. 7, the memory controller 200 may include a mapping data determination unit 210 and a mapping data management unit 220. Fig. 7 illustrates an operation of the memory controller 200 in a case where extended mapping data corresponding to an internal operation of the memory controller 200 or a mapping data generation request MG _ REQ of the host 300 has been stored in the memory device 100.

The mapping data determination unit 210 may receive the mapping data generation request MG _ REQ (r) from the host pc 300. The map data generation request MG _ REQ may be a request for generating expanded map data. The map data generation request MG _ REQ may be a request for generating a plurality of expanded map data. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the mapping relationship between the logical block address LBA and the physical block address PBA has been updated and/or information for extending error correction of the mapping data. The information for error correction may include error correction bits. The error correction bits may be parity bits. The parity bit may be a bit added to check whether an error has occurred during the information transmission process.

The mapping data determination unit 210 may generate a request MG _ REQ based on an internal operation of the memory controller 200 or mapping data received from the host 300, outputting the bitmap request BM _ REQ to the memory device 100 (c). The mapping data determining unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ ((c)). The mapping data managing unit 210 may receive the bitmap information BM _ INF and determine whether to generate extended mapping data based on the bitmap information BM _ INF.

In one embodiment, the bitmap information BM _ INF may include information on a bitmap corresponding to the mapping segment. The mapping segment may correspond to a plurality of extension mapping data. In other words, the map segment may include a plurality of extended map data. Accordingly, the bitmap information BM _ INF may include information corresponding to at least one mapping segment including extended mapping data corresponding to an internal operation of the memory controller 200 or a mapping data generation request MG _ REQ received from the host 300.

The bitmap information BM _ INF may include information on a decision bit corresponding to the mapped segment and a storage location. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated. The storage location may indicate an address where a plurality of extended mapping data corresponding to the mapping segment has been stored.

In a case where information on the bitmap corresponding to the map segment is not stored in the memory device 100, the bitmap information BM _ INF may indicate that all of the plurality of extension map data corresponding to the map segment has not been generated. In the case where information on the bitmap corresponding to the mapping segment has been stored in the memory device 100, the mapping data determining unit 210 may receive bitmap information BM _ INF including decision bits and storage positions.

In fig. 7, the expanded mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ of the host 300 has been stored in the memory device 100. Accordingly, in the bitmap information BM _ INF output to the memory device 100, the bitmap of at least one map segment corresponding to the extension map data may include information indicating that the extension map data has been stored in the memory device 100. In various embodiments, the decision bit may have a specific value, and the information on the storage location may include information on an address where the extension map data is stored.

The mapping data determining unit 210 may output the generation information GE _ INF based on the bitmap information BM _ INF received from the memory device 100 (r). In one embodiment, the generation information GE _ INF may include information indicating that extended mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 has been generated. The generation information GE _ INF may include information indicating that the mapping data management unit 220 does not generate extended mapping data corresponding to the request of the host 300.

If the mapping data managing unit 220 receives the generation information GE _ INF from the mapping data determining unit 210, the mapping data managing unit 220 may output a generation completion response GC _ RES to the host 300 (c). In one embodiment, the generation information GE _ INF may include information indicating that all of a plurality of extended mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 have been generated. The mapping data management unit 220 may output a generation completion response GC _ RES indicating that all of the plurality of extended mapping data corresponding to the request received from the host 300 have been generated, to the host 300.

After having received the generation completion response GC _ RES from the mapping data management unit 220, the host 300 may output a request for reading the extended mapping data generated in response to the mapping data generation request MG _ REQ to the memory controller 200.

Fig. 8 is a diagram illustrating a method of outputting mapping data corresponding to a request of the host 300 to the host 300 according to an embodiment of the present disclosure.

Referring to fig. 8, the memory controller 200 may include a mapping data determination unit 210 and a mapping data management unit 220. The mapping data determining unit 210 may determine whether extended mapping data corresponding to the mapping data read request MR _ REQ received from the host 300 has been stored in the memory device 100. The mapping data managing unit 220 may receive the extension mapping data corresponding to the mapping data read request MR _ REQ of the host 300 from the memory device 100 and output the extension mapping data to the host 300.

In one embodiment, the mapping data determination unit 210 may receive a mapping data read request MG _ REQ (r) from the host 300. The mapping data read request MR _ REQ may be a request for reading the extended mapping data stored in the memory device 100. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the extension mapping data has been updated and/or information for error correction of the extension mapping data.

The mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100 based on the mapping data read request MR _ REQ received from the host 300 (c). The mapping data determining unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ ((c)). The mapping data managing unit 210 may determine whether to output the extension mapping data based on the bitmap information BM _ INF.

In one embodiment, the bitmap information BM _ INF may include information on a bitmap corresponding to the mapping segment. The mapping segment may correspond to a plurality of extension mapping data. The map segment may include a plurality of extension map data. The bitmap information BM _ INF may include information on the decision bit and storage position corresponding to the mapped segment. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated. The storage location may indicate a location where a plurality of extension mapping data corresponding to the mapping segment has been stored.

In the case where the bitmap information BM _ INF corresponding to the mapped segment is not stored in the memory device 100, the determination bit in the bitmap information BM _ INF may be "0". In the case where the bitmap information BM _ INF corresponding to the map segment has been stored in the memory device 100, the map data determination unit 210 may receive the bitmap information BM _ INF including the updated decision bits and a storage location where the plurality of extension map data included in the map segment is stored.

In one embodiment, the bitmap information BM _ INF in the memory device 100 may include information before generating all of the plurality of extension map data corresponding to the map segment or after they have been generated.

In various embodiments, the bitmap information BM _ INF may include decision bits and storage location information having default values in the case where all of the plurality of extension map data corresponding to the map segment are not generated. After all of the plurality of extension mapping data corresponding to the mapping segment have been generated, the bitmap information BM _ INF may include a decision bit having a specific bit and storage location information including information on an address where the extension mapping data is stored.

In fig. 8, a plurality of extension map data corresponding to the map data read request MR _ REQ of the host 300 have been stored in the memory device 100. Accordingly, the mapping data determining unit 210 may receive information on a bitmap corresponding to at least one mapping segment including the extension mapping data. Here, the bitmap corresponding to at least one mapping segment may include decision bits having a specific value and information on an address where the extension mapping data is stored.

The mapping data determining unit 210 may output the generation information GE _ INF based on the bitmap information BM _ INF received from the memory device 100 (r). The generation information GE _ INF may include information indicating whether extension mapping data corresponding to the request received from the host 300 is already stored.

The mapping data managing unit 220 may receive the generation information GE _ INF from the mapping data determining unit 210. The mapping data managing unit 220 may receive the generation information GE _ INF and output extended mapping data corresponding to a request of the host 300. In the case where all of the plurality of extension map data corresponding to the map data read request MR _ REQ of the host 300 have been stored in the memory device 100, the generation information GE _ INF may include information on a decision bit indicating that all of the plurality of extension map data have been generated. The generation information GE _ INF may include information on a storage location indicating an address where the corresponding extension map data is stored.

In one embodiment, the mapping data management unit 220 may output a mapping data read command MDR _ CMD for outputting extended mapping data corresponding to the mapping data read request MR _ REQ of the host 300 to the memory device 100 (c). The mapping data read command MDR _ CMD may be determined based on the generation information GE _ INF.

If the generation information GE _ INF includes information indicating that all of the plurality of extension mapping data corresponding to the request of the host 300 are stored, the mapping data management unit 220 may output the mapping data read command MDR _ CMD to the memory device 100. The mapping data management unit 220 may output an address where the extended mapping data is stored to the memory device 100 together with the mapping data read command MDR _ CMD.

In one embodiment, the mapping data management unit 220 may receive the extension mapping data from the memory device 100 (sixth). In one embodiment, the mapping data management unit 220 may receive a plurality of extension mapping data from the memory device 100.

In various embodiments, the mapping data management unit 220 may receive the extended mapping data corresponding to the mapping data read command MDR _ CMD from the memory device 100. The mapping data managing unit 220 may receive the extended mapping data based on the mapping segment. When the mapping data managing unit 220 receives the extension mapping data from the memory device 100, the mapping data managing unit 220 may receive all of the plurality of extension mapping data included in one mapping section and then receive the plurality of extension mapping data included in a subsequent mapping section.

The mapping data managing unit 220 may output the extended mapping data received from the memory device 100 to the host 300 (c). The mapping data managing unit 220 may output the extended mapping data corresponding to the mapping data read request MR _ REQ received from the host pc 300 to the host pc 300. The mapping data management unit 220 may output the extended mapping data to the host 300 based on the mapping segment. In the same way as when the extension map data is received from the memory device 100, the map data management unit 220 may output all of the plurality of extension map data in one map section, and then output the plurality of extension map data in the subsequent map section to the host 300.

In one embodiment, the host 300 may store the extended mapping data received from the mapping data management unit 220 in the host memory 310. The extension map data may be stored in the host memory 310 based on the map segment. Host 300 can receive the expanded mapping data corresponding to the mapped segment from mapping data management unit 220 and store the expanded mapping data corresponding to the mapped segment in host memory 310. Host 300 may store expanded mapping data corresponding to one mapped segment and then store expanded mapping data corresponding to a subsequent mapped segment.

Fig. 9 is a diagram illustrating an operation of the memory controller 200 in a case where mapping data corresponding to a request of the host 300 does not exist according to an embodiment of the present disclosure.

Referring to fig. 9, the memory controller 200 may include a mapping data determination unit 210 and a mapping data management unit 220. The mapping data determining unit 210 may determine whether extended mapping data corresponding to the mapping data read request MR _ REQ received from the host 300 has been stored in the memory device 100. The mapping data management unit 220 may output a response corresponding to the mapping data read request MR _ REQ of the host 300 to the host 300.

In one embodiment, the mapping data determination unit 210 may receive a mapping data read request MG _ REQ (r) from the host 300. The mapping data read request MR _ REQ may be a request for reading the extended mapping data stored in the memory device 100. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the mapping relationship between the logical block address LBA and the physical block address PBA has been updated and/or information for extending error correction of the mapping data. The information for error correction may include error correction bits. The error correction bits may be parity bits. The parity bit may be a bit added to check whether an error has occurred during the information transmission process.

The mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100 based on the mapping data read request MR _ REQ received from the host 300 (c). The mapping data determining unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ ((c)). The mapping data managing unit 210 may determine whether to output the extension mapping data based on the bitmap information BM _ INF.

In one embodiment, the bitmap information BM _ INF may include information on a bitmap corresponding to the mapping segment. The mapping segment may correspond to a plurality of extension mapping data. The map segment may include a plurality of extension map data. The bitmap information BM _ INF may include information on the decision bit and storage position corresponding to the mapped segment. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated. The storage location may indicate a location where a plurality of extension mapping data corresponding to the mapping segment has been stored.

In the case where the bitmap information BM _ INF corresponding to the mapped segment is not stored in the memory device 100, the bitmap information BM _ INF may include a determination bit and a storage position having a default value. In the case where the bitmap information BM _ INF corresponding to the map segment has been stored in the memory device 100, the map data determination unit 210 may receive the bitmap information BM _ INF including the updated decision bits and storage positions.

In fig. 9, some or all of a plurality of extension map data corresponding to the map data read request MR _ REQ of the host 300 have not been stored in the memory device 100. Accordingly, the mapping data determining unit 210 may receive bitmap information BM _ INF including decision bits and storage locations of default values or information on a bitmap corresponding to mapping segments including some of the extended mapping data. The bitmap corresponding to the map segment including some of the extension map data may include a decision bit having a specific value and information on an address where the extension map data is stored.

The mapping data determining unit 210 may output the generation information GE _ INF based on the bitmap information BM _ INF received from the memory device 100 (r). The generation information GE _ INF may include information indicating whether extension mapping data corresponding to a request received from the host pc 300 has been stored.

The mapping data managing unit 220 may receive the generation information GE _ INF from the mapping data determining unit 210. The mapping data managing unit 220 may receive the generation information GE _ INF and output extended mapping data corresponding to a request of the host 300. However, in fig. 9, since all or some of the extension map data corresponding to the map data read request MR _ REQ has not been stored in the memory device 100, the map data determination unit 210 may output the generation information GE _ INF including information indicating that the generation of the extension map data corresponding to the request of the host 300 has not been completed.

If the mapping data managing unit 220 receives the generation information GE _ INF from the mapping data determining unit 210, the mapping data managing unit 220 may output the generation incompletion response GNC _ RES to the host pc 300. In one embodiment, the generation information GE _ INF may include information indicating that all of a plurality of extension mapping data corresponding to the internal operation of the memory controller 200 or the mapping data generation request MG _ REQ received from the host 300 have not been generated. The mapping data management unit 220 may output to the host 300 a generation incomplete response GNC _ RES indicating that all of the plurality of extension mapping data corresponding to the request received from the host 300 have not been generated (c).

After having received the generation incompletion response GNC _ RES from the mapping data management unit 220, the host 300 may output a mapping data generation request MG _ REQ for generating the expanded mapping data that has not been generated yet. The mapping data management unit 220 may generate the extended mapping data based on the mapping data generation request MG _ REQ received from the host pc 300.

Fig. 10 is a block diagram illustrating a memory device (e.g., memory device 100 of fig. 1) according to an embodiment of the present disclosure.

Referring to fig. 10, the memory device 100 may include a memory cell array 110 and a peripheral circuit 120. Peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write (read/write) circuit 123, a data input and output (input/output) circuit 124, and control logic 125.

Memory cell array 110 may include a plurality of memory blocks BLK1 through BLKz. Memory blocks BLK1 through BLKz are connected to address decoder 121 through row lines RL and to read/write circuit 123 through bit lines BL1 through BLm. Each of the memory blocks BLK1 through BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be non-volatile memory cells.

The plurality of memory cells in the memory cell array 110 may be divided into a plurality of blocks according to the purpose of use. System information such as various setting information required to control the memory device 100 may be stored in a plurality of blocks.

Each of the first to z-th memory blocks BLK1 to BLKz includes a plurality of memory cell strings. The first through mth cell strings are coupled to first through mth bit lines BL1 through BLm, respectively. Each of the first through m-th cell strings includes a drain select transistor, a plurality of memory cells coupled in series to each other, and a source select transistor. The drain select transistor DST is coupled to a drain select line DSL. The first to nth memory cells are coupled to the first to nth word lines, respectively. The source select transistor SST is coupled to a source select line SSL. The drain of the drain select transistor DST is coupled to a corresponding bit line. The drain select transistors DST of the first through mth cell strings are coupled to first through mth bit lines BL1 through BLm, respectively. The source of the source select transistor SST is coupled to a common source line CSL. In one embodiment, the common source line CSL may be commonly coupled to the first through z-th memory blocks BLK1 through BLKz. The drain select line DSL, the first to nth word lines WL1 to WLn, and the source select line SSL are included in the row line RL. The drain select line DSL, the first to nth word lines WL1 to WLn, and the source select line SSL are controlled by the address decoder 121. The common source line CSL is controlled by control logic 125. The first bit line BL1 to the mth bit line BLm are controlled by the read/write circuit 123.

Address decoder 121 is coupled to memory cell array 110 by row lines RL. Address decoder 121 may operate under the control of control logic 125. Address decoder 121 receives address ADDR through control logic 125.

In one embodiment, the program operation and the read operation of the memory device 100 may be performed on a page basis.

During a program operation or a read operation, the address ADDR received by the control logic 125 may include a block address and a row address. The address decoder 121 may decode a block address among the received addresses ADDR. The address decoder 121 may select a corresponding one of the memory blocks BLK1 through BLKz in response to the decoded block address.

The address decoder 121 may decode a row address among the received addresses ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage supplied from the voltage generator 122 to the row line RL and select one word line of the selected memory block.

During an erase operation, the address ADDR may include a block address. The address decoder 121 may decode a block address and select one memory block according to the decoded block address. The erase operation may be performed on all or a portion of one memory block.

During a partial erase operation, the address ADDR may include a block address and a row address. The address decoder 121 may select a corresponding one of the memory blocks BLK1 through BLKz in response to the decoded block address.

The address decoder 121 may decode a row address among the received addresses ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage supplied from the voltage generator 122 to the row line RL and select at least one word line of the selected memory block.

In one embodiment, the address decoder 121 may include a block decoder, a word line decoder, and an address buffer.

The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic 125.

In one embodiment, the voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated from the voltage generator 122 may be used as an operation voltage of the memory device 100.

In one embodiment, the voltage generator 122 may generate the plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal supply voltage, and generate the plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 125. The generated voltage is applied to the word line selected by the address decoder 121.

During a program operation, the voltage generator 122 may generate a program pulse having a high voltage and a pass pulse having a lower voltage level than the program pulse. During a read operation, the voltage generator 122 may generate a read voltage and a pass voltage higher than the read voltage. During an erase operation, voltage generator 122 may generate an erase voltage.

The read/write circuit 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are coupled to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may be operated under the control of the control logic 125.

The first to mth page buffers PB1 to PBm may be in data communication with the data input/output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm may receive DATA to be stored through the DATA input/output circuit 124 and the DATA lines DL.

During a program operation, when a program pulse is applied to a selected word line, the first to mth page buffers PB1 to PBm may transmit data received through the data input/output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. Based on the data sent, the memory cells in the selected page are programmed. Memory cells coupled to bit lines that are applied with a program enable voltage (e.g., ground voltage) may have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which the program-inhibit voltage (e.g., a supply voltage) is applied may be maintained. During a program verify operation, the first to mth page buffers PB1 to PBm may read page data from selected memory cells through the bit lines BL1 to BLm.

During a read operation, the read/write circuit 123 may read DATA from the memory cells in the selected page through the bit lines BL and output the read DATA to the DATA input/output circuit 124. During an erase operation, the read/write circuit 123 may float the bit line BL.

In one embodiment, the read/write circuits 123 may include column select circuits.

The data input/output circuit 124 is coupled to the first to mth page buffers PB1 to PBm through the data line DL. The data input/output circuit 124 may operate under the control of control logic 125. During a programming operation, the data input/output circuit 124 may receive data to be stored from an external controller (not shown).

The control logic 125 is connected to the address decoder 121, the voltage generator 122, the read/write circuit 123, and the data input/output circuit 124. Control logic 125 may control the overall operation of memory device 100. The control logic 125 may receive a command CMD and an address ADDR from an external controller. The control logic 125 may control the address decoder 121, the voltage generator 122, the read/write circuit 123, and the data input/output circuit 124 in response to the command CMD.

Fig. 11 is a diagram illustrating an example of a memory cell array (e.g., memory cell array 110 of fig. 10) according to an embodiment of the present disclosure.

Referring to fig. 11, the memory cell array 110 may include a plurality of memory blocks BLK1 through BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The memory cells are arranged in the + X direction, + Y direction, and + Z direction. The structure of each memory block will be described in more detail with reference to fig. 12 and 13.

Fig. 12 is a circuit diagram illustrating a memory block (e.g., memory block BLKa among the plurality of memory blocks BLK1 through BLKz of fig. 11) according to an embodiment of the present disclosure.

Referring to fig. 12, the memory block BLKa may include a plurality of cell strings CS11 through CS1m and CS21 through CS2 m. In one embodiment, each of the cell strings CS11 through CS1m and CS21 through CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., + X direction). In fig. 12, two cell strings are shown arranged in the column direction (i.e., + Y direction). However, this illustration is made for convenience only, and it will be understood that three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 through CS1m and CS21 through CS2m may include at least one source select transistor SST, first through nth memory cells MC1 through MCn, a pipe transistor PT, and at least one drain select transistor DST.

The selection transistors SST and DST and the memory cells MC1 to MCn may have similar structures, respectively. In one embodiment, each of the selection transistors SST and DST and the memory cells MC1 through MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a guide pillar for providing a channel layer may be provided in each cell string. In one embodiment, a guide pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCp.

In one embodiment, the source selection transistors of cell strings arranged in the same row are coupled to a source selection line extending in a row direction, and the source selection transistors of cell strings arranged in different rows are coupled to different source selection lines. In fig. 12, the source select transistors of the cell strings CS11 through CS1m in the first row are coupled to a first source select line SSL 1. The source select transistors of the cell strings CS 21-CS 2m in the second row are coupled to a second source select line SSL 2.

In one embodiment, the source select transistors of the cell strings CS 11-CS 1m and CS 21-CS 2m may be commonly coupled to a single source select line.

The first through nth memory cells MC1 through MCn in each cell string are coupled between the source select transistor SST and the drain select transistor DST.

The first through nth memory cells MC1 through MCn may be divided into first through pth memory cells MC1 through MCp and (p +1) th through nth memory cells MCp +1 through MCn. The first through pth memory cells MC1 through MCp are arranged consecutively in a direction opposite to the + Z direction, and are coupled in series between the source select transistor SST and the tunnel transistor PT. The (p +1) th to nth memory cells MCp +1 to MCn are arranged in succession in the + Z direction and are coupled in series between the pipe transistor PT and the drain select transistor DST. The first through nth memory cells MC1 through MCp and the (p +1) th through nth memory cells MCp +1 through MCn are coupled to each other through a pipe transistor PT. The gates of the first through nth memory cells MC1 through MCn of each cell string are coupled to the first through nth word lines WL1 through WLn, respectively.

The respective gates of the pipe transistors PT of the cell strings are coupled to the line PL.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MCp +1 to MCn. The cell string arranged in the row direction is coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second drain select line DSL 2.

The cell strings arranged in the column direction may be coupled to bit lines extending in the column direction. In fig. 12, cell strings CS11 and CS21 in a first column are coupled to a first bit line BL 1. The cell strings CS1m and CS2m in the mth column are coupled to the mth bit line BLm.

Memory cells coupled to the same word line in cell strings arranged in a row direction form a single page. For example, among the cell strings CS11 through CS1m in the first row, the memory cells coupled to the first word line WL1 form a single page. Among the cell strings CS21 through CS2m in the second row, the memory cells coupled to the first word line WL1 form another single page. When any one of the drain select lines DSL1 and DSL2 is selected, a corresponding cell string arranged in the direction of a single row may be selected. When any one of the word lines WL1 to WLn is selected, a corresponding single page may be selected from among the selected cell strings.

In one embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. The even-numbered cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the respective even bit lines. Odd-numbered cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the corresponding odd bit lines.

In one embodiment, at least one of the first through nth memory cells MC1 through MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells may be provided to reduce an electric field between the drain select transistor DST and the memory cells MCp +1 to MCn. As the number of dummy memory cells increases, the reliability of the operation of the memory block BLKa may increase, and the size of the memory block BLKa may increase. As the number of dummy memory cells decreases, the size of the memory block BLKa may decrease, but the operational reliability of the memory block BLKa may decrease.

In order to effectively control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation has been performed, dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled to the respective dummy memory cells.

Fig. 13 is a circuit diagram illustrating a memory block (e.g., memory block BLKb of the plurality of memory blocks BLK1 through BLKz of fig. 11) according to an embodiment of the present disclosure.

Referring to fig. 13, the memory block BLKb may include a plurality of cell strings CS11 'to CS1 m' and CS21 'to CS2 m'. Each of the cell strings CS11 'to CS1 m' and CS21 'to CS2 m' extends in the + Z direction. Each of the cell strings CS11 ' to CS1m ' and CS21 ' to CS2m ' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) provided in a lower portion of the memory block BLK1 '.

The source select transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 through MCn. The source select transistors of the cell strings arranged in the same row are coupled to the same source select line. The source select transistors of the cell strings CS11 'to CS1 m' arranged in the first row may be coupled to a first source select line SSL 1. The source selection transistors of the cell strings CS21 'to CS2 m' arranged in the second row may be coupled to a second source selection line SSL 2. In one embodiment, the source select transistors of the cell strings CS11 'through CS1 m' and CS21 'through CS2 m' may be commonly coupled to a single source select line.

The first through nth memory cells MC1 through MCn in each cell string are coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the first through nth memory cells MC1 through MCn are coupled to the first through nth word lines WL1 through WLn, respectively.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MC1 through MCn. The drain select transistors of the cell strings arranged in the row direction may be coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'through CS1 m' in the first row are coupled to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 'to CS2 m' in the second row may be coupled to a second drain select line DSL 2.

Accordingly, the memory block BLKb of fig. 13 may have an equivalent circuit similar to that of the memory block BLKa of fig. 12, except that the pipe transistor PT is excluded from each cell string.

In one embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11 'to CS1 m' or CS21 'to CS2 m' arranged in the row direction may be coupled to the respective even bit lines, and odd-numbered cell strings among the cell strings CS11 'to CS1 m' or CS21 'to CS2 m' arranged in the row direction may be coupled to the respective odd bit lines.

In one embodiment, at least one of the first through nth memory cells MC1 through MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce an electric field between the source select transistor SST and the memory cells MC1 through MCn. Alternatively, at least one or more dummy memory cells may be provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 through MCn. As the number of dummy memory cells increases, the reliability of the operation of the memory block BLKb may increase, and the size of the memory block BLKb may increase. As the number of dummy memory cells decreases, the size of the memory block BLKb may decrease, but the operational reliability of the memory block BLKb may decrease.

In order to effectively control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKb, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation has been performed, dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled to the respective dummy memory cells.

Fig. 14 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 1-7) according to an embodiment of the present disclosure.

Referring to fig. 14, at step S1401, the mapping data managing unit 220 may start generation of mapping data. The mapping data management unit 220 may start generation of mapping data in response to a mapping data generation request MG _ REQ received from the host 300 or an internal operation of the memory controller 200.

In one embodiment, the mapping data determining unit 210 may receive the mapping data generation request MG _ REQ from the host 300. The mapping data generation request MG _ REQ may be an extended mapping data request. The extended mapping data request may be a request to generate or read extended mapping data. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information.

At step S1403, the mapping data determining unit 210 may determine the bitmap information BM _ INF from the memory device 100. In various embodiments, the mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100 based on the mapping data generation request MG _ REQ received from the host 300 or an internal operation of the memory controller 200. The mapping data determination unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ and determine whether to generate extended mapping data based on the bitmap information BM _ INF.

At step S1405, the mapping data determining unit 210 may determine whether the decision bit has a logic low level "0". The mapping data determining unit 210 may determine whether the decision bit includes a default value of "0". The decision bits may be bits included in a bitmap. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated.

The mapping data determining unit 210 may receive bitmap information BM _ INF from the memory device 100. Further, the mapping data determining unit 210 may determine whether the extension mapping data has been stored in the memory device 100 based on the bitmap information BM _ INF. When it is determined that the determination bit is not the logic low level "0", that is, if the determination bit has the logic high level "1" (S1405, no), the process proceeds to step S1407. When it is determined that the determination bit is "0" (S1405, yes), the process advances to step S1409.

At step S1407, the mapping data management unit 220 may output a generation completion response GC _ RES to the host 300. In various embodiments, when it is determined that the decision bit in the bitmap information BM _ INF is not the logic low level "0", that is, when it is determined that the decision bit is not the default value, the bitmap information BM _ INF may indicate that all of the plurality of extension map data have been generated and stored in the memory device 100. When it is determined that all of the plurality of extended mapping data have been generated, the mapping data management unit 220 may output a generation completion response GC _ RES to the host 300 because there is no need to generate mapping data.

Accordingly, when the mapping data managing unit 220 receives the generation information GE _ INF from the mapping data determining unit 210, the mapping data managing unit 220 may output a generation completion response GC _ RES to the host pc 300. The generation information GE _ INF may include information indicating that all of a plurality of extension map data corresponding to the map data generation request MG _ REQ received from the host 300 or the internal operation of the memory controller 200 have been generated.

At step S1409, the mapping data managing unit 220 may generate mapping data. The mapping data may be extended mapping data. In one embodiment, the mapping data management unit 220 may generate extended mapping data based on the mapping segments. The map segment may include a plurality of extension map data. When a plurality of extension mapping data included in the mapping segment are generated, the mapping data management unit 220 may output the generated extension mapping data to the memory device 100.

At step S1411, the mapping data management unit 220 may output a mapping segment program command MSP _ CMD to the memory device 100. The map section program command MSP _ CMD may be a command for storing a plurality of extended map data generated by the map data management unit 220 in the memory device 100.

In various embodiments, when the generation of the plurality of extended mapping data is completed, the mapping data management unit 220 may output the mapping segment program command MSP _ CMD to the memory device 100. Each time generation of the extended mapping data in the mapping segment is completed, a command for storing the extended mapping data corresponding to the mapping segment may be output. In one embodiment, when generation of the expanded mapping data in one mapping segment is completed, the expanded mapping data corresponding to the mapping segment is stored in the memory device 100. Subsequently, the mapping data managing unit 220 may generate extended mapping data corresponding to the subsequent mapping segment.

At step S1413, the mapping data management unit 220 may output a bitmap program command BMP _ CMD to the memory device 100. After all of the plurality of extension mapping data corresponding to the mapping segment program command MSP _ CMD has been stored in the memory device 100, the bitmap program command BMP _ CMD may be output. After the map segment program command MSP _ CMD has been output, the bitmap program command BMP _ CMD may be output. The memory device 100 may receive a bitmap program command BMP _ CMD and update the bitmap.

In various embodiments, the bitmap may be updated to indicate that all of the plurality of extended mapping data corresponding to the mapping segment has been stored. When the memory device 100 receives the bitmap program command BMP _ CMD, the bitmap corresponding to the map segment in the memory device 100 may be updated. In one embodiment, the decision bits in the bitmap may be updated from a default value to a particular value. Further, information on where a plurality of extension map data corresponding to the map segment is stored may be updated.

Fig. 15 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 1 and 2) according to an embodiment of the present disclosure.

Referring to fig. 15, at step S1501, the mapping data managing unit 220 may start generation of mapping data included in the mapping section. In various embodiments, a mapping segment may include a plurality of mapping data. The plurality of map data may be a plurality of extended map data to be generated in response to an internal operation of the memory controller 200 or a map data generation request MG _ REQ of the host 300.

In one embodiment, the extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the mapping relationship between the logical block address LBA and the physical block address PBA has been updated and/or information for extending error correction of the mapping data. The information for error correction may include error correction bits. The error correction bits may be parity bits. The parity bit may be a bit added to check whether an error has occurred during the information transmission process.

At step S1503, it is determined whether the current operating state of the storage device 50 is the power sleep mode. The power sleep mode may mean that the storage device 50 operates in a low power state. When it is determined that the storage device 50 operates in the power sleep mode, the extended mapping data generated by the mapping data management unit 220 may be deleted. In the case where the current operating state of the storage device 50 is the power sleep mode, the process proceeds to step S1505.

At step S1505, the mapping data managing unit 220 may interrupt the generation of the mapping data. In other words, the mapping data management unit 220 may interrupt the generation of the mapping data when it is determined that the storage device 50 operates in the low power state. With storage device 50 in a power sleep mode, storage device 50 may perform only minimal operations.

At step S1507, the state of the storage device 50 may be a power-on state. The power wake state may mean that the memory device 50 may operate in a normal power state. When it is determined that the storage device 50 may operate in the normal power state, the mapping data management unit 220 may generate the extended mapping data again.

At step S1509, when the memory device 50 operates in the normal power state, the mapping data determining unit 210 may receive the bitmap information BM _ INF from the memory device 100. The mapping data determining unit 210 may output the generation information GE _ INF to the mapping data managing unit 220 based on the bitmap information BM _ INF.

The mapping data determining unit 210 can check the mapping section corresponding to the generated extended mapping data through the decision bit in the bitmap information BM _ INF. The generated extended mapping data may be checked based on the determined bit of the bitmap corresponding to each mapping segment. Further, the mapping data managing unit 220 may check a mapping segment corresponding to the extended mapping data that generates the interrupt. Based on the determined bit of the bitmap corresponding to each mapped segment, the extended mapping data that generated the interrupt may be examined.

At step S1511, the mapping data managing unit 220 may regenerate all mapping data included in the corresponding mapping segment. The mapping data managing unit 220 may regenerate the extended mapping data, which has been generated with the interrupt and is included in the mapping section, based on the generation information GE _ INF received from the mapping data determining unit 210. The generation information GE _ INF may include information indicating whether extension mapping data corresponding to the request received from the host 300 is already stored.

In one embodiment, memory controller 200 may include a buffer memory as volatile Random Access Memory (RAM) for storing the mapping data. Since the memory controller 200 includes a volatile RAM, the mapping data being generated may be deleted when the storage device 50 operates in the power sleep mode. However, the extension map data is stored in the memory device 100 whenever the extension map data corresponding to the map segment is generated. Accordingly, the mapping data management unit 220 may generate extension mapping data other than the extension mapping data stored in the memory device 100. Accordingly, mapping data other than the extension mapping data stored in the memory device 100 can be generated.

Fig. 16 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 1, 8, and 9) according to an embodiment of the present disclosure.

Referring to fig. 16, at step S1601, the mapping data determination unit 210 may receive a mapping data read request MR _ REQ from the host 300. The mapping data read request MR _ REQ may be a request for reading the extended mapping data stored in the memory device 100. The extended mapping data may include mapping information indicating a mapping relationship between the logical block address LBA and the physical block address PBA, and additional field information. The additional field information may include information on the number of times the extension mapping data has been updated and/or information for error correction of the extension mapping data.

At step S1603, the mapping data determination unit 210 may check the bitmap information BM _ INF received from the memory device 100. In various embodiments, the mapping data determination unit 210 may output the bitmap request BM _ REQ to the memory device 100 based on the mapping data read request MR _ REQ received from the host 300. The mapping data determining unit 210 may receive bitmap information BM _ INF corresponding to the bitmap request BM _ REQ. The mapping data managing unit 210 may determine whether to generate extended mapping data based on the bitmap information BM _ INF.

At step S1605, the mapping data determining unit 210 may determine whether the determination bit is a logic low level "0". The mapping data determining unit 210 may determine whether the decision bit includes a default value. The decision bits may be bits included in a bitmap. The determination bit may be a bit indicating whether all of the plurality of extension map data corresponding to the map segment has been generated.

The mapping data determining unit 210 may receive bitmap information BM _ INF from the memory device 100. Further, the mapping data determining unit 210 may determine whether the extended mapping data corresponding to the mapping data read request MR _ REQ of the host 300 has been stored in the memory device 100 using the determination bit. When it is determined that the judged bit is not "0", that is, when the judged bit is "1" (S1605, no), the process proceeds to step S1609. When it is determined that the determination position is "0" (S1605, yes), the process proceeds to step S1607.

At step S1607, the mapping data management unit 220 may output the generation incomplete response GNC _ RES to the host pc 300. In various embodiments, in the case where the bitmap information BM _ INF includes information indicating that map data has not been generated, all or some of the plurality of extension map data corresponding to the map data read request MR _ REQ may not be stored in the memory device 100. In a case where all or some of the plurality of extension mapping data corresponding to the mapping data read request MR _ REQ have not been stored in the memory device 100, the mapping data determining unit 210 may output generation information GE _ INF including information indicating that generation of the extension mapping data has not been completed.

When receiving the generation information GE _ INF from the mapping data determining unit 210, the mapping data managing unit 220 may output the generation incomplete response GNC _ RES to the host 300. In one embodiment, the generation information GE _ INF may include information indicating that all of a plurality of extension mapping data corresponding to the mapping data read request MR _ REQ received from the host 300 or the internal operation of the memory controller 200 have not been generated yet. The mapping data management unit 220 may output a generation incomplete response GNC _ RES indicating that all of the plurality of extension mapping data corresponding to the request received from the host 300 or the internal operation of the memory controller 200 have not been generated to the host 300.

At step S1609, the mapping data management unit 220 may output a mapping data read command MDR _ CMD to the memory device 100. In various embodiments, the mapping data management unit 220 may output a mapping data read command MDR _ CMD for outputting extended mapping data corresponding to the mapping data read request MR _ REQ of the host 300. The mapping data read command MDR _ CMD may be determined based on the generation information GE _ INF.

When the generation information GE _ INF includes information indicating that all of the plurality of extension mapping data corresponding to the request of the host 300 have been stored, the mapping data management unit 220 may output a mapping data read command MDR _ CMD to the memory device 100. The mapping data management unit 220 may output an address where the extended mapping data is stored to the memory device 100 together with the mapping data read command MDR _ CMD.

At step S1611, the mapping data managing unit 220 may receive the mapping data. In various embodiments, the mapping data management unit 220 may receive the extended mapping data from the memory device 100. In one embodiment, the mapping data management unit 220 may receive a plurality of extension mapping data from the memory device 100.

In one embodiment, the mapping data management unit 220 may receive the extended mapping data corresponding to the mapping data read command MDR _ CMD from the memory device 100. The mapping data managing unit 220 may receive the extended mapping data based on the mapping segment. When the extension mapping data is received from the memory device 100, the mapping data managing unit 220 may receive all of the plurality of extension mapping data included in one mapping section and then receive the plurality of extension mapping data included in a subsequent mapping section.

At step S1613, the mapping data management unit 220 may output the extended mapping data received from the memory device 100 to the host 300. The mapping data managing unit 220 may receive the extended mapping data corresponding to the mapping data read request MR _ REQ received from the host 300. The mapping data management unit 220 may output the extended mapping data to the host 300 based on the mapping segment. In other words, in the same manner as when the extension map data is received from the memory device 100, the map data management unit 220 may output all of the plurality of extension map data included in one map segment, and then output the plurality of extension map data included in a subsequent map segment to the host 300.

In one embodiment, the host 300 may store the extended mapping data received from the mapping data management unit 220 in the host memory 310. The extension map data may be stored in the host memory 310 based on the map segment. Host 300 can receive the expanded mapping data corresponding to the mapped segment from mapping data management unit 220 and store the expanded mapping data corresponding to the mapped segment in host memory 310. Host 300 may store expanded mapping data corresponding to one mapped segment and then store expanded mapping data corresponding to a subsequent mapped segment.

Fig. 17 is a diagram illustrating a memory controller 1000 (e.g., the memory controller of fig. 1) according to an embodiment of the present disclosure.

Memory controller 1000 is coupled to a host (e.g., host 300 of FIG. 1) and a memory device (e.g., memory device 100 of FIG. 1). In response to a request from the host 300, the memory controller 1000 may access the memory device 100. For example, the memory controller 1000 may control write operations, read operations, erase operations, and background operations of the memory device 100. Memory controller 1000 may provide an interface between memory device 100 and host 300. Memory controller 1000 may drive firmware for controlling memory device 100.

Referring to fig. 17, the memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

Bus 1070 may provide a channel between the components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and perform logical operations. The processor 1010 may communicate with the host 300 through a host interface 1040 and may communicate with the memory device 100 through a memory interface 1060. Additionally, processor 1010 may communicate with memory buffer 1020 through buffer control circuitry 1050. The processor 1010 may control the operation of the storage device by using the memory buffer 1020 as an operation memory, a cache memory, or a buffer memory.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by host 300 to Physical Block Addresses (PBAs) through the FTL. The FTL can receive the LBA and convert the LBA to a PBA using a mapping table. The address mapping method using the FTL can be modified in various ways according to the unit of mapping. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

Processor 1010 may randomize data received from host 300. For example, processor 1010 may randomize data received from host 300 using a random seed. The randomized data may be provided to the memory device 100 as the stored data to be stored and may be programmed to the memory cell array.

During a read operation, processor 1010 may randomize data received from memory device 100. For example, the processor 1010 may use the derandomization seed to derandomize data received from the memory device 100. The derandomized data can be output to the host 300.

In one embodiment, the processor 1010 may drive software or firmware to perform the randomization or derandomization operations.

Memory buffer 1020 may be used as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands to be executed by processor 1010. Memory buffer 1020 may store data to be processed by processor 1010. Memory buffer 1020 may include static ram (sram) or dynamic ram (dram).

The ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform an ECC encoding operation based on data to be written to the memory device 100 through the memory interface 1060. The ECC encoded data may be sent to the memory device 100 through the memory interface 1060. The ECC circuit 1030 may perform ECC decoding operations on data received from the memory device 100 through the memory interface 1060. For example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

Host interface 1040 may communicate with host 300 under the control of processor 1010. The host interface 1040 may perform communication using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and reduced load DIMM (lrdimm) communication methods.

Buffer control circuitry 1050 may control memory buffer 1020 under the control of processor 1010.

The memory interface 1060 may communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device 100 through a channel.

For example, memory controller 1000 may include neither memory buffer 1020 nor buffer control circuitry 1050.

For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read only memory) provided in the memory controller 1000. Alternatively, processor 1010 may load code from memory device 100 through memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data in the memory controller 1000. The control bus may transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be separate from each other and may not interfere with each other nor affect each other. The data bus may be coupled to the ECC circuit 1030, the host interface 1040, the buffer control circuit 1050, and the memory interface 1060. The control bus may be coupled to the processor 1010, the memory buffer 1020, the host interface 1040, the buffer control circuit 1050, and the memory interface 1060.

Fig. 18 is a block diagram illustrating a memory card system 2000 including a storage device according to an embodiment of the present disclosure.

Referring to fig. 18, the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is coupled to a memory device 2200. The memory device 2200 is accessible by the memory controller 2100. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2100 and a host (e.g., host 300 of fig. 1). The memory controller 2100 may drive firmware for controlling the memory device 2200. The memory device 2200 may be embodied in the same manner as the memory device 100 described with reference to fig. 10.

In one embodiment, memory controller 2100 may include components such as a Random Access Memory (RAM), a processing unit, a host interface, and memory interface and ECC circuitry.

The memory controller 2100 may communicate with external devices through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a particular communication protocol. In one embodiment, the memory controller 2100 may communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory express (NVMe) protocols. In one embodiment, the connector 2300 may be defined by at least one of the various communication protocols described above.

In one embodiment, memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable rom (eeprom), NAND flash, NOR flash, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin transfer torque magnetic RAM (STT-MRAM).

In one embodiment, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), a compact flash Card (CF), a smart media card (e.g., SM or SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, or MMCmicro), a Secure Digital (SD) card (e.g., SD, miniSD, microSD, or SDHC), or a universal flash memory (UFS).

Fig. 19 is a block diagram illustrating a Solid State Drive (SSD) system 3000 including storage devices according to an embodiment of the disclosure.

Referring to fig. 19, SSD system 3000 may include host 3100 and SSD 3200. SSD 3200 may exchange signals SIG with host 3100 via signal connector 3001 and may receive power PWR via power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

In one embodiment, SSD controller 3210 may perform the functions of memory controller 200 described above with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In one embodiment, signal SIG may be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of various interfaces, such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI-express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory express (NVMe) interface.

The auxiliary power supply 3230 may be coupled to the host 3100 via a power connector 3002. The auxiliary power supply 3230 may be supplied with power PWR from the host 3100, and may be charged by the power PWR. When the power supply from the host 3100 cannot be smoothly performed, the auxiliary power supply 3230 may supply the power of the SSD 3200. In one embodiment, auxiliary power supply 3230 may be located inside SSD 3200 or outside SSD 3200. For example, the auxiliary power supply 3230 may be provided in a main board and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 20 is a block diagram illustrating a user system 4000 including a storage device according to an embodiment of the present disclosure.

Referring to fig. 20, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may run components included in the user system 4000, an Operating System (OS), or user programming. In one embodiment, the application processor 4100 may include a controller, interface, graphics engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile RAM (such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, and LPDDR3 SDRAM) or non-volatile RAM (such as PRAM, ReRAM, MRAM, and FRAM). In one embodiment, the application processor 4100 and the memory module 4200 can be packaged based on a Package On Package (POP) and then can be provided as a single semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications, such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, bluetooth, or Wi-Fi communications. In one embodiment, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data therein. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. In one embodiment, the memory module 4400 may be implemented as a non-volatile semiconductor memory device, such as a phase change ram (pram), a magnetic ram (mram), a resistive ram (rram), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In one embodiment, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

In one embodiment, the memory module 4400 may include a plurality of non-volatile memory devices, and each of the plurality of non-volatile memory devices may operate in the same manner as the memory device 100 described above with reference to fig. 10-13. The memory module 4400 may operate in the same manner as the memory device 50 described above with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or outputting data to an external device. In one embodiment, the user interface 4500 can include a user input interface such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. The user interface 4500 may further include a user output interface such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an active matrix OLED (amoled) display device, an LED, a speaker, and a motor.

Various embodiments of the present disclosure may provide a memory controller capable of efficiently generating mapping data, and a method of operating the memory controller.

Although embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.

The scope of the disclosure, therefore, is not to be restricted except in light of the foregoing description, by the appended claims and their equivalents.

In the embodiments discussed above, all steps may be selectively performed or skipped. Additionally, the steps in each embodiment may not always be performed in a regular order. Furthermore, the embodiments disclosed in the present specification and drawings are intended to help those of ordinary skill in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains will readily appreciate that various modifications are possible based on the technical scope of the present disclosure.

The embodiments of the present disclosure have been described with reference to the accompanying drawings, and specific terms or words used in the description should be construed according to the spirit of the present disclosure without limiting the subject matter of the present disclosure. It should be understood that many variations and modifications of the basic inventive concepts described herein will still fall within the spirit and scope of the present disclosure, as defined by the appended claims and their equivalents.