阅读说明：本技术 存储装置及操作存储装置的方法 (Storage device and method for operating storage device ) 是由 边谕俊 于 2019-10-25 设计创作，主要内容包括：本申请可提供一种存储器控制器,该存储器控制器被配置成控制存储器装置。该存储器控制器可包括：突然断电(SPO)感测单元,被配置成感测SPO事件并基于该SPO事件生成感测信息；SPO级别确定单元,被配置成基于感测信息来确定SPO级别；系统数据控制单元,被配置成基于SPO级别来确定待写入的系统数据和写入该系统数据的写入时间点,并且生成用于在所确定的写入时间点存储系统数据的命令；以及系统数据存储装置,被配置成存储系统数据。该系统数据存储装置可包括非易失性存储器。(The present application may provide a memory controller configured to control a memory device. The memory controller may include: an abrupt power off (SPO) sensing unit configured to sense an SPO event and generate sensing information based on the SPO event; an SPO level determination unit configured to determine an SPO level based on the sensing information; a system data control unit configured to determine system data to be written and a writing time point at which the system data is written based on the SPO level, and generate a command for storing the system data at the determined writing time point; and a system data storage configured to store system data. The system data storage may include non-volatile memory.)

1. A memory controller that controls a memory device, the memory controller comprising:

an abrupt power off sensing unit, i.e., an SPO sensing unit, sensing an SPO event and generating sensing information based on the SPO event;

an SPO level determination unit that determines an SPO level based on the sensing information;

a system data control unit determining system data to be written and a writing time point at which the system data is written based on the SPO level, and generating a command for storing the system data at the determined writing time point; and

a system data storage device storing the system data,

wherein the system data storage comprises non-volatile memory.

2. The memory controller of claim 1,

wherein the SPO sensing unit stores a power-off time in the memory device when a power supply is turned off, and

wherein the SPO sense unit receives the power-off time from the memory device when the power is turned on and generates the sensing information based on the power-off time.

3. The memory controller of claim 1,

wherein when the sensed information includes information regarding a number of times the SPO event has occurred within a reference time,

as the number of times the SPO event has occurred increases, the SPO level increases.

4. The memory controller of claim 1,

wherein when the sensing information includes information on a period in which the SPO event occurs, the SPO level is increased as the period in which the SPO event occurs is decreased.

5. The memory controller of claim 1, wherein the number of types of system data to be written increases as the SPO level increases.

6. The memory controller of claim 1,

wherein when the SPO level increases, a time between write time points at which the system data is written decreases, and

wherein a time between write time points at which the system data is written increases as the SPO level decreases.

7. The memory controller of claim 1, wherein the SPO level determination unit updates the SPO level in response to a request of a host.

8. The memory controller of claim 1, wherein the SPO level determination unit updates the SPO level after a predetermined reference time elapses.

9. The memory controller of claim 1,

wherein when the SPO event occurs after the system data has been stored,

performing a data recovery operation using the system data stored immediately prior to the occurrence of the SPO event.

10. The memory controller of claim 1, wherein the command to store the system data is generated prior to performing a write operation of the memory device.

11. A method of operating a memory controller that controls a memory device, the method comprising:

sensing an sudden power off event (SPO event) and generating sensing information based on the SPO event;

determining an SPO level based on the sensed information;

determining system data to be written and a writing time point of the system data based on the SPO level; and is

Generating a command for storing the system data at the determined writing time point.

12. The method of claim 11, wherein generating the sensing information comprises:

storing a power-off time in the memory device when the power supply is turned off, and

when the power is turned on, the power-off time is received from the memory device, and the sensing information is generated based on the power-off time.

13. The method of claim 11, wherein the first and second light sources are selected from the group consisting of,

wherein generating the sensing information comprises: generating information on the number of times the SPO event has occurred within a reference time, and

wherein determining the SPO level comprises: determining the SPO level such that the SPO level increases as the number of times the SPO event has occurred increases.

14. The method of claim 11, wherein the first and second light sources are selected from the group consisting of,

wherein generating the sensing information comprises: generating information about a period of time during which the SPO event occurred, and

wherein determining the SPO level comprises: determining the SPO level such that the SPO level increases as the period of time during which the SPO event occurs decreases.

15. The method of claim 11, wherein in determining system data to be written and the point in time of writing,

when the SPO level increases, the number of types of system data to be written increases.

16. The method of claim 11, wherein in determining system data to be written and the point in time of writing,

when the SPO level is increased, the time between write time points at which the system data is written is decreased, and

when the SPO level decreases, the time between write time points at which the system data is written increases.

17. The method of claim 11, wherein determining the SPO level comprises: the updated SPO level is determined in response to a request by the host.

18. The method of claim 11, wherein determining the SPO level comprises: the updated SPO level is determined after a predetermined reference time has elapsed.

19. The method of claim 11, wherein generating the command is performed prior to performing a write operation of the memory device.

20. A memory device, comprising:

a memory device storing data;

a memory controller sensing an SPO event that is an abrupt power-off event and determining an SPO level, and determining system data to be written and a write time point at which the system data is written based on the SPO level; and

a system data storage device storing the system data,

wherein the system data storage comprises non-volatile memory.

Technical Field

Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a memory device and a method of operating the same.

Background

Typically, the storage device stores data under the control of a host, such as a computer, smart phone or smart tablet. Examples of the storage device may be classified into a device that stores data in a magnetic disk, such as a Hard Disk Drive (HDD), and a device that stores data in a semiconductor memory, particularly a nonvolatile memory, such as a Solid State Drive (SSD) or a memory card.

The storage device may include a memory device to store data, and a memory controller configured to store data in the memory device. Memory devices can be classified into volatile memory and non-volatile memory. Representative examples of non-volatile memory may include read-only memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change random access memory (PRAM), magnetic ram (mram), resistive ram (rram), and ferroelectric ram (fram).

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory device capable of changing a system data write period and a method of operating the same.

Embodiments of the present disclosure may provide a memory controller configured to control a memory device, the memory controller including: an abrupt power off (SPO) sensing unit configured to sense an SPO event and generate sensing information based on the SPO event; an SPO level determination unit configured to determine an SPO level based on the sensing information; a system data control unit configured to determine system data to be written and a writing time point at which the system data is written based on the SPO level, and generate a command for storing the system data at the determined writing time point; and a system data storage configured to store system data, wherein the system data storage includes a non-volatile memory.

Embodiments of the present disclosure may provide a method of operating a memory controller configured to control a memory device, the method comprising: sensing a Sudden Power Off (SPO) event and generating sensing information based on the SPO event; determining an SPO level based on the sensed information; determining system data to be written and a writing time point at which the system data is written based on the SPO level; and generating a command for storing the system data at the determined writing time point.

Embodiments of the present disclosure may provide a memory device, including: a memory device configured to store data; a memory controller configured to sense a Sudden Power Off (SPO) event and determine a SPO level, and determine system data to be written and a writing time point at which the system data is written based on the SPO level; and a system data storage configured to store system data, wherein the system data storage includes a non-volatile memory.

Embodiments of the present disclosure may provide a memory device, including: a memory device configured to store data; and a controller configured to detect an occurrence of Sudden Power Off (SPO), determine a writing period based on the occurrence of SPO, and store system data in the memory device for the determined writing period, wherein the writing period is variably adjusted based on the occurrence of SPO.

Drawings

Fig. 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

FIG. 3 is a diagram illustrating a memory controller including a power-down-burst (SPO) storage device, according to an embodiment of the present disclosure.

Fig. 4 is a diagram illustrating an operation of updating a Sudden Power Off (SPO) occurrence count number according to an embodiment of the present disclosure.

Fig. 5 is a diagram illustrating a method of updating a Sudden Power Off (SPO) occurrence period and a SPO occurrence count number according to an embodiment of the present disclosure.

Fig. 6 is a diagram illustrating system data according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating a method of determining a Sudden Power Off (SPO) level according to an embodiment of the present disclosure.

Fig. 8 is a diagram illustrating a method of determining a Sudden Power Off (SPO) level according to an embodiment of the present disclosure.

Fig. 9 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 10 is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

Fig. 11 is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

Fig. 12 is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

Fig. 13 is a diagram illustrating an operation of a memory controller according to an embodiment of the present disclosure.

Fig. 14 is a diagram illustrating an operation of a memory controller according to an embodiment of the present disclosure.

Fig. 15 is a diagram illustrating an operation of a memory device according to an embodiment of the present disclosure.

Fig. 16 is a diagram illustrating an operation of a memory controller according to an embodiment of the present disclosure.

Fig. 17 is a diagram illustrating an operation of a memory controller according to an embodiment of the present disclosure.

Fig. 18 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

Fig. 19 is a block diagram illustrating a memory card system including a storage device according to an embodiment of the present disclosure.

Fig. 20 is a block diagram illustrating a Solid State Drive (SSD) system including a storage device according to an embodiment of the disclosure.

Fig. 21 is a block diagram illustrating a user system including a storage device according to an embodiment of the present disclosure.

Detailed Description

The specific structural and functional descriptions of the embodiments of the present disclosure that are incorporated in this specification or application are intended to be illustrative only of the embodiments of the present disclosure. The description should not be construed as limited to the embodiments described in this specification or application.

The present disclosure will now be described in detail based on examples. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein but should be construed to cover modifications, equivalents, or alternatives falling within the spirit and scope of the present disclosure. It will be understood, however, that the description is not intended to limit the disclosure to those exemplary embodiments, and the disclosure is not intended to cover the exemplary embodiments, but also various alternatives, modifications, equivalents, and other embodiments, which fall within the spirit and scope of the disclosure.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Also, a second element may be referred to as a first element.

It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may be present between the element and the other element. In contrast, it will be understood that when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present. Other expressions describing the relationship between elements, such as "between … …", "directly between … …", "adjacent" or "directly adjacent", should be interpreted in the same way.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

A detailed description of functions and configurations well known to those skilled in the art will be omitted so as not to obscure the subject matter of the present disclosure. This is intended to omit unnecessary description in order to make the subject matter of the present disclosure clear.

Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the disclosure are shown, so that those skilled in the art can readily implement the technical solutions of the present disclosure.

Fig. 1 is a block diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200.

The storage device 50 may be a device configured to store data under the control of a host 300 such as: a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a Television (TV), a tablet Personal Computer (PC), or a vehicle infotainment system.

The storage device 50 may be manufactured as any of various types of storage devices according to a host interface as a communication system with the host 300. For example, the storage device 50 may be configured by any of various types of storage devices such as: SSD, MMC, eMMC, RS-MMC or micro MMC type multimedia cards, SD, mini SD, micro SD type secure digital cards, Universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, Personal Computer Memory Card International Association (PCMCIA) card type storage devices, Peripheral Component Interconnect (PCI) card type storage devices, PCI express (PCI-e or PCIe) type storage devices, Compact Flash (CF) cards, smart media cards and memory sticks.

The memory device 50 may be manufactured in any of a variety of package types. For example, the memory device 50 may be manufactured in the form of any one of a variety of packaging types, such as: a Package On Package (POP) type, a System In Package (SIP) type, a System On Chip (SOC) type, a multi-chip package (MCP) type, a Chip On Board (COB) type, a wafer-level manufacturing package (WFP) type, and a wafer-level stack package (WSP) type.

The memory controller 200 may control the overall operation of the memory device 50.

When power is applied to the storage device 50, the memory controller 200 may execute the firmware. In the case where the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a Flash Translation Layer (FTL) to control communication between the host 300 and the memory device 100.

The memory controller 200 may include a power down burst (SPO) sensing unit 210. The SPO sensing unit 210 may sense the SPO event. The SPO event may be a phenomenon in which the power supply is suddenly turned off. If the power is suddenly turned off, the SPO sensing unit 210 may control the memory device 100 to store a point of time when the power is turned off. The point of TIME when the power is turned off may be a power-off TIME PO _ TIME. The power down TIME PO _ TIME may be stored in the memory device 100 and/or the memory controller 200.

If the power is turned on again after the power is turned off, SPO sensing unit 210 may receive a power-off TIME PO _ TIME from memory device 100. Accordingly, the SPO sensing unit 210 may calculate the SPO duration based on the duration from the time point when the power is turned off to the time point when the power is turned on.

The SPO sensing unit 210 may sense the SPO event and generate sensing information SE _ INF. In various embodiments, the SPO sensing unit 210 may generate the sensing information SE _ INF based on the SPO duration. The sensing information SE _ INF may include at least one of the number of times the SPO event has occurred within the reference time t _ ref and the SPO occurrence period SPO _ PER. The SPO occurrence period SPO _ PER may be an average value of the SPO duration.

Memory controller 200 may include SPO storage 211. SPO storage 211 may store the power down TIME PO _ TIME sensed by SPO sensing unit 210. Further, the SPO storage device 211 may store SPO occurrence TIME, which is the TIME between the stored power-off TIMEs PO _ TIME.

In an embodiment, the SPO storage 211 may be formed of non-volatile memory. Therefore, even if the power is turned off, the power-off TIME PO _ TIME and the SPO occurrence TIME stored in the SPO storage device 211 can be retained in the SPO storage device 211. Even if the power is turned off, the power-off TIME PO _ TIME and the SPO occurrence TIME can be stored in the SPO storage device 211.

The memory controller 200 may include an SPO level determination unit 220. The SPO level determination unit 220 may receive sensing information SE _ INF from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF. From the SPO LEVEL SPO _ LEVEL, the system DATA SYS _ DATA to be written and the time point at which the system DATA SYS _ DATA is written (i.e., the writing time point) can be determined.

In an embodiment, the SPO LEVEL SPO _ LEVEL may increase as the number of SPO occurrence counts SPO _ NUM increases. The SPO occurrence count number SPO _ NUM may be the number of times that an SPO event has occurred within the reference time t _ ref. Conversely, as the number of SPO occurrence counts, SPO _ NUM, decreases, the SPO LEVEL, SPO _ LEVEL, may decrease.

In an embodiment, the SPO LEVEL SPO _ LEVEL may increase as the SPO occurrence period SPO _ PER decreases. In contrast, as the SPO occurrence period SPO _ PER increases, the SPO LEVEL SPO _ LEVEL may decrease.

Based on the SPO LEVEL SPO _ LEVEL, the type of system DATA SYS _ DATA to be stored in the memory controller 200 and/or the memory device 100 may be determined. The area of the memory controller 200 or the memory device 100 where the system DATA SYS _ DATA is to be stored may include a nonvolatile memory cell or a nonvolatile memory.

Further, based on the SPO LEVEL SPO _ LEVEL, the period and/or the count number of writing the system DATA SYS _ DATA into the nonvolatile memory cell may be determined. The system DATA SYS _ DATA may comprise at least one of HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, firmware-related DATA FW _ DATA, and mapping-related DATA MAP _ DATA.

The memory controller 200 may include a system data control unit 230. The system data control unit 230 may receive the SPO LEVEL SPO _ LEVEL from the SPO LEVEL determination unit 220.

The system DATA control unit 230 may determine the type of the system DATA SYS _ DATA to be written based on the SPO LEVEL SPO _ LEVEL. In various embodiments, as the SPO LEVEL SPO _ LEVEL increases, the number of types of system DATA SYS _ DATA to be written may increase. Conversely, as the SPO LEVEL SPO _ LEVEL decreases, the number of types of system DATA SYS _ DATA to be written may decrease.

The system DATA control unit 230 may determine a writing time point at which the system DATA SYS _ DATA is written based on the SPO LEVEL SPO _ LEVEL. In various embodiments, as the SPO LEVEL SPO _ LEVEL increases, the number of times the system DATA SYS _ DATA is written to the nonvolatile memory cells of the memory controller 200 or the memory device 100 may increase, and the time between writing time points may decrease. In various embodiments, as the SPO LEVEL SPO _ LEVEL decreases, the number of times the system DATA SYS _ DATA is written to the nonvolatile memory cell may decrease, and the time between writing time points may increase.

The system DATA control unit 230 may write the system DATA SYS _ DATA into the memory device 100 and/or the memory controller 200 based on the SPO LEVEL SPO _ LEVEL. The area to be written with the system DATA SYS _ DATA may include nonvolatile memory cells.

The system DATA control unit 230 may write the system DATA SYS _ DATA into the nonvolatile memory unit at a write time point determined based on the SPO LEVEL SPO _ LEVEL. In an embodiment, the system DATA control unit 230 may write the system DATA SYS _ DATA into the system DATA storage 240. In an embodiment, the system DATA control unit 230 may write the system DATA SYS _ DATA into the DATA storage 130 of the memory device 100. In various embodiments, the memory device 100 may receive the system DATA SYS _ DATA from the system DATA control unit 230 through an interface (e.g., the memory interface 1060 of fig. 18) of the memory controller 200 and a peripheral circuit (e.g., the DATA input/output circuit 124 of fig. 9) of the memory device 100 and store the received system DATA SYS _ DATA in the DATA storage device 130.

When the system DATA writing condition is satisfied, the system DATA control unit 230 may write the system DATA SYS _ DATA. In various embodiments, the system DATA SYS _ DATA may be written when a memory block storing DATA in the memory device 100 is changed. Therefore, when the map DATA is updated, the system DATA SYS _ DATA may be written. Further, when mapping information (for example, physical-to-logical (P2L) mapping information) indicating a mapping relationship between a Physical Block Address (PBA) and a Logical Block Address (LBA) is updated, system DATA SYS _ DATA may be written.

Accordingly, if the system DATA writing condition is satisfied, the system DATA control unit 230 may write the system DATA SYS _ DATA determined based on the SPO LEVEL SPO _ LEVEL at a writing time point determined based on the SPO LEVEL SPO _ LEVEL.

The system DATA control unit 230 may store the system DATA SYS _ DATA to cope with the SPO event in which the power is turned off at an unspecified point in time. If the system DATA SYS _ DATA is frequently stored in the nonvolatile memory, the amount of changed system DATA may be reduced. Therefore, since the amount of the system DATA SYS _ DATA to be restored is reduced, the restoration time is reduced, so that the time required to perform the startup can be reduced. However, if the system DATA SYS _ DATA is frequently stored in the nonvolatile memory, the performance of the storage device 50 may be degraded. The operating efficiency of the memory device 50 may be reduced. Accordingly, the system DATA control unit 230 may determine an optimal writing time point of the system DATA SYS _ DATA and a type of the system DATA SYS _ DATA to be stored to cope with the SPO event.

In an embodiment, memory controller 200 may include system data storage 240. In an embodiment, memory controller 200 may not include system data storage 240.

Where memory controller 200 includes system data storage 240, system data storage 240 may include volatile memory units or nonvolatile memory units. If system data storage 240 includes non-volatile memory cells, system data storage 240 may include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM or PCRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), or spin torque transfer magnetoresistive RAM (STT-MRAM).

In the case where the system DATA storage 240 includes a nonvolatile memory or a nonvolatile memory unit, the system DATA control unit 230 may store the system DATA SYS _ DATA in the system DATA storage 240. Since the system DATA storage 240 includes a nonvolatile memory cell, the system DATA SYS _ DATA stored in the system DATA storage 240 may be retained even if the power is turned off. Accordingly, if the power is turned on again after the power is turned off, the memory device 50 including the memory controller 200 and the memory device 100 may perform a recovery operation based on the system DATA SYS _ DATA stored in the system DATA storage 240.

In an embodiment, system data storage 240 may be disposed external to memory controller 200. The system data storage 240 may be included in the storage 50 as a component provided independently of the memory controller 200.

In an embodiment, system data storage 240 may be included in memory device 100.

Data may be stored in the memory device 100. The memory device 100 may operate under the control of the memory controller 200. Memory device 100 may include a memory cell array including a plurality of memory cells configured to store data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In an embodiment, each page may be a unit of storing data in the memory device 100 or reading stored data from the memory device 100. Each memory block may be a unit of erase data.

In an embodiment, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), a low power double data rate 4(LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a low power ddr (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, Resistive Random Access Memory (RRAM), phase change memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or spin torque transfer random access memory (STT-RAM). In this specification, the memory device 100 is a NAND flash memory.

In an embodiment, the memory device 100 may be implemented in a three-dimensional array structure. The present disclosure is applicable not only to a flash memory in which a charge storage layer is formed of a conductive Floating Gate (FG), but also to a charge extraction flash (CTF) memory in which a charge storage layer is formed of an insulating layer.

In an embodiment, each of the memory cells included in the memory device 100 may be formed of a single-layer cell (SLC) capable of storing one bit of data. Alternatively, each of the memory cells included in the memory device 100 may be formed of a multi-layer cell (MLC) capable of storing two-bit data, a triple-layer cell (TLC) capable of storing three-bit data, or a quadruple-layer cell (QLC) capable of storing four-bit data.

The memory device 100 may receive a command and an address from the memory controller 200 and access a region of the memory cell array selected by the address. The memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write (or program) operation, a read operation, and an erase operation. During a programming operation, the memory device 100 may program data to a region selected by an address. During a read operation, the memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data from an area selected by an address.

The memory device 100 may perform a program operation or an erase operation using the set operation voltage under the control of the memory controller 200.

Memory device 100 may include a data storage device 130. In an embodiment, the DATA storage device 130 may store the system DATA SYS _ DATA received from the system DATA control unit 230. In various embodiments, the DATA storage device 130 may receive the system DATA SYS _ DATA from the system DATA control unit 230 through peripheral circuits (e.g., the DATA input/output circuit 124 of fig. 9) of the memory device 100 and an interface (e.g., the memory interface 1060 of fig. 18) of the memory controller 200. Note, however, that description will be made that the DATA storage device 130 can store the system DATA SYS _ DATA received from the system DATA control unit 230. Data storage 130 may include non-volatile memory cells. The DATA storage device 130 may receive a command from the system DATA control unit 230 to store the system DATA SYS _ DATA. The DATA storage device 130 may store the system DATA SYS _ DATA based on a command received from the system DATA control unit 230. The data storage 130 may have the same function as the system data storage 240.

Accordingly, if the power is turned on again after the power is turned off, the system DATA SYS _ DATA stored in the DATA storage device 130 may be provided to the memory controller 200. The memory controller 200 may receive the system DATA SYS _ DATA and perform a recovery operation.

In an embodiment, the memory controller 200 may receive data and a Logical Block Address (LBA) from the host 300, and convert the LBA to a Physical Block Address (PBA) indicating an address of a memory unit storing the data, the memory unit being included in the memory device 100. In addition, the memory controller 200 may store mapping information indicating a mapping relationship between the LBA and the PBA in the buffer memory.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a programming operation, the memory controller 200 may provide programming commands, PBAs, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and PBA to the memory device 100.

In an embodiment, the memory controller 200 may autonomously generate and transmit program commands, addresses, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory device 100 in an interleaved manner to enhance the operation performance.

The host 300 may communicate with the storage device 50 using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and reduced load DIMM (lrdimm).

FIG. 2 is a diagram illustrating a memory controller, such as memory controller 200 of FIG. 1, according to an embodiment of the present disclosure.

Referring to fig. 2, the memory controller 200 may include an SPO sensing unit 210, an SPO level determining unit 220, a system data control unit 230, and a system data storage 240. In an embodiment, memory controller 200 may not include system data storage 240. In fig. 2, the SPO storage device 211 among the components of the memory controller 200 is omitted.

The SPO sensing unit 210 may sense the SPO event. The SPO event may be a phenomenon in which the power supply is suddenly turned off. The SPO sensing unit 210 may sense the SPO event and store a time point at which the SPO event is sensed in the memory device 100. In various embodiments, if the power is suddenly turned off, i.e., if an SPO event occurs, the SPO sensing unit 210 may be controlled such that a point of time at which the power is turned off is stored in the memory device 100. The point of TIME when the power is turned off may be a power-off TIME PO _ TIME. The power down TIME PO _ TIME may be stored in the memory device 100 and/or the memory controller 200. In this figure, the power-down TIME PO _ TIME is stored in the memory device 100. Thus, when power is turned off, SPO sensing unit 210 may store the power-off TIME PO _ TIME in memory device 100.

The SPO sensing unit 210 may receive the power down TIME PO _ TIME from the memory device 100. In various embodiments, if power is turned on again after an SPO event, SPO sensing unit 210 may receive a power down TIME PO _ TIME from memory device 100. When the power is turned on, the SPO sensing unit 210 may receive the power-off TIME PO _ TIME and generate sensing information SE _ INF. The sensing information SE _ INF may include information about the number of times that SPO events have occurred within the reference time t _ ref. Further, the sensing information SE _ INF may include information on the SPO occurrence period.

Accordingly, the SPO sensing unit 210 may generate the sensing information SE _ INF based on a duration from a time point when the power is turned off to a time point when the power is turned on. The sensing information SE _ INF may be generated based on an average of the durations of time that the power-off state is maintained due to the SPO event.

The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL. In various embodiments, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL SPO _ LEVEL may be determined based on information about the number of times an SPO event has occurred within the reference time t _ ref. Alternatively, the SPO LEVEL SPO _ LEVEL may be determined according to the SPO occurrence period. The SPO occurrence period may be an average of the power-off duration of the SPO events that have occurred a reference number of times.

In an embodiment, the sensing information SE _ INF may comprise information about the number of times an SPO event has occurred within the reference time t _ ref. Here, the SPO LEVEL SPO _ LEVEL may increase as the number of times that SPO events have occurred increases. Conversely, as the number of SPO events that have occurred decreases, the SPO LEVEL SPO _ LEVEL may decrease.

In an embodiment, the sensing information SE _ INF comprises information about the period of occurrence of SPO. Here, as the SPO occurrence period decreases, the SPO LEVEL SPO _ LEVEL may increase. Conversely, as the SPO occurrence period increases, the SPO LEVEL SPO _ LEVEL may decrease.

Thus, the higher the SPO LEVEL SPO _ LEVEL, the more frequent the SPO events occur. Conversely, if the SPO LEVEL SPO _ LEVEL is sufficiently reduced, SPO events may occur infrequently. Therefore, as the SPO LEVEL SPO _ LEVEL increases, the time between writing time points of the system DATA SYS _ DATA is written decreases. As the SPO LEVEL SPO _ LEVEL decreases, the time between write time points at which the system DATA SYS _ DATA is written increases.

Based on the SPO LEVEL SPO _ LEVEL, the type and the write count number of the system DATA SYS _ DATA to be stored in the memory controller 200 and/or the memory device 100 may be determined. The system DATA SYS _ DATA may comprise at least one of HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, firmware-related DATA FW _ DATA, and mapping-related DATA MAP _ DATA.

In various embodiments, as the SPO LEVEL SPO _ LEVEL increases, the number of times the system DATA SYS _ DATA is written may increase. As the SPO LEVEL SPO _ LEVEL increases, the time between write time points of the system DATA SYS _ DATA may be written may decrease. Conversely, as the SPO LEVEL SPO _ LEVEL decreases, the number of times the system DATA SYS _ DATA is written may decrease. As the SPO LEVEL SPO _ LEVEL decreases, the time between write time points at which the system DATA SYS _ DATA is written may increase.

Therefore, as the SPO LEVEL SPO _ LEVEL is lowered, the number of times of writing the system DATA SYS _ DATA is reduced, so that the efficiency of the memory device can be improved. The performance of the memory device may be enhanced by adjusting the number of times the system DATA SYS _ DATA is written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of times the system DATA SYS _ DATA is written increases. In this case, the amount of the system DATA SYS _ DATA to be restored by the memory device can be reduced by frequently writing the system DATA SYS _ DATA. Accordingly, the performance of the memory device may be enhanced.

The system DATA SYS _ DATA will be described in more detail with reference to fig. 6

The SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL.

In an embodiment, the SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL in response to a request of the host 300. Accordingly, if a request to update the SPO LEVEL SPO _ LEVEL is received from the host 300, the SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL based on the new sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may output the updated SPO LEVEL SPO _ LEVEL to the system data control unit 230.

In an embodiment, the SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL after a predetermined time elapses. In various embodiments, after a predetermined time has elapsed, the SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL based on the new sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may output the updated SPO LEVEL SPO _ LEVEL to the system data control unit 230.

The system data control unit 230 may receive the SPO LEVEL SPO _ LEVEL from the SPO LEVEL determination unit 220. The system DATA control unit 230 may write the system DATA SYS _ DATA into the system DATA storage 240 or the nonvolatile memory unit of the memory device 100 according to the SPO LEVEL SPO _ LEVEL. The system DATA control unit 230 may change the number of times the system DATA SYS _ DATA is stored according to the determined SPO LEVEL SPO _ LEVEL.

In an embodiment, the system DATA control unit 230 may control the system DATA SYS _ DATA such that the number of types of the system DATA SYS _ DATA to be stored may increase as the SPO LEVEL SPO _ LEVEL received from the SPO LEVEL determination unit 220 increases. In contrast, the system DATA control unit 230 may control the system DATA SYS _ DATA such that the number of types of the stored system DATA SYS _ DATA may be reduced as the SPO LEVEL SPO _ LEVEL is lowered. The system DATA control unit 230 may control the system DATA SYS _ DATA such that mapping-related DATA among the types of the system DATA SYS _ DATA must be stored even if the SPO LEVEL SPO _ LEVEL is relatively low.

Accordingly, as the SPO LEVEL SPO _ LEVEL is lowered, the number of pieces of system DATA SYS _ DATA to be written to the system DATA storage device 240 or the nonvolatile memory cells of the memory device 100 is reduced, so that the efficiency of the storage device may be improved because the number of pieces of DATA to be written is reduced. The performance of the memory device can be enhanced by adjusting the number of pieces of system DATA SYS _ DATA to be written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of pieces of system DATA SYS _ DATA to be written to the nonvolatile memory cells increases. In this case, the amount of the system DATA SYS _ DATA to be restored by the memory device can be reduced by increasing the number of types of the system DATA SYS _ DATA to be written. Accordingly, the performance of the memory device may be enhanced.

In an embodiment, as the SPO LEVEL SPO _ LEVEL increases, the system DATA control unit 230 may increase the number of times the system DATA SYS _ DATA is written. In contrast, as the SPO LEVEL SPO _ LEVEL is lowered, the system DATA control unit 230 may reduce the number of times the system DATA SYS _ DATA is written.

The system DATA control unit 230 may store the system DATA SYS _ DATA in the system DATA storage device 240 and/or the memory device 100. The system DATA SYS _ DATA may be stored in the system DATA storage 240 and/or in non-volatile memory cells of the memory device 100. In various embodiments, the system DATA control unit 230 may store the system DATA SYS _ DATA determined based on the SPO LEVEL SPO _ LEVEL. Further, the system DATA control unit 230 may store the system DATA SYS _ DATA at a writing time point determined based on the SPO LEVEL SPO _ LEVEL.

To store the system DATA SYS _ DATA, the system DATA control unit 230 may output a system DATA write command SDW _ CMD and the system DATA SYS _ DATA. The system DATA control unit 230 may output a system DATA write command SDW _ CMD and system DATA SYS _ DATA to the system DATA storage device 240 and/or the memory device 100. The system DATA SYS _ DATA received from the system DATA control unit 230 may be stored in the system DATA storage 240 and/or a nonvolatile memory unit of the memory device 100.

When the system DATA writing condition is satisfied, the system DATA control unit 230 may write the system DATA SYS _ DATA. In various embodiments, the system DATA SYS _ DATA may be written when a memory block storing DATA in the memory device 100 is changed. Therefore, when the map DATA is updated, the system DATA SYS _ DATA may be written. Further, when mapping information (for example, physical-to-logical (P2L) mapping information) indicating a mapping relationship between a Physical Block Address (PBA) and a Logical Block Address (LBA) is updated, system DATA SYS _ DATA may be written.

Accordingly, if the system DATA write condition is satisfied, the system DATA control unit 230 may write the system DATA SYS _ DATA determined based on the SPO LEVEL SPO _ LEVEL into the system DATA storage 240 and/or the nonvolatile memory cells of the memory device 100 at a write time point determined based on the SPO LEVEL SPO _ LEVEL.

The system DATA storage 240 may store system DATA SYS _ DATA. The system data store 240 may include volatile memory units or nonvolatile memory units. If system data storage 240 includes non-volatile memory cells, system data storage 240 may include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM or PCRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), or spin torque transfer magnetoresistive RAM (STT-MRAM).

In the case where the system DATA storage 240 includes a nonvolatile memory, the system DATA control unit 230 may store the system DATA SYS _ DATA in the system DATA storage 240. Therefore, the system DATA storage 240 may retain the stored system DATA SYS _ DATA even if the power is turned off. Accordingly, if the power is turned on again after the power is turned off, the memory device 50 including the memory controller 200 and the memory device 100 may perform a recovery operation based on the system DATA SYS _ DATA stored in the system DATA storage 240.

In various embodiments, if an SPO event occurs after the system DATA storage 240 has stored the system DATA SYS _ DATA, the memory controller 200 may perform a DATA recovery operation using the system DATA SYS _ DATA that has been stored in the system DATA storage 240 immediately before the SPO event occurs.

FIG. 3 is a diagram illustrating a memory controller including an SPO storage device, such as memory controller 200 of FIG. 1 including SPO storage device 211, according to an embodiment of the disclosure.

Referring to fig. 3, the memory controller 200 may include an SPO sensing unit 210, an SPO storage 211, an SPO level determining unit 220, a system data control unit 230, and a system data storage 240. Although fig. 3 shows memory controller 200 including system data storage 240, system data storage 240 may be implemented external to memory controller 200.

The memory controller 200 of fig. 3 has the same configuration as the memory controller 200 of fig. 2 except for the SPO storage device 211; therefore, in the description about the embodiment of fig. 3, the contents overlapping with those of the embodiment of fig. 2 will be omitted.

SPO storage 211 may receive power down TIME PO _ TIME from SPO sense unit 210. The power-off TIME PO _ TIME may be a TIME point at which the power is turned off. The power down TIME PO _ TIME may be stored in the memory device 100 and/or the memory controller 200. In fig. 3, the power-off TIME PO _ TIME is stored in the SPO storage device 211 in the memory controller 200.

SPO storage 211 may store the power down TIME PO _ TIME received from SPO sensing unit 210. The SPO storage device 211 may store a point in TIME when the power-off TIME PO _ TIME is received, whenever the power-off TIME PO _ TIME is received.

The SPO storage 211 may store SPO occurrence times. The SPO occurrence TIME may be a TIME between TIME points when the power-off TIME PO _ TIME is received. In an embodiment, the SPO event may occur again after the first SPO event occurs. The SPO event that occurs after the first SPO event may be a second SPO event. The SPO storage 211 may store a time between the first SPO event and the second SPO event. The TIME between the first SPO event and the second SPO event may be calculated using the power down TIME PO _ TIME.

The SPO storage 211 may accumulate SPO occurrence times. The accumulated SPO occurrence time may be stored in the SPO storage 211. In various embodiments, the SPO occurrence duration, including the previous SPO occurrence duration, may be stored each time a SPO event occurs.

The SPO storage 211 may store the number of SPO occurrence counts. In various embodiments, the SPO storage 211 may count the number of SPO occurrences when power is turned on again after a SPO event. When power is turned on again after an SPO event, the number of SPO occurrence counts may increase by "1". The increased number of SPO occurrence counts may be stored in SPO storage 211.

The SPO storage device 211 may generate the sensing information SE _ INF based on the power-off TIME PO _ TIME. The sensing information SE _ INF may include information on the SPO occurrence time and the number of SPO occurrence counts.

In various embodiments, the SPO occurrence time may be the time between the point in time when a SPO event has occurred and the point in time when another SPO event occurs again. The SPO occurrence count number may be the number of TIMEs the power-off TIME PO _ TIME is received. Since the SPO occurrence time and the SPO occurrence count number are accumulatively stored, the SPO storage 211 may output sensing information including information on the accumulated SPO occurrence time and the SPO occurrence count number to the SPO sensing unit 210 when the power is turned on.

The SPO sensing unit 210 may output the sensing information SE _ INF received from the SPO storage 211 to the SPO level determining unit 220. The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF. The operation after the SPO LEVEL determination unit 220 receives the sensing information SE _ INF and determines the SPO LEVEL SPO _ LEVEL is the same as that of the embodiment of fig. 2.

Fig. 4 is a diagram illustrating an operation of updating a Sudden Power Off (SPO) occurrence count number according to an embodiment of the present disclosure.

Referring to fig. 4, a first column indicates power on or off, and a second column indicates the number of SPO occurrence counts recorded in the SPO storage 211 of fig. 3. In FIG. 4, the power outage may be a power outage caused by an SPO event.

The zeroth power-on state may indicate that the storage device 50 is initially turned on. In this case, the SPO occurrence count number may not be stored in the SPO storage 211.

The first power-off state may indicate that an SPO event initially occurs. If an SPO event occurs, SPO storage device 211 may store the power down TIME PO _ TIME received from SPO sensing unit 210. In this case, the SPO occurrence count number may not be stored in the SPO storage 211.

After the first power-off state, the power supply may be turned on again. Such a state where the power supply is turned on again may be the first power-on state. In the first power-on state, the SPO storage device 211 may sense the power-on state and store the number of SPO occurrence counts. Because the initial SPO event occurs after storage device 50 is initially turned on, the SPO occurrence count number to be stored by SPO storage device 211 may be "1". After the stored SPO occurrence count number, SPO storage 211 may output sensing information SE _ INF including information about the stored SPO occurrence count number to SPO sensing unit 210.

After the first power-on state, the SPO event may occur again. The SPO state may be a second power-down state. In the second power-down state, SPO storage device 211 may store a power-down TIME PO _ TIME received from SPO sensing unit 210. In an embodiment, the number of SPO occurrence counts stored in SPO storage 211 may remain at "1".

If the power is turned on again after the second power-off state, the number of SPO occurrence counts may be increased by "1" and updated to "2". Such a state in which the power is turned on again after the second power-off state may be a second power-on state. In the second power-on state, the SPO occurrence count number may be updated to "2", and the updated SPO occurrence count number may be stored in the SPO storage device 211. The SPO storage 211 may output sensing information SE _ INF including information on the number of updated SPO occurrence counts to the SPO sensing unit 210.

After the second power-on state, the SPO event may again occur. The SPO state may be a third power-down state. In the third power-down state, SPO storage device 211 may store a power-down TIME PO _ TIME received from SPO sensing unit 210. In an embodiment, the number of SPO occurrence counts stored in the SPO storage 211 may be maintained at "2".

If the power is turned on again after the third power-off state, the number of SPO occurrence counts may be increased by "1" and updated to "3". Such a state in which the power is turned on again after the third power-off state may be a third power-on state. In the third power-on state, the SPO occurrence count number may be updated to "3", and the updated SPO occurrence count number may be stored in the SPO storage device 211. The SPO storage 211 may output sensing information SE _ INF including information on the number of updated SPO occurrence counts to the SPO sensing unit 210.

Although fig. 4 shows a process of updating the SPO occurrence count number from 1 to 3, the SPO occurrence count number stored in the SPO storage device 211 may be increased.

Fig. 5 is a diagram illustrating a method of updating a Sudden Power Off (SPO) occurrence period and a SPO occurrence count number according to an embodiment of the present disclosure.

Referring to fig. 4 and 5, fig. 5 shows a state in which the storage device 50 is switched from the zeroth power-on state to the third power-on state. That is, fig. 5 shows the state of the memory device 50 in the timing from the zeroth power-on state.

The zeroth power-on state may indicate that the storage device 50 is initially turned on. The first power-down state may indicate an initial SPO event. If an SPO event occurs, SPO storage device 211 may store the power down TIME PO _ TIME received from SPO sensing unit 210. In this case, the SPO occurrence count number may not be stored in the SPO storage 211.

The period between the zeroth power-on time point and the first power-off time point may be a first off time t _ off 1. The first off time t _ off1 may be the time taken before the initial SPO event occurs. The first off time t _ off1 may be a time when the SPO occurrence period is determined.

After the first power-off state, the power supply may be turned on again. Such a state where the power supply is turned on again may be the first power-on state. In the first power-on state, the number of SPO occurrence counts may be updated. Because the power has been turned on after the initial SPO event, the SPO occurrence count number may be updated to "1". The updated SPO occurrence count number may be stored in SPO storage 211. Further, in the first power-on state, the SPO storage device 211 may store a first off time t _ off 1. The first off time t _ off1 may be a period between the zeroth power-on time point and the first power-off time point.

After the first power-on state, the SPO event may occur again. The SPO state may be a second power-down state. In an embodiment, the period between the first power-off time point and the second power-off time point may be a second off time t _ off 2. The second off time t _ off2 may be the time taken after an SPO event occurs before another SPO event occurs.

After the second power-off state, the power supply may be turned on again. This state where the power supply is turned on again may be the second energization state. In the second powered-on state, the number of SPO occurrences may be updated. The number of SPO occurrence counts stored in the SPO storage 211 may be updated from "1" to "2". The updated SPO occurrence count number may be stored in SPO storage 211. Further, in the second powered-on state, the SPO storage device 211 may store a second off time t _ off 2. The second off time t _ off2 may be a period between the first power-off time point and the second power-off time point.

In the second power-on state, the SPO storage device 211 may accumulate and store the SPO occurrence time and the SPO occurrence count number. In various embodiments, the accumulated SPO occurrence time may be a value obtained by adding the first off-time t _ off1 and the second off-time t _ off 2. Further, the number of accumulated SPO occurrence counts may be "2" as an update value. The SPO storage 211 may output sensing information SE _ INF including information on the accumulated SPO occurrence time and the accumulated SPO occurrence count number to the SPO sensing unit 210.

Based on the accumulated SPO occurrence time and the accumulated number of SPO occurrence counts, the SPO occurrence period and the number of times a SPO event occurs within the reference time may be determined. In an embodiment, the SPO occurrence period may be a value obtained by dividing the sum of the first off time t _ off1 and the second off time t _ off2 by the updated SPO occurrence count number. In an embodiment, the number of times the SPO event occurs within the reference time may be a value determined by comparing the reference time with a sum of the first off-time t _ off1 and the second off-time t _ off 2.

After the second power-on state, the SPO event may again occur. The SPO state may be a third power-down state. In an embodiment, the period between the second power-off time point and the third power-off time point may be a third power-off time t _ off 3. The third off time t _ off3 may be the time taken after an SPO event occurs before another SPO event occurs.

After the third power-off state, the power supply may be turned on again. This state in which the power source is turned on again may be a third energization state. In the third power-on state, the number of SPO occurrences may be updated. The number of SPO occurrence counts stored in the SPO storage 211 may be updated from "2" to "3". The updated SPO occurrence count number may be stored in SPO storage 211. Further, in the third powered-off state, the SPO storage device 211 may store a third off time t _ off 3. The third off time t _ off3 may be a period between the second power-off time point and the third power-off time point.

In the third power-on state, the SPO storage device 211 may accumulate and store the SPO occurrence time and the SPO occurrence count number. In various embodiments, the accumulated SPO occurrence time may be a value obtained by adding the first off-time t _ off1, the second off-time t _ off2, and the third off-time t _ off 3. Further, the number of accumulated SPO occurrence counts may be "3" as an updated value. Accordingly, the SPO storage 211 may output sensing information SE _ INF including information on the accumulated SPO occurrence time and the accumulated SPO occurrence count number to the SPO sensing unit 210.

Based on the accumulated SPO occurrence time and the accumulated number of SPO occurrence counts, the SPO occurrence period and the number of times a SPO event occurs within the reference time may be determined. In the embodiment, the SPO occurrence period may be a value obtained by dividing the sum of the first off time t _ off1, the second off time t _ off2, and the third off time t _ off3 by the updated SPO occurrence count number. In an embodiment, the number of times the SPO event occurs within the reference time may be a value determined by comparing the reference time with a sum of the first off-time t _ off1, the second off-time t _ off2, and the third off-time t _ off 3.

Fig. 6 is a diagram illustrating system DATA SYS _ DATA according to an embodiment of the present disclosure. For example, the system DATA SYS _ DATA may be generated by the system DATA control unit 230 of fig. 2.

Referring to fig. 6, the system DATA SYS _ DATA may include at least one of HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, firmware-related DATA FW _ DATA, and mapping-related DATA MAP _ DATA.

The system DATA SYS _ DATA may be setting DATA required for the memory controller 200 to control the memory device 100. The system DATA SYS _ DATA may be classified into HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, firmware-related DATA FW _ DATA, and mapping-related DATA MAP _ DATA according to its contents.

The HOST-related DATA HOST DATA and the USER-related DATA USER _ DATA may comprise start-up-related information and USER-related information. The boot-related information may include boot loader-related information and boot-related information. The user-related information may include information about the protected memory block (RPMB) being replaced and the permanent Write Protect (WP) that persists during the next power-on. The boot loader related information may include information required to execute an operating system, load a kernel into memory, and hand over control of the memory to a host, or information required to initialize hardware. The boot-related information may include various hardware information, initialization information, and information related to the transfer of the operating system image. The information related to the RPMB and WP may include main information or confidential information of the user.

The firmware-related information FW _ DATA may include setting information related to the memory device, such as firmware system algorithm or hardware register information and FTL-related information.

The mapping-related information MAP _ DATA may include at least one of mapping Index (MAP Index), mapping table (MAP T1 to T5), and MAP conversion (MAP P2L) and temporary mapping (MAP temp P2L) information. The mapping index may include a location of the mapping-related information, and the mapping table may include actual mapping data information of the memory device. The mapping translation and temporary mapping information may include information between physical addresses and logical addresses.

The HOST-related DATA HOST _ DATA, the USER-related DATA USER _ DATA, the firmware-related DATA FW _ DATA and the mapping-related DATA MAP _ DATA may be stored in one memory block, or distributed and stored in a plurality of memory blocks.

Although the size of the system DATA SYS _ DATA is small, the system DATA SYS _ DATA is very important information required to drive the memory device, and thus may be set to store multiple copies thereof.

In the case where the erase operation of the memory device is performed on a block basis, when the system DATA SYS _ DATA is updated, it is possible to erase the system information stored together with the updated system information. Therefore, to prevent this, the system DATA SYS _ DATA may be stored in a different memory block.

The type of system DATA SYS _ DATA to be stored in the system DATA storage device 240 and/or the memory device 100 may vary according to the SPO LEVEL SPO _ LEVEL. In various embodiments, as the SPO LEVEL SPO _ LEVEL is lowered, the number of SPO events occurring is reduced, and thus the number of types of system DATA SYS _ DATA to be stored may be reduced. In contrast, as the SPO LEVEL SPO _ LEVEL is increased, the number of times of occurrence of the SPO event increases, so that the number of types of the system DATA SYS _ DATA to be stored may increase.

Even if the SPO LEVELs SPO _ LEVEL are different from each other, the mapping-related DATA MAP _ DATA among the types of the system DATA SYS _ DATA may be included in the system DATA SYS _ DATA to be stored. Thus, the mapping-related DATA MAP _ DATA may be stored regardless of the SPO LEVEL SPO _ LEVEL.

Fig. 7 is a diagram illustrating a method of determining a Sudden Power Off (SPO) level according to an embodiment of the present disclosure. For example, the SPO level may be determined by the SPO level determination unit 220.

Referring to fig. 7, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the SPO occurrence count number SPO _ NUM indicating the number of times an SPO event has occurred within the reference time t _ ref.

In an embodiment, the reference time t _ ref may be stored in the SPO level determination unit 220 in advance. The reference time t _ ref may be a time required to determine the SPO LEVEL SPO _ LEVEL. The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL while changing the reference time t _ ref.

The SPO level determination unit 220 may count the number of SPO occurrence counts SPO _ NUM within the reference time t _ ref based on the sensing information received from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the SPO occurrence count number SPO _ NUM.

In an embodiment, the SPO LEVEL SPO _ LEVEL may be the first SPO LEVEL SPO _ LEVEL1 if the number of SPO occurrence counts SPO _ NUM is p1 or less. The SPO LEVEL SPO _ LEVEL may be a second SPO LEVEL SPO _ LEVEL2 if the number of SPO occurrence counts, SPO _ NUM, is greater than p1 and is p2 or less. The SPO LEVEL SPO _ LEVEL may be the third SPO LEVEL SPO _ LEVEL3 if the number of SPO occurrence counts SPO _ NUM is greater than p 2.

Although fig. 7 shows that the section to which the SPO occurrence count number SPO _ NUM can belong is any one of three sections, the number of sections on which the SPO LEVEL SPO _ LEVEL is determined can be increased. In determining the SPO LEVEL SPO _ LEVEL, the section to which the SPO occurrence count number SPO _ NUM can belong can be further subdivided.

In an embodiment, the SPO LEVEL determination unit 220 may determine one of the first to third SPO LEVELs SPO _ LEVEL1 to SPO _ LEVEL3 as the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may output the determined SPO LEVEL SPO _ LEVEL to the system data control unit 230.

The first SPO LEVEL SPO _ LEVEL1 may be an SPO LEVEL SPO _ LEVEL determined among the first to third SPO LEVELs SPO _ LEVEL1 to SPO _ LEVEL3 when the SPO occurrence count number SPO _ NUM is minimum. In an embodiment, when the SPO occurrence count number SPO _ NUM is p1 or less, it may be determined that the SPO LEVEL SPO _ LEVEL is the first SPO LEVEL SPO _ LEVEL 1. Therefore, since the SPO occurrence count number SPO _ NUM indicating the number of times the SPO event has occurred within the reference time t _ ref is relatively small, it is not necessary to frequently write the system DATA SYS _ DATA to the system DATA storage device 240 or the nonvolatile memory cells of the memory device 100. Therefore, the system DATA (SYS _ DATA) writing period may be relatively long. The time between the writing time points of the system DATA SYS _ DATA may be increased. Further, since the SPO occurrence count number SPO _ NUM is small, the number of types of system DATA SYS _ DATA to be stored can be reduced. In this case, however, the system DATA SYS _ DATA may also include the mapping-related DATA MAP _ DATA.

The third SPO LEVEL SPO _ LEVEL3 may be an SPO LEVEL SPO _ LEVEL determined among the first to third SPO LEVELs SPO _ LEVEL1 to SPO _ LEVEL3 when the SPO occurrence count number SPO _ NUM is maximum. In an embodiment, when the number of SPO occurrence counts, SPO _ NUM, is greater than p2, it may be determined that the SPO LEVEL SPO _ LEVEL is the third SPO LEVEL SPO _ LEVEL 3. Therefore, since the SPO occurrence count number SPO _ NUM indicating the number of times the SPO event has occurred within the reference time t _ ref is relatively large, it is necessary to frequently write the system DATA SYS _ DATA to the system DATA storage device 240 or the nonvolatile memory cells of the memory device 100. Therefore, the system DATA (SYS _ DATA) writing period may be relatively short. The time between the writing time points of the system DATA SYS _ DATA may be reduced. Further, since the SPO occurrence count number SPO _ NUM is large, the number of types of system DATA SYS _ DATA to be stored can be increased. Thus, in this case, the system DATA SYS _ DATA may include not only the mapping-related DATA MAP _ DATA but also HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, and firmware-related DATA FW _ DATA.

The second SPO LEVEL SPO _ LEVEL2 may be an SPO LEVEL SPO _ LEVEL determined when the SPO occurrence count number SPO _ NUM is greater than the SPO occurrence count number SPO _ NUM of the first SPO LEVEL SPO _ LEVEL1 and less than the SPO occurrence count number SPO _ NUM of the third SPO LEVEL SPO _ LEVEL 3. In an embodiment, when the number of SPO occurrence counts, SPO _ NUM, is greater than p1 and is p2 or less, the SPO LEVEL SPO _ LEVEL may be determined to be the second SPO LEVEL SPO _ LEVEL 2. Thus, the SPO occurrence count number SPO _ NUM indicating the number of times an SPO event has occurred within the reference time t _ ref may be greater than the SPO occurrence count number SPO _ NUM of the first SPO LEVEL SPO _ LEVEL1 and less than the SPO occurrence count number SPO _ NUM of the third SPO LEVEL SPO _ LEVEL 3. The period of writing the system DATA SYS _ DATA to the second SPO LEVEL SPO _ LEVEL2 of the nonvolatile memory cell may be shorter than the period of the first SPO LEVEL SPO _ LEVEL1 and longer than the period of the third SPO LEVEL SPO _ LEVEL 3. Further, the number of types of the system DATA SYS _ DATA to be stored at the second SPO LEVEL SPO _ LEVEL2 may be greater than the number of types of the system DATA SYS _ DATA to be stored at the first SPO LEVEL SPO _ LEVEL1, and may be less than the number of types of the system DATA SYS _ DATA to be stored at the third SPO LEVEL SPO _ LEVEL 3.

Accordingly, in the case where the sensing information SE _ INF may include information regarding the number of times the SPO event has occurred within the reference time t _ ref, the SPO LEVEL SPO _ LEVEL may increase as the number of times the SPO event has occurred increases. Conversely, as the number of SPO events that have occurred decreases, the SPO LEVEL SPO _ LEVEL may decrease.

Therefore, as the SPO LEVEL SPO _ LEVEL is lowered, the number of times of writing the system DATA SYS _ DATA is reduced, so that the efficiency of the memory device can be improved. The performance of the memory device may be enhanced by adjusting the number of times the system DATA SYS _ DATA is written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of times the system DATA SYS _ DATA is written increases. In this case, the amount of the system DATA SYS _ DATA to be restored by the memory device can be reduced by frequently writing the system DATA SYS _ DATA. Accordingly, the performance of the memory device may be enhanced.

In an embodiment, as the SPO LEVEL SPO _ LEVEL is lowered, the number of pieces of system DATA SYS _ DATA to be written in the system DATA storage 240 or the nonvolatile memory cells of the memory device 100 is reduced, so that the efficiency of the storage device may be improved because the number of pieces of DATA to be written is reduced. The performance of the memory device can be enhanced by adjusting the number of pieces of system DATA SYS _ DATA to be written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of pieces of system DATA SYS _ DATA to be written in the nonvolatile memory cells of the system DATA storage device 240 or the memory device 100 increases. In this case, the amount of system DATA to be restored by the storage device can be reduced by increasing the number of types of system DATA SYS _ DATA to be written. Accordingly, the performance of the memory device may be enhanced.

If the SPO LEVEL SPO _ LEVEL is determined to be a relatively high LEVEL, the interval between writing time points of the system DATA SYS _ DATA may be reduced. In addition, the number of types of system DATA SYS _ DATA to be written in the nonvolatile memory cell may be increased.

Fig. 8 is a diagram illustrating a method of determining a Sudden Power Off (SPO) LEVEL SPO _ LEVEL according to an embodiment of the present disclosure. For example, the SPO LEVEL SPO _ LEVEL may be determined by the SPO LEVEL determination unit 220.

Referring to fig. 8, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the SPO occurrence period SPO _ PER.

In an embodiment, the SPO occurrence period SPO _ PER may be an average value of the reference count number interrupt power duration. The reference count number may be determined in advance and stored in the SPO level determination unit 220. The reference count number may be the number of times the SPO event has occurred. The SPO section may be a section defined from a power-off time point to a power-on time point.

In various embodiments, the SPO level determination unit 220 may determine a reference count number for determining the SPO occurrence period SPO _ PER. The number of reference counts may vary. The SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL by calculating an average value of the reference count number interrupt power durations.

In an embodiment, if the SPO occurrence period SPO _ PER is t1 or less, the SPO LEVEL SPO _ LEVEL may be a sixth SPO LEVEL SPO _ LEVEL 6. The SPO LEVEL SPO _ LEVEL may be the fifth SPO LEVEL SPO _ LEVEL5 if the SPO occurrence period SPO _ PER is greater than t1 and is t2 or less. The SPO LEVEL SPO _ LEVEL may be a fourth SPO LEVEL SPO _ LEVEL4 if the SPO occurrence period SPO _ PER is greater than t 2.

Although fig. 8 illustrates that the section to which the SPO occurrence period SPO _ PER can belong is any one of three sections, the number of sections on which the SPO LEVEL SPO _ LEVEL is determined may be increased. The section to which the SPO occurrence period SPO _ PER may belong may be further subdivided in determining the SPO LEVEL SPO _ LEVEL.

In an embodiment, the SPO LEVEL determination unit 220 may determine one of the fourth to sixth SPO LEVELs SPO _ LEVEL4 to SPO _ LEVEL6 as the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL determination unit 220 may output the determined SPO LEVEL SPO _ LEVEL to the system data control unit 230.

The sixth SPO LEVEL SPO _ LEVEL6 may be the SPO LEVEL SPO _ LEVEL determined among the fourth to sixth SPO LEVELs SPO _ LEVEL4 to SPO _ LEVEL6 when the SPO occurrence period SPO _ PER is shortest. If the SPO occurrence period SPO _ PER is relatively short, SPO events may occur frequently. In an embodiment, when the SPO occurrence period SPO _ PER is t1 or less, it may be determined that the SPO LEVEL SPO _ LEVEL is the sixth SPO LEVEL SPO _ LEVEL 6.

If the SPO LEVEL SPO _ LEVEL is determined to be the sixth SPO LEVEL SPO _ LEVEL6, the system DATA control unit 230 needs to write the system DATA SYS _ DATA to the nonvolatile memory unit frequently because the SPO occurrence period SPO _ PER is relatively short. Therefore, the system DATA (SYS _ DATA) writing period may be relatively short. The time between the writing time points of the system DATA SYS _ DATA may be reduced. Further, since the SPO occurrence period SPO _ PER is short, the number of types of system DATA SYS _ DATA to be stored can be increased. Thus, in this case, the system DATA SYS _ DATA may include not only the mapping-related DATA MAP _ DATA but also HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, and firmware-related DATA FW _ DATA.

The fourth SPO LEVEL SPO _ LEVEL4 may be a SPO LEVEL SPO _ LEVEL determined among the fourth to sixth SPO LEVELs SPO _ LEVEL4 to SPO _ LEVEL6 when the SPO occurrence period SPO _ PER is longest. If the SPO occurrence period SPO _ PER is relatively long, the SPO occurrence frequency may be decreased. In an embodiment, when the SPO occurrence period SPO _ PER is greater than t2, the SPO LEVEL SPO _ LEVEL may be determined to be the fourth SPO LEVEL SPO _ LEVEL 4.

If the SPO LEVEL SPO _ LEVEL is determined to be the fourth SPO LEVEL SPO _ LEVEL4, the system DATA control unit 230 does not need to write the system DATA SYS _ DATA frequently because the SPO occurrence period SPO _ PER is relatively long. Therefore, the system DATA (SYS _ DATA) writing period may be relatively long. The time between the writing time points of the system DATA SYS _ DATA may be increased. Further, since the SPO occurrence period SPO _ PER is long, the number of types of system DATA SYS _ DATA to be stored can be reduced. In this case, however, the system DATA SYS _ DATA may also include the mapping-related DATA MAP _ DATA.

The fifth SPO LEVEL SPO _ LEVEL5 may be the SPO LEVEL SPO _ LEVEL determined when the SPO occurrence period SPO _ PER is longer than the SPO occurrence period SPO _ PER of the sixth SPO LEVEL SPO _ LEVEL6 and shorter than the SPO occurrence period SPO _ PER of the fourth SPO LEVEL SPO _ LEVEL 4. In an embodiment, when the SPO occurrence period SPO _ PER is longer than t1 and shorter than or equal to t2, the SPO LEVEL SPO _ LEVEL may be determined to be the fifth SPO LEVEL SPO _ LEVEL 5. Accordingly, a period of writing the system DATA SYS _ DATA to the system DATA storage device 240 or the nonvolatile memory cells of the memory device 100 may be shorter than a period of the fourth SPO LEVEL SPO _ LEVEL4 and longer than a period of the sixth SPO LEVEL SPO _ LEVEL 6. Further, the number of types of the system DATA SYS _ DATA to be stored in the nonvolatile memory cell at the fifth SPO LEVEL SPO _ LEVEL5 may be greater than the number of types of the system DATA SYS _ DATA to be stored at the fourth SPO LEVEL SPO _ LEVEL4, and may be less than the number of types of the system DATA SYS _ DATA to be stored at the sixth SPO LEVEL SPO _ LEVEL 6.

As the SPO LEVEL SPO _ LEVEL increases, the interval between writing time points at which the system DATA SYS _ DATA is written may decrease, and the number of types of system DATA SYS _ DATA to be written may increase.

In the case where the SPO LEVEL SPO _ LEVEL is determined based on the SPO occurrence count number SPO _ NUM, the larger the SPO occurrence count number SPO _ NUM, the higher the SPO LEVEL SPO _ LEVEL may be. In the case where the SPO LEVEL SPO _ LEVEL is determined based on the SPO occurrence period SPO _ PER, the longer the SPO occurrence period SPO _ PER is, the lower the SPO LEVEL SPO _ LEVEL may be.

Accordingly, when the sensing information SE _ INF includes information on the SPO occurrence period SPO _ PER, the shorter the SPO occurrence period SPO _ PER is, the higher the SPO LEVEL SPO _ LEVEL may be. Conversely, the longer the SPO occurrence period SPO _ PER, the lower the SPO LEVEL SPO _ LEVEL may be.

Therefore, as the SPO LEVEL SPO _ LEVEL is lowered, the number of times of writing the system DATA SYS _ DATA is reduced, so that the efficiency of the memory device can be improved. The performance of the memory device may be enhanced by adjusting the number of times the system DATA SYS _ DATA is written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of times the system DATA SYS _ DATA is written increases. In this case, the amount of the system DATA SYS _ DATA to be restored by the memory device can be reduced by frequently writing the system DATA SYS _ DATA. Accordingly, the performance of the memory device may be enhanced.

In an embodiment, as the SPO LEVEL SPO _ LEVEL is lowered, the number of pieces of system DATA SYS _ DATA to be written in the nonvolatile memory cell is reduced, so that the efficiency of the storage device may be improved because the number of pieces of DATA to be written is reduced. The performance of the memory device can be enhanced by adjusting the number of pieces of system DATA SYS _ DATA to be written. In contrast, as the SPO LEVEL SPO _ LEVEL increases, the number of pieces of system DATA SYS _ DATA to be written to the nonvolatile memory cells increases. In this case, the amount of system DATA to be restored by the storage device can be reduced by increasing the number of types of system DATA SYS _ DATA to be written. Accordingly, the performance of the memory device may be enhanced.

FIG. 9 is a block diagram illustrating a memory device, such as memory device 100 of FIG. 1, according to an embodiment of the present disclosure.

Referring to fig. 9, the memory device 100 may include a memory cell array 110 and peripheral circuits 120. Peripheral circuitry 120 may include address decoder 121, voltage generator 122, read and write (read/write) circuitry 123, data input and output (input/output) circuitry 124, and control logic 125.

Memory cell array 110 may include a plurality of memory blocks BLK1 through BLKz. The memory blocks BLK1 to BLKz are connected to the address decoder 121 through row lines RL and to the read/write circuit 123 through bit lines BL1 to BLm. Each of the memory blocks BLK1 through BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells.

The plurality of memory cells in the memory cell array 110 may be divided into a plurality of blocks according to the purpose of use. System information such as various setting information required to control the memory device 100 may be stored in a plurality of blocks.

Each of the first to z-th memory blocks BLK1 to BLKz includes a plurality of memory cell strings. The first to mth cell strings are coupled to first to mth bit lines BL1 to BLm, respectively. Each of the first to mth cell strings includes a drain select transistor, a plurality of memory cells coupled in series to each other, and a source select transistor. The drain select transistor DST is coupled to a drain select line DSL. The first to nth memory cells are coupled to first to nth word lines, respectively. The source select transistor SST is coupled to a source select line SSL. The drain of the drain select transistor DST is coupled to a corresponding bit line. The drain select transistors DST of the first to mth cell strings are coupled to first to mth bit lines BL1 to BLm, respectively. The source of the source selection transistor SST is coupled to the common source line CSL. In an embodiment, the common source line CSL may be commonly coupled to the first to z-th memory blocks BLK1 to BLKz. The row line RL includes a drain select line DSL, first to nth word lines WL1 to WLn, and a source select line SSL. The drain select line DSL, the first to nth word lines WL1 to WLn, and the source select line SSL are controlled by the address decoder 121. The common source line CSL is controlled by control logic 125. The first to mth bit lines BL1 to BLm are controlled by the read/write circuit 123.

Address decoder 121 is coupled to memory cell array 110 by row lines RL. Address decoder 121 may operate under the control of control logic 125. Address decoder 121 receives address ADDR through control logic 125.

In an embodiment, the program operation and the read operation of the memory device 100 may be performed on a page basis.

During a program operation or a read operation, the address ADDR received by the control logic 125 may include a block address and a row address. The address decoder 121 may decode a block address among the received addresses ADDR. The address decoder 121 may select a corresponding one of the memory blocks BLK1 through BLKz in response to the decoded block address.

The address decoder 121 may decode a row address among the received addresses ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage supplied from the voltage generator 122 to the row line RL and select one word line of the selected memory block.

During an erase operation, the address ADDR may include a block address. The address decoder 121 may decode the block address and select one memory block according to the decoded block address. The erase operation may be performed on all or part of one memory block.

During a partial erase operation, the address ADDR may include a block address and a row address. The address decoder 121 may select a corresponding one of the memory blocks BLK1 through BLKz in response to the decoded block address.

The address decoder 121 may decode a row address among the received addresses ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage supplied from the voltage generator 122 to the row line RL and select at least one word line of the selected memory block.

In an embodiment, the address decoder 121 may include a block decoder, a word line decoder, and an address buffer.

The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic 125.

In an embodiment, the voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated from the voltage generator 122 may be used as an operation voltage of the memory device 100.

In an embodiment, the voltage generator 122 may generate the plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal supply voltage, and generate the plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 125. The address decoder 121 applies the generated voltage to the selected word line.

During a program operation, the voltage generator 122 may generate a program pulse having a high voltage and a pass pulse having a voltage level lower than the program pulse. During a read operation, the voltage generator 122 may generate a read voltage and a pass voltage higher than the read voltage. During an erase operation, the voltage generator 122 may generate an erase voltage.

The read/write circuit 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are coupled to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may operate under the control of the control logic 125.

The first to mth page buffers PB1 to PBm may be in data communication with the data input/output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm may receive DATA to be stored through the DATA input/output circuit 124 and the DATA lines DL.

During a program operation, when a program pulse is applied to a selected word line, the first to mth page buffers PB1 to PBm may transfer data received through the data input/output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. The memory cells in the selected page are programmed based on the transferred data. A memory cell coupled to a bit line to which a program enable voltage (e.g., ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which the program-inhibit voltage (e.g., a supply voltage) is applied may be maintained. During a program verify operation, the first to mth page buffers PB1 to PBm may read page data from selected memory cells through the bit lines BL1 to BLm.

During a read operation, the read/write circuit 123 may read DATA from the memory cells in the selected page through the bit lines BL and output the read DATA to the DATA input/output circuit 124. During an erase operation, the read/write circuit 123 may float the bit line BL.

In an embodiment, the read/write circuits 123 may include column select circuits.

The data input/output circuit 124 is coupled to the first to mth page buffers PB1 to PBm through the data line DL. The data input/output circuit 124 may operate under the control of control logic 125. During a programming operation, the data input/output circuit 124 may receive data to be stored from an external controller (not shown).

The control logic 125 is connected to the address decoder 121, the voltage generator 122, the read/write circuit 123, and the data input/output circuit 124. The control logic 125 may control the overall operation of the memory device 100. The control logic 125 may receive a command CMD and an address ADDR from an external controller. The control logic 125 may control the address decoder 121, the voltage generator 122, the read/write circuit 123, and the data input/output circuit 124 in response to the command CMD.

Fig. 10 is a diagram illustrating a memory cell array, such as memory cell array 110 of fig. 9, according to an embodiment of the present disclosure.

Referring to fig. 10, the memory cell array 110 may include a plurality of memory blocks BLK1 through BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The memory cells are arranged in the + X direction, + Y direction, and + Z direction. The structure of each memory block will be described in more detail with reference to fig. 11 and 12.

Fig. 11 is a circuit diagram illustrating a memory block, for example, a memory block BLKa among the plurality of memory blocks BLK1 through BLKz of fig. 10, according to an embodiment of the present disclosure.

Referring to fig. 11, the memory block BLKa may include a plurality of cell strings CS11 through CS1m and CS21 through CS2 m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., + X direction). In fig. 11, it is shown that two cell strings are arranged in the column direction (i.e., + Y direction). However, this illustration is merely for convenience of description, and it will be understood that three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 through CS1m and CS21 through CS2m may include at least one source select transistor SST, first through nth memory cells MC1 through MCn, a pipe transistor PT, and at least one drain select transistor DST.

The selection transistors SST and DST and the memory cells MC1 through MCn may have similar structures, respectively. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCp.

In an embodiment, the source selection transistors of cell strings arranged in the same row are coupled to a source selection line extending in the row direction, and the source selection transistors of cell strings arranged in different rows are coupled to different source selection lines. In fig. 11, the source select transistors of the cell strings CS11 through CS1m in the first row are coupled to a first source select line SSL 1. The source select transistors of the cell strings CS21 through CS2m in the second row are coupled to a second source select line SSL 2.

In an embodiment, the source select transistors of the cell strings CS11 through CS1m and CS21 through CS2m may be commonly coupled to a single source select line.

The first to nth memory cells MC1 to MCn in each cell string are coupled between the source selection transistor SST and the drain selection transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p +1 to nth memory cells MCp +1 to MCn. The first to pth memory cells MC1 to MCp are continuously arranged in a direction opposite to the + Z direction, and are coupled in series between the source select transistor SST and the tunnel transistor PT. The p +1 th to nth memory cells MCp +1 to MCn are continuously arranged in the + Z direction and are coupled in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p +1 to nth memory cells MCp +1 to MCn are coupled to each other through a pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are coupled to the first to nth word lines WL1 to WLn, respectively.

The respective gates of the pipe transistors PT of the cell string are coupled to the line PL.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MCp +1 to MCn. The cell string arranged in the row direction is coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second drain select line DSL 2.

Cell strings arranged in the column direction may be coupled to bit lines extending in the column direction. In fig. 11, the cell strings CS11 and CS21 in the first column are coupled to a first bit line BL 1. The cell strings CS1m and CS2m in the mth column are coupled to the mth bit line BLm.

Memory cells coupled to the same word line among cell strings arranged in the row direction form a single page. For example, memory cells coupled to the first word line WL1 among the cell strings CS11 through CS1m in the first row form a single page. Memory cells coupled to the first word line WL1 among the cell strings CS21 through CS2m in the second row form another single page. When any one of the drain select lines DSL1 and DSL2 is selected, the corresponding cell string arranged in a single row direction may be selected. When any one of the word lines WL1 to WLn is selected, a corresponding single page may be selected from among the selected cell strings.

In an embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. The even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the respective even bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the respective odd bit lines.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be disposed to reduce an electric field between the source select transistor SST and the memory cells MC1 through MCp. Optionally, at least one or more dummy memory cells may be disposed to reduce an electric field between the drain select transistor DST and the memory cells MCp +1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKa may increase, but the size of the memory block BLKa may increase. As the number of dummy memory cells decreases, the size of the memory block BLKa may decrease, but the operational reliability of the memory block BLKa may decrease.

In order to effectively control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to the dummy word line coupled to each dummy memory cell.

Fig. 12 is a circuit diagram illustrating a memory block, for example, a memory block BLKb among the plurality of memory blocks BLK1 through BLKz of fig. 10, according to an embodiment of the present disclosure.

Referring to fig. 12, the memory block BLKb may include a plurality of cell strings CS11 'to CS1m' and CS21 'to CS2 m'. Each of the cell strings CS11 'to CS1m' and CS21 'to CS2m' extends in the + Z direction. Each of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown), wherein the substrate is disposed at a lower portion of the memory block BLKb.

The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are coupled to the same source select line. The source select transistors of the cell strings CS11 'to CS1m' arranged in the first row may be coupled to a first source select line SSL 1. The source select transistors of the cell strings CS21 'to CS2m' arranged in the second row may be coupled to a second source select line SSL 2. In an embodiment, the source select transistors of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may be commonly coupled to a single source select line.

The first to nth memory cells MC1 to MCn in each cell string are coupled in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn are coupled to the first to nth word lines WL1 to WLn, respectively.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MC1 through MCn. The drain select transistors of the cell strings arranged in the row direction may be coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' in the first row are coupled to a first drain select line DSL 1. The drain select transistors of the cell strings CS21 'to CS2m' in the second row may be coupled to a second drain select line DSL 2.

Accordingly, the memory block BLKb of fig. 12 may have an equivalent circuit similar to that of the memory block BLKa of fig. 11, except that the pipe transistor PT is removed from each cell string.

In an embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11 'to CS1m' or CS21 'to CS2m' arranged in the row direction may be coupled to the respective even bit lines, and odd-numbered cell strings among the cell strings CS11 'to CS1m' or CS21 'to CS2m' arranged in the row direction may be coupled to the respective odd bit lines.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be disposed to reduce an electric field between the source select transistor SST and the memory cells MC1 through MCn. Alternatively, at least one or more dummy memory cells may be disposed to reduce an electric field between the drain select transistor DST and the memory cells MC1 through MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKb may increase, but the size of the memory block BLKb may increase. As the number of dummy memory cells decreases, the size of the memory block BLKb may decrease, but the operational reliability of the memory block BLKb may decrease.

In order to effectively control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKb, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation is performed, the dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to the dummy word line coupled to each dummy memory cell.

Fig. 13 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 2 or 3) according to an embodiment of the present disclosure.

Referring to fig. 13, in step S1301, the SPO sensing unit 210 may sense a SPO event. The SPO event may be a phenomenon in which the power supply is suddenly turned off. If the power is suddenly turned off, the SPO sensing unit 210 may control the memory device 100 to store a point of time when the power is turned off. The point of TIME when the power is turned off may be a power-off TIME PO _ TIME. The power down TIME PO _ TIME may be stored in the memory device 100.

In step S1303, the SPO sensing unit 210 may generate sensing information SE _ INF. In various embodiments, the SPO sensing unit 210 may generate the sensing information SE _ INF based on the SPO duration. The sensing information SE _ INF may include at least one of the number of times the SPO event has occurred during the reference time t _ ref and the SPO occurrence period SPO _ PER. The SPO occurrence period SPO _ PER may be an average value of the SPO duration.

In step S1305, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL. In various embodiments, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the sensing information SE _ INF received from the SPO sensing unit 210. From the SPO LEVEL SPO _ LEVEL, the system DATA SYS _ DATA to be written and the time point at which the system DATA SYS _ DATA is written may be determined.

The higher the frequency of occurrence of an SPO event, the higher the SPO LEVEL SPO _ LEVEL can be. The lower the frequency of occurrence of an SPO event, the lower the SPO LEVEL SPO _ LEVEL can be.

In step S1307, the SPO LEVEL determination unit 220 may determine whether to update the SPO LEVEL SPO _ LEVEL. The SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL. In various embodiments, the SPO LEVEL determination unit 220 may update the SPO LEVEL SPO _ LEVEL in response to a request of the host 300 or after a predetermined time elapses. In the case where the SPO LEVEL determination unit 220 updates the SPO LEVEL SPO _ LEVEL (S1307, yes), the process proceeds to step S1301, whereby the SPO sensing unit 210 senses the SPO event to generate new sensing information SE _ INF. In the case where the SPO LEVEL determination unit 220 may not update the SPO LEVEL SPO _ LEVEL (S1307, no), the process proceeds to step S1309.

In step S1309, the system data control unit 230 may determine whether the system data writing condition has been satisfied. The system data write condition may include any one of a change in a storage block in the memory device 100 that stores data and an update of mapping information (i.e., physical to logical (P2L)) indicating a mapping relationship between a Physical Block Address (PBA) and a Logical Block Address (LBA). The system data write conditions may vary.

If the system data writing condition is satisfied (yes at S1309), the process proceeds to step S1311. If the system data write condition is not satisfied (no at S1309), the process proceeds to step S1301. In case the system DATA write condition is not satisfied, the system DATA control unit 230 may not write the system DATA SYS _ DATA, and the SPO sensing unit 210 may sense the SPO event in order to generate the new sensing information SE _ INF.

In step S1311, the system DATA control unit 230 may store the system DATA SYS _ DATA at a time point determined based on the SPO LEVEL SPO _ LEVEL. The system DATA control unit 230 may write the system DATA SYS _ DATA based on the SPO LEVEL SPO _ LEVEL received from the SPO LEVEL determination unit 220. The system DATA control unit 230 may write the system DATA SYS _ DATA determined based on the SPO LEVEL SPO _ LEVEL at a writing time point corresponding to the SPO LEVEL SPO _ LEVEL. After the system DATA SYS _ DATA has been written, the process may again proceed to step S1301.

Fig. 14 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 2 or 3) according to an embodiment of the present disclosure.

Referring to fig. 14, the power may be turned off in step S1401. In various embodiments, the power down event may be a condition in which the power supply is suddenly disconnected. If the power is suddenly turned off, the SPO sensing unit 210 may control the memory device 100 to store a point of time when the power is turned off.

In step S1403, the SPO sensing unit 210 may store the power-off time point in the memory device 100. In various embodiments, the power-off time point may be a time point at which the power is suddenly turned off. The point of TIME when the power is suddenly turned off may be a power-off TIME PO _ TIME. The power down TIME PO _ TIME may be stored in the memory device 100. The power-down TIME PO _ TIME stored in the memory device 100 may be output to generate the sensing information SE _ INF.

In step S1405, power may be turned on. In various embodiments, the power supply may be turned on again after the SPO event has occurred. In the case where the power is turned on, the storage device 50 may perform a recovery operation using the system DATA SYS _ DATA. The system DATA SYS _ DATA may comprise at least one of HOST-related DATA HOST _ DATA, USER-related DATA USER _ DATA, firmware-related DATA FW _ DATA, and mapping-related DATA MAP _ DATA.

In step S1407, the SPO sensing unit 210 may receive a power-off time point from the memory device 100. In detail, the power-off TIME point may be power-off TIME PO _ TIME stored in the memory device 100 when the SPO event occurs.

In step S1409, the SPO sensing unit 210 may receive the power-off TIME PO _ TIME and calculate a duration from the power-off TIME PO _ TIME to a TIME point at which the power is turned on again. Whenever an SPO event occurs, SPO sensing unit 210 may calculate a duration from the power-off TIME PO _ TIME to a point in TIME when the power is turned on again. The duration from the power-off TIME PO _ TIME to the point of TIME when the power is turned on again may be accumulatively calculated.

In step S1411, the SPO sensing unit 210 may generate sensing information SE _ INF. The SPO sensing unit 210 may sense the SPO event and generate sensing information SE _ INF. In various embodiments, the SPO sensing unit 210 may generate the sensing information SE _ INF based on the SPO duration. The SPO sensing unit 210 may generate the sensing information SE _ INF by calculating a duration from a power-off time point to a power-on time point.

The sensing information SE _ INF may include information about the number of times that SPO events have occurred within the reference time t _ ref. Further, the sensing information SE _ INF may include information on the SPO occurrence period SPO _ PER. The SPO occurrence period SPO _ PER may be an average value of the SPO duration. The SPO occurrence period SPO _ PER may be a value obtained by accumulating the duration from each power-off time point to the corresponding power-on time point and dividing the accumulated duration by the number of times the SPO event has occurred.

Fig. 15 is a diagram illustrating an operation of a memory device (e.g., the memory device 100 of fig. 2 or 3) according to an embodiment of the present disclosure.

Referring to fig. 15, in step S1501, the memory device 100 may receive a write command. When a write command is received from the memory controller 200, the memory device 100 may receive a Physical Block Address (PBA) to execute the write command together with the write command.

In step S1503, the memory device 100 may determine whether to write system data. In various embodiments, the memory device 100 may receive a system DATA write command SDW _ CMD and system DATA SYS _ DATA from the memory controller 200. If the system DATA write condition is satisfied, the memory device 100 may receive the system DATA write command SDW _ CMD and the system DATA SYS _ DATA at a write time point determined based on the SPO LEVEL SPO _ LEVEL. When receiving the system DATA write command SDW _ CMD and the system DATA SYS _ DATA from the memory controller 200, the memory device 100 may determine to write the received system DATA SYS _ DATA.

In the case where the memory device 100 has determined that the system DATA SYS _ DATA is written (yes at S1503), the process proceeds to step S1505. In the case where the memory device 100 has determined not to write the system DATA SYS _ DATA (S1503, no), the process proceeds to step S1507.

In step S1505, the memory device 100 may write the system DATA SYS _ DATA received from the system DATA control unit 230. In various embodiments, the system DATA SYS _ DATA may include mapping information including the PBA received with the write command. Therefore, the point in time at which the system DATA SYS _ DATA is written can be delayed as much as possible. Further, since the time point of writing the system DATA SYS _ DATA may be delayed as much as possible, the system DATA SYS _ DATA including a large amount of information may be stored in the memory device 100.

In step S1507, the memory device 100 may execute the write command. In various embodiments, the memory device 100 may receive a write command, an address, and write data from the memory controller 200 and perform an operation corresponding to the write command. In the case where it has been determined to write the system DATA, the memory device 100 may write the system DATA SYS _ DATA and then perform an operation corresponding to the write command. In the case where the memory device 100 does not write the system DATA SYS _ DATA, the memory device 100 may omit the operation of writing the system DATA SYS _ DATA and directly perform the operation corresponding to the write command.

Fig. 16 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 2 or 3) according to an embodiment of the present disclosure.

Referring to fig. 16, in step S1601, the SPO level determination unit 220 may determine the reference time t _ ref. The reference time t _ ref may be a time required to determine the SPO LEVEL SPO _ LEVEL. If the SPO LEVEL determination unit 220 determines the reference time t _ ref, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the SPO occurrence count number SPO _ NUM indicating the number of times the SPO event has occurred within the determined reference time t _ ref.

In step S1603, the SPO level determination unit 220 may sense the SPO occurrence count number SPO _ NUM indicating the number of times the SPO event has occurred within the determined reference time t _ ref. In various embodiments, the SPO level determination unit 220 may receive the sensing information SE _ INF from the SPO sensing unit 210 when a SPO event occurs. The sensing information SE _ INF may include information about the time the power was turned off due to the SPO event, and the number of SPO occurrence counts SPO _ NUM. The SPO level determination unit 220 may determine an SPO occurrence count number SPO _ NUM indicating the number of times an SPO event has occurred within the determined reference time t _ ref. The number of SPO occurrence counts SPO _ NUM can be determined based on the sensing information SE _ INF.

In step S1605, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL. The SPO LEVEL SPO _ LEVEL may be determined based on sensing information SE _ INF received from the SPO sensing unit 210. The SPO LEVEL SPO _ LEVEL may be determined based on an SPO occurrence count number SPO _ NUM that indicates the number of times an SPO event has occurred within the reference time t _ ref. In the case where the number of times the SPO event has occurred within the reference time t _ ref is relatively small, the SPO LEVEL SPO _ LEVEL may be determined to be a low LEVEL. In contrast, if the number of times the SPO event has occurred within the reference time t _ ref is relatively large, the SPO LEVEL SPO _ LEVEL may be determined to be a high LEVEL.

Fig. 17 is a diagram illustrating an operation of a memory controller (e.g., memory controller 200 of fig. 2 or 3) according to an embodiment of the present disclosure.

Referring to fig. 17, in step S1701, the SPO level determination unit 220 may determine an SPO occurrence period SPO _ PER. The SPO occurrence period SPO _ PER may be determined based on sensing information SE _ INF received from the SPO sensing unit 210. The SPO occurrence period SPO _ PER may be an average value of the reference count number interrupt electric duration. The reference count number may be the number of times the SPO event has occurred. The reference count number may be stored in the SPO level determination unit 220 in advance. The SPO section may be a section defined from a power-off time point to a power-on time point.

If the SPO occurrence period SPO _ PER is relatively short, SPO events may occur frequently. If the SPO occurrence period SPO _ PER is relatively short, the system DATA control unit 230 needs to write the system DATA SYS _ DATA frequently. Accordingly, a period of time in which the system DATA SYS _ DATA is written to the system DATA storage device 240 or the nonvolatile memory cells of the memory device 100 may be relatively short. The time between the writing time points of the system DATA SYS _ DATA may be reduced. Further, since the SPO occurrence period SPO _ PER is short, the number of types of system DATA SYS _ DATA to be stored can be increased.

In contrast, if the SPO occurrence period SPO _ PER is relatively long, the SPO occurrence frequency may be decreased. If the SPO occurrence period SPO _ PER is relatively long, the system DATA control unit 230 does not need to write the system DATA SYS _ DATA to the nonvolatile memory unit frequently. Therefore, the system DATA (SYS _ DATA) writing period may be relatively long. The time between the writing time points of the system DATA SYS _ DATA may be increased. Further, since the SPO occurrence period SPO _ PER is long, the number of types of system DATA SYS _ DATA to be stored can be reduced.

In step S1703, the SPO LEVEL determination unit 220 may determine the SPO LEVEL SPO _ LEVEL based on the SPO occurrence period SPO _ PER. In an embodiment, the SPO LEVEL SPO _ LEVEL may increase as the SPO occurrence period SPO _ PER decreases. In contrast, as the SPO occurrence period SPO _ PER increases, the SPO LEVEL SPO _ LEVEL may decrease.

Fig. 18 is a diagram illustrating a memory controller 1000, such as memory controller 200 of fig. 1, according to an embodiment of the present disclosure.

Memory controller 1000 is coupled to a host (e.g., host 300 of FIG. 1) and a memory device (e.g., memory device 100 of FIG. 1). The memory controller 1000 may access the memory device 100 in response to a request from the host 300. For example, the memory controller 1000 may control write operations, read operations, erase operations, and background operations of the memory device 100. The memory controller 1000 may provide an interface between the memory device 100 and the host 300. Memory controller 1000 may drive firmware to control memory device 100.

Referring to fig. 18, the memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, a bus 1070, and a system data storage device 1080.

Bus 1070 may provide a channel between the components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and perform logical operations. The processor 1010 may communicate with the host 300 through a host interface 1040 and with the memory device 100 through a memory interface 1060. Additionally, processor 1010 may communicate with memory buffer 1020 through buffer control circuitry 1050. The processor 1010 may control the operation of the storage device by using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by host 300 to Physical Block Addresses (PBAs) through the FTL. The FTL can receive the LBA and use a mapping table to convert the LBA to PBA. The address mapping method using the FTL can be variously modified according to the mapping unit. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

Processor 1010 may randomize data received from the host. For example, processor 1010 may use a randomization seed to randomize data received from host 300. The randomized data may be provided to the memory device 100 as data to be stored and may be programmed to an array of memory cells.

During a read operation, the processor 1010 may derandomize data received from the memory device 100. For example, the processor 1010 may use the derandomization seed to derandomize data received from the memory device 100. The derandomized data can be output to the host 300.

In an embodiment, the processor 1010 may drive software or firmware to perform the randomization operation or the derandomization operation.

In an embodiment, the processor 1010 may perform an operation of determining the type of the system DATA SYS _ DATA to be written in the nonvolatile memory and a writing time point of the system DATA SYS _ DATA. The processor 1010 may include the SPO sensing unit 210, the SPO level determining unit 220, and the system data control unit 230 of fig. 2 and 3.

In various embodiments, processor 1010 may sense the SPO event and record a power-off TIME PO _ TIME, which is a point in TIME when the power is turned off, in the memory device and/or a non-volatile memory included in memory controller 1000. Subsequently, processor 1010 may generate sensing information SE _ INF based on the SPO duration. The sensing information SE _ INF may include at least one of the number of times the SPO event has occurred during the reference time t _ ref and the SPO occurrence period SPO _ PER. The SPO occurrence period SPO _ PER may be an average value of the SPO duration.

The processor 1010 may determine the SPO LEVEL based on the sensing information SE _ INF. The processor 1010 may determine the type of the system DATA SYS _ DATA to be written to the memory device and/or the memory controller 1000 and a writing time point based on the SPO LEVEL SPO _ LEVEL.

In an embodiment, where the sensing information SE _ INF may include information regarding the number of times an SPO event has occurred within the reference time t _ ref, the SPO LEVEL SPO _ LEVEL may increase as the number of times an SPO event has occurred increases. Conversely, as the number of SPO events that have occurred decreases, the SPO LEVEL SPO _ LEVEL may decrease.

In an embodiment, when the sensing information SE _ INF includes information on the SPO occurrence period SPO _ PER, the shorter the SPO occurrence period SPO _ PER is, the higher the SPO LEVEL SPO _ LEVEL may be. Conversely, the longer the SPO occurrence period SPO _ PER, the lower the SPO LEVEL SPO _ LEVEL may be.

If the processor 1010 determines the type of the system DATA SYS _ DATA and the writing time point of the system DATA SYS _ DATA, the processor 1010 may write the determined type of the system DATA SYS _ DATA at the determined writing time point. The processor 1010 may write the system DATA SYS _ DATA to the memory device and/or a nonvolatile memory included in the memory controller 1000.

Memory buffer 1020 may be used as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands to be executed by processor 1010. Memory buffer 1020 may store data to be processed by processor 1010. Memory buffer 1020 may include static ram (sram) or dynamic ram (dram).

ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform ECC encoding operations based on data to be written to the memory device 100 through the memory interface 1060. The ECC encoded data may be transferred to the memory device 100 through the memory interface 1060. The ECC circuit 1030 may perform ECC decoding operations on data received from the memory device 100 through the memory interface 1060. For example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and reduced load DIMM (lrdimm).

The buffer control circuit 1050 may control the memory buffer 1020 under the control of the processor 1010.

The memory interface 1060 may communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory devices over the channels.

For example, memory controller 1000 may include neither memory buffer 1020 nor buffer control circuitry 1050.

For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read only memory) disposed in the memory controller 1000. Alternatively, the processor 1010 may load code from a memory device through the memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transfer data in the memory controller 1000. The control bus may communicate control information, such as commands and addresses, in the memory controller 1000. The data bus and the control bus may be separate from each other and may neither interfere with nor affect each other. The data bus may be coupled to a host interface 1040, a buffer control circuit 1050, an ECC circuit 1030, and a memory interface 1060. The control bus may be coupled to a host interface 1040, processor 1010, buffer control circuit 1050, memory buffer 1020, and memory interface 1060.

System data storage 1080 may perform the same functions as system data storage 240 of fig. 2 and 3. System data storage 1080 may include non-volatile memory. The system DATA storage 1080 may write the system DATA SYS _ DATA at a write time point determined by the processor 1010. In an embodiment, the processor 1010 may output a system DATA write command SDW _ CMD and system DATA SYS _ DATA, and store the system DATA SYS _ DATA in the system DATA storage 1080.

Since the system DATA storage device 1080 includes a nonvolatile memory unit, the system DATA SYS _ DATA stored in the system DATA storage device 1080 can be retained even if the power is turned off. Accordingly, if the power is turned on again after the power is turned off, the storage device including the memory controller 1000 and the memory device 100 may perform a recovery operation based on the system DATA SYS _ DATA stored in the system DATA storage device 1080.

In various embodiments, if an SPO event occurs after system DATA storage 1080 has stored system DATA SYS _ DATA, memory controller 1000 may perform a DATA recovery operation using system DATA SYS _ DATA that has been stored in system DATA storage 1080 immediately before the SPO event occurred.

Fig. 19 is a block diagram illustrating a memory card system 2000 including a storage device according to an embodiment of the present disclosure.

Referring to fig. 19, the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is coupled to the memory device 2200. The memory controller 2100 may access the memory device 2200. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2200 and a host (e.g., host 300 of fig. 1). The memory controller 2100 may drive firmware to control the memory device 2200. The memory device 2200 may be implemented in the same manner as the memory device 100 described with reference to fig. 9.

In an embodiment, memory controller 2100 may include components such as a Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and ECC circuitry.

The memory controller 2100 may communicate with external devices through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller 2100 may communicate with external devices through at least one of various communication protocols such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory at high speed (NVMe) protocols. In an embodiment, the connector 2300 may be defined by at least one of the various communication protocols described above.

In an embodiment, memory device 2200 may be implemented as any of a variety of non-volatile memory devices such as: electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM).

In an embodiment, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card such as: personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) card, smart media card (e.g., SM or SMC), memory stick, multimedia card (e.g., MMC, RS-MMC, or micro MMC), Secure Digital (SD) card (e.g., SD, mini SD, micro SD, or SDHC), or Universal Flash (UFS).

Fig. 20 is a block diagram illustrating a Solid State Drive (SSD) system 3000 including a storage device according to an embodiment of the disclosure.

Referring to fig. 20, SSD system 3000 may include host 3100 and SSD 3200. The SSD 3200 may exchange signals SIG with the host 3100 through the signal connector 3001, and may receive power PWR through the power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

In an embodiment, the SSD controller 3210 may perform the functions of the memory controller 200 described above with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In an embodiment, signal SIG may be a signal based on an interface between host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of various interfaces such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory at high speed (NVMe) interfaces.

The auxiliary power supply 3230 may be coupled to the host 3100 via a power connector 3002. The auxiliary power supply 3230 may be supplied with power PWR from the host 3100 and may be charged by the power PWR. When the supply of power from the host 3100 is not smoothly performed, the auxiliary power supply 3230 may supply power of the SSD 3200. In embodiments, auxiliary power supply 3230 may be located inside SSD 3200 or outside SSD 3200. For example, the auxiliary power supply 3230 may be provided in a motherboard and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDRSDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 21 is a block diagram illustrating a user system 4000 including a storage device according to an embodiment of the present disclosure.

Referring to fig. 21, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may run components included in the user system 4000, an Operating System (OS), or user programs. In an embodiment, the application processor 4100 may include a controller, interface, graphics engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR2 SDRAM, DDR3SDRAM, LPDDR SDARM, and LPDDR 3SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) and then may be provided as a single semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, bluetooth, or Wi-Fi communications. In an embodiment, the network module 4300 may be included in the application processor 4100.

Data may be stored in the memory module 4400. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transfer data stored in the memory module 4400 to the application processor 4100. In an embodiment, the memory module 4400 may be implemented as a non-volatile semiconductor memory device such as: phase change ram (pram), magnetic ram (mram), resistive ram (rram), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

In an embodiment, the memory module 4400 may include a plurality of non-volatile memory devices, and each of the plurality of non-volatile memory devices may operate in the same manner as the memory device 100 described above with reference to fig. 9. The memory module 4400 may operate in the same manner as the memory device 50 described above with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. In an embodiment, user interface 4500 may include user input interfaces such as: a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may further include user output interfaces such as: liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and monitors.

As described above, various embodiments of the present disclosure may provide a memory device capable of changing a system data writing period and a method of operating the same.

Although embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.

The scope of the disclosure, therefore, is not to be restricted except in light of the foregoing description, by the appended claims and their equivalents.

In the embodiments discussed above, all steps may be selectively performed or skipped. In addition, the steps in each embodiment are not always performed in the conventional order. Furthermore, the embodiments disclosed in the present specification and drawings are intended to help those skilled in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. Those skilled in the art to which the present disclosure pertains will readily appreciate that various modifications are possible based on the technical scope of the present disclosure.

Embodiments of the present disclosure have been described with reference to the accompanying drawings, and specific terms or words used in the specification should be construed in accordance with the spirit of the present disclosure, without limiting the subject matter of the present disclosure. It should be understood that many variations and modifications of the basic inventive concepts described herein will still fall within the spirit and scope of the present disclosure, as defined by the appended claims and their equivalents.