阅读说明：本技术 纳米线晶体管元件 (Nanowire transistor element ) 是由 冯立伟 蔡世鸿 洪世芳 林昭宏 郑志祥 于 2015-01-26 设计创作，主要内容包括：本发明公开一种纳米线晶体管元件。具体是公开一种互补式金属氧化物半导体元件,包含基底,包括第一元件区和第二元件区。多个第一纳米线形成于该基底上并位于该第一元件区中,各该第一纳米线分别包含第一半导体核心以及第二半导体核心,其中该第二半导体核心环绕该第一半导体核心,且该第二半导体核心的一晶格常数不同于该第一半导体核心的一晶格常数。多个第二纳米线,形成于该基底上并位于该第二元件区中,其中各该第二纳米线包含该第一半导体核心。第一栅极,环绕部分的各该第一纳米线。第二栅极,环绕部分的各该第二纳米线。(The invention discloses a nanowire transistor element. The CMOS device comprises a substrate including a first device region and a second device region. A plurality of first nanowires are formed on the substrate and located in the first element region, each of the first nanowires includes a first semiconductor core and a second semiconductor core, wherein the second semiconductor core surrounds the first semiconductor core, and a lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core. A plurality of second nanowires formed on the substrate and located in the second device region, wherein each of the second nanowires includes the first semiconductor core. And a first gate surrounding a portion of each of the first nanowires. And a second gate surrounding a portion of each of the second nanowires.)

1. A CMOS device, comprising:

a substrate including a first element region and a second element region;

a plurality of first nanowires formed on the substrate and located in the first device region, each of the first nanowires comprising:

a first semiconductor core; and

a second semiconductor core surrounding the first semiconductor core, the second semiconductor core having a lattice constant different from a lattice constant of the first semiconductor core;

a plurality of second nanowires formed on the substrate and located in the second device region, each of the second nanowires including the first semiconductor core;

a first gate surrounding a portion of each of the first nanowires; and

and a second gate surrounding a portion of each of the second nanowires.

2. The CMOS device of claim 1, wherein said first gate exposes a portion of said second semiconductor core.

3. The CMOS device of claim 1, wherein said first semiconductor core comprises silicon.

4. The CMOS device of claim 3, wherein said second semiconductor core comprises silicon germanium or silicon carbide.

5. The CMOS device of claim 1, further comprising a third semiconductor core formed between said second semiconductor core and said first gate, said first gate exposing a portion of said third semiconductor core.

6. The CMOS device of claim 5, wherein the third semiconductor core comprises silicon.

7. The CMOS device of claim 1, further comprising:

two first connecting pads respectively arranged at two end points of the first nanowires; and

and the two second connecting pads are respectively arranged at two end points of the plurality of second nanowires.

8. The CMOS device as in claim 7, further comprising an insulating layer between said two first pads, said two second pads and said substrate.

9. The CMOS device of claim 7 wherein said two first bonding pads, said two second bonding pads and said first semiconductor core comprise the same material.

10. The CMOS device of claim 1, wherein said second semiconductor core surrounds and completely encapsulates said first semiconductor core.

11. A nanowire transistor element, comprising:

a substrate including a groove;

a nanowire suspended over the recess, wherein the nanowire comprises:

a first semiconductor core; and

a second semiconductor core surrounding the first semiconductor core, the second semiconductor core having a lattice constant different from a lattice constant of the first semiconductor core; and

and a gate surrounding a portion of the nanowire.

12. The nanowire transistor element of claim 11, further comprising:

doped regions formed in the substrate at both sides of the recess; and

two connecting pads, which are arranged at two end points of the nanowire and are positioned on the doped region.

13. The nanowire transistor device of claim 12, wherein the two connection pads, the first semiconductor core and the substrate comprise the same material.

14. The nanowire transistor device of claim 12, wherein the two connection pads and the doped region comprise complementary conductivity types.

15. The nanowire transistor element of claim 11, wherein the first semiconductor core comprises silicon and the second semiconductor core comprises silicon germanium or silicon carbide.

16. The nanowire transistor element of claim 11, wherein the gate exposes a portion of the second semiconductor core.

17. The nanowire transistor element of claim 11, further comprising a third semiconductor core formed between the second semiconductor core and the gate, wherein the gate exposes a portion of the third semiconductor core.

18. The nanowire transistor element of claim 17, wherein the third semiconductor core comprises silicon.

19. The nanowire transistor element of claim 11, wherein the substrate comprises a silicon substrate.

20. The nanowire transistor device of claim 11, wherein the two semiconductor cores surround and completely encapsulate the first semiconductor core.

Technical Field

The present invention relates to a nanowire transistor device, and more particularly, to a multi-core (multiple core) nanowire transistor device.

Background

As devices have been developed to 65 nm technology generation, the conventional planar (MOS) MOS transistor fabrication process is difficult to continue to shrink, and thus, the prior art proposes a solution to replace planar transistor devices with three-dimensional or non-planar (non-planar) multi-gate transistor devices. For example, double-gate (dual-gate) Fin Field effect transistor (FinFET) devices, triple-gate (tri-gate) FinFET devices, and omega (omega) FinFET devices have been proposed. Now, a gate-all-around (GAA) transistor device using a nanowire as a channel is developed as a solution for continuously increasing the device integration and the device performance.

Disclosure of Invention

The invention aims to provide a nanowire transistor element and a manufacturing method thereof.

To achieve the above objective, the present invention provides a cmos device, which includes a substrate including a first device region and a second device region. A plurality of first nanowires are formed on the substrate and located in the first element region, each of the first nanowires includes a first semiconductor core and a second semiconductor core, wherein the second semiconductor core surrounds the first semiconductor core, and a lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core. A plurality of second nanowires formed on the substrate and located in the second device region, wherein each of the second nanowires includes the first semiconductor core. And a first gate surrounding a portion of each of the first nanowires. And a second gate surrounding a portion of each of the second nanowires.

To achieve the above object, the present invention further provides a nanowire transistor device, which includes a substrate including a groove. A nanowire suspended over the recess, wherein the nanowire comprises a first semiconductor core and a second semiconductor core, wherein the second semiconductor core surrounds the first semiconductor core and a lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core. And a gate surrounding a portion of the nanowire.

According to the manufacturing method of the nanowire transistor element provided by the invention, the substrate with the nanowire is subjected to at least one SEG manufacturing process, and another semiconductor epitaxial layer with the lattice constant different from that of the nanowire is formed on the surface of the nanowire so as to increase the carrier mobility of the nanowire channel. Therefore, the nanowire transistor device provided by the present invention is a multi-core nanowire transistor device, each nanowire channel of the multi-core nanowire transistor device comprises at least a first semiconductor core and a second semiconductor core, the first semiconductor core is surrounded and coated by the second semiconductor core, and the second semiconductor core is used as a nanowire channel with high carrier mobility.

Drawings

FIGS. 1A-2C are schematic diagrams of a nanowire transistor device and a method for fabricating the same according to a first preferred embodiment of the present invention, wherein

FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A;

FIG. 2B is an enlarged cross-sectional view taken along line A-A' of FIG. 2A; and

FIG. 2C is a cross-sectional view taken along line B-B' of FIG. 2A;

fig. 3A to 3C, and fig. 3A to 3C are schematic diagrams of a nanowire transistor device and a method for fabricating the same according to a second preferred embodiment of the present invention, wherein

FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A; and

FIG. 3C is an enlarged cross-sectional view taken along line B-B' of FIG. 3A;

FIGS. 4-5 are schematic diagrams of a nanowire transistor device and a method for fabricating the same according to a third preferred embodiment of the present invention;

FIG. 6 is a schematic diagram of a variation of a nanowire transistor device and a method of fabricating the same according to the present invention;

fig. 7 to 8 are schematic views of a nanowire transistor device and a method for fabricating the same according to a fourth preferred embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 200 SOI substrate

200p pMOS element region

200n nMOS element region

102 substrate

102d doped region

104 insulating layer

104r groove

106 semiconductor layer

107. 108 epitaxial layer

110. 210p, 210n nanowires

112 first semiconductor core

114 second semiconductor core

116 third semiconductor core

120. 220p, 220n connection pad

122. 240 patterned hard mask

130. 230p, 230n gate

Tangent lines of A-A' and B-B

Detailed Description

Referring to fig. 1A to 2C, fig. 1A to 2C are schematic diagrams of a nanowire transistor device and a method for fabricating the same according to a first preferred embodiment of the present invention. Referring first to fig. 1A and 1B, fig. 1B is a cross-sectional view taken along line a-a' of fig. 1A. As shown in fig. 1A and fig. 1B, the preferred embodiment first provides a substrate 102, and an insulating layer 104 and a semiconductor layer 106, such as a single crystal silicon layer 106, are sequentially formed on the substrate 102. Therefore, the substrate 102, the insulating layer 104 and the single-crystal silicon layer 106 may form a silicon-on-insulator (SOI) substrate 100. By patterning the single-crystal silicon layer 106 and etching the insulating layer 104, a plurality of nanowires 110 and two connecting pads 120 disposed at two ends of the nanowires 110 are further formed on the substrate 102. As shown in fig. 1B, the insulating layer 104 is etched to further include a groove 104r corresponding to the nanowire 110, so that the nanowire 110 is suspended on the SOI substrate 100, particularly on the insulating layer 104 of the SOI substrate 100, and isolated from the substrate 102. In addition, in the preferred embodiment, the connecting pads 120 are disposed on the insulating layer 104, and thus can be isolated from the substrate 102 by the insulating layer 104. As shown in fig. 1A, the connecting pads 120 are respectively disposed at two ends of each of the nanowires 110, so that the nanowires 110 and the connecting pads 120 can have a stair-step pattern, the nanowires 110 serve as stairs of the stair-step pattern, and the connecting pads 120 can be regarded as pillars of the stair-step pattern.

Please continue to refer to fig. 1A and fig. 1B. The nano-wire 110 may include a first semiconductor core 112, and in the preferred embodiment, the first semiconductor core 112 and the connection pad 120 include the same material, i.e., single crystal silicon, but is not limited thereto. Those skilled in the art will appreciate that in other variations of the present embodiment, the first semiconductor core 112 may comprise other materials, such as germanium. However, in other variations of the preferred embodiment, the first semiconductor core 112 and the bonding pad 120 may comprise different materials. In addition, a silicon layer trimming (Si trimming) step may be selectively performed as needed to further reduce the diameter of the first semiconductor core 112 of the nanowire 110.

Referring to fig. 2A to 2C, fig. 2B is a cross-sectional view taken along line a-a 'of fig. 2A, and fig. 2C is an enlarged cross-sectional view taken along line B-B' of fig. 2A. Next, a first SEG process is performed to form a semiconductor layer, in particular, an epitaxial layer 107, on the substrate. The epitaxial layer 107 may comprise a material having a different lattice constant than the material of the first semiconductor core 112. For example, the epitaxial layer 107 provided in the preferred embodiment may comprise silicon germanium (Si) depending on the conductivity type of the desired transistor_1-XGe_X) Or silicon carbide (SiC). In addition, the germanium content in the epitaxial layer 107 may gradually increase with the time of the fabrication process, mainly to be not more than 60%. However, it should be understood by those skilled in the art that the material of the epitaxial layer 107 is not limited to the silicon germanium or silicon carbide, and gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III-V compound semiconductor (III-V compound semiconductor) material may be used as well, it should be noted that, because of the exposed nature of the epitaxial growth along the surface of the semiconductor layer (e.g., silicon layer) during the SEG process, only the surface of the semiconductor layer 106 will form the epitaxial layer 107. As shown in FIGS. 2B and 2C, because the first semiconductor core 112 is suspended over the substrate 102, the epitaxial layer 107 is formed on the fully exposed surface of the first semiconductor core 112, and surrounds and completely covers the first semiconductor core 112, forming the second semiconductor core 114 as shown in FIGS. 2B and 2C, and the lattice constant of the second semiconductor core 114 is different from that of the first semiconductor core 114 The lattice constant of the core 112, and the second semiconductor core 114 remains separated from the substrate 102. Meanwhile, the epitaxial layer 107 also covers the bonding pads 120, as shown in FIG. 2B.

Next, a gate 130 (shown in fig. 5) is formed on the substrate, and the gate 130 surrounds and covers a portion of each nanowire 110, especially a central portion of each nanowire 110 (shown in fig. 5). The gate 130 may include a gate conductive layer (not shown) and a gate dielectric layer (not shown). In addition, after the gate electrode 130 is formed, dopants may be implanted into the exposed nanowire 110 through an ion implantation process to form a source/drain electrode (not shown). Thus, the fabrication of the nanowire transistor element is completed. It should be noted that, since the nanowire 110 is suspended on the substrate 102, the gate 130 can completely cover the central portion of the nanowire 110, so that the circumferential portion of the nanowire 110 can be used as a channel region, and thus the nanowire transistor device is a full-gate transistor device.

Therefore, no matter what kind of semiconductor material the first semiconductor core 112 of the nanowire 110 comprises, the nanowire transistor device and the manufacturing method thereof according to the preferred embodiment further form an epitaxial layer 107 with a lattice constant different from that of the semiconductor material outside the first semiconductor core 112 as the second semiconductor core 114 by an SEG manufacturing process. That is, the lattice constant of the second semiconductor core 114 of the present preferred embodiment is different from the lattice constant of the first semiconductor core 112. In the preferred embodiment, second semiconductor core 114 may preferably comprise silicon germanium or silicon carbide. That is, the preferred embodiment provides a dual core nanowire transistor element. More importantly, the second semiconductor core 114 may serve as a channel region of the nanowire transistor device to provide higher carrier mobility, thereby contributing to the enhancement of performance and electrical performance of the nanowire transistor device.

Referring to fig. 3A to 3C, fig. 3A to 3C are schematic views illustrating a nanowire transistor device and a method for fabricating the same according to a second preferred embodiment of the present invention, fig. 3B is a cross-sectional view taken along a line a-a 'in fig. 3A, and fig. 3C is an enlarged cross-sectional view taken along a line B-B' in fig. 3A. It should be noted that, in the second preferred embodiment, the same elements as those in the first preferred embodiment are denoted by the same symbols and may include the same material selections, so that the following description is omitted. According to the nanowire transistor device and the manufacturing method thereof provided by the preferred embodiment, as shown in fig. 3A and fig. 3B, a substrate 102 is provided, and an insulating layer 104 and a semiconductor layer 106, such as a single crystal silicon layer 106, are sequentially formed on the substrate 102. As previously described, the substrate 102, the insulating layer 104 and the single crystal silicon layer 106 constitute an SOI substrate 100. The substrate 102 further includes a plurality of nanowires 110 and two connecting pads 120, wherein the connecting pads 120 are respectively disposed at two ends of each nanowire 110. As shown in fig. 3B, the insulating layer 104 further includes a groove 104r corresponding to the nanowire 110, so that the nanowire 110 is suspended on the SOI substrate 100, particularly on the insulating layer 104 of the SOI substrate 100, and isolated from the substrate 102. In addition, in the preferred embodiment, the connecting pads 120 are disposed on the insulating layer 104, and thus can be isolated from the substrate 102 by the insulating layer 104. In addition, as shown in FIG. 3A, the nanowires 110 and the bonding pads 120 may have a stair-step pattern, the nanowires 110 serve as steps of the stair-step pattern, and the bonding pads 120 may be regarded as pillars of the stair-step pattern.

Please continue to refer to fig. 3A and fig. 3B. The nano-wires 110 may include the first semiconductor core 112, and in the preferred embodiment, the material selection of the first semiconductor core 112 and the bonding pad 120 is the same as that of the first preferred embodiment, and therefore, the detailed description thereof is omitted. In addition, a silicon layer trimming step may be optionally performed to further reduce the diameter of the first semiconductor core 112 of the nanowire 110, as desired.

Please continue to refer to fig. 3A to fig. 3C. Next, a first SEG process is performed to form a semiconductor layer, in particular, an epitaxial layer 107, on the substrate. The epitaxial layer 107 may comprise a material having a different lattice constant than the material of the first semiconductor core 112. The material selection of the epitaxial layer 107 is the same as that of the first preferred embodiment, and therefore, is not described herein again. As mentioned above, since the epitaxial layer is formed along the surface of the semiconductor layer (e.g., silicon layer) in the SEG process, only the exposed surface of the semiconductor layer 106 forms the epitaxial layer 107. As shown in fig. 3B and 3C, since the first semiconductor core 112 is completely suspended above the substrate 102, the epitaxial layer 107 surrounds and completely covers the first semiconductor core 112, so as to form the second semiconductor core 114 shown in fig. 3B and 3C, and the second semiconductor core 114 is still suspended above the substrate 102. And as previously described, the lattice constant of the second semiconductor core 114 is different from the lattice constant of the first semiconductor core 112.

Please still refer to fig. 3A to 3C. After the first SEG process, a second SEG process is performed to form an epitaxial layer 108 on the semiconductor layer 106. Epitaxial layer 108 may comprise a material having a different lattice constant than the material of epitaxial layer 107. in the preferred embodiment, epitaxial layer 108 preferably comprises silicon, but is not limited thereto. As mentioned above, since the epitaxial layer is formed along the surface of the semiconductor layer during the SEG process, only the exposed surface of the epitaxial layer 107 will form the epitaxial layer 108. As shown in fig. 3B and 3C, since the second semiconductor core 114 is still fully suspended on the substrate 102, the epitaxial layer 108 surrounds and completely covers the second semiconductor core 114, so as to form the third semiconductor core 116 shown in fig. 3B and 3C, and the third semiconductor core 116 is still suspended on the substrate 102.

Next, a gate 130 (shown in fig. 5) is formed on the substrate, and the gate 130 surrounds and covers a portion of each nanowire 110, especially a central portion of each nanowire 110 (shown in fig. 5). The gate 130 may include a gate conductive layer (not shown) and a gate dielectric layer (not shown). It is noted that the portion of the nanowire 110 covered by the gate 130 can serve as a nanowire channel. In addition, after the gate electrode 130 is formed, dopants may be implanted into the exposed nanowire 110 through an ion implantation process to form a source/drain electrode (not shown). Thus, the fabrication of the nanowire transistor element is completed.

As can be seen, no matter what kind of semiconductor material the first semiconductor core 112 of the nanowire 110 comprises, the nanowire transistor device and the method for fabricating the same according to the preferred embodiment of the present invention are formed by two SEG fabrication processes on the semiconductor material, i.e., the second semiconductor core 114 and the third semiconductor core 116 are formed outside the first semiconductor core 112, wherein the lattice constant of the second semiconductor core 114 is different from the lattice constant of the first semiconductor core 112, and the third semiconductor core 116 is preferably silicon. That is, the present preferred embodiment provides a triple core nanowire transistor element. In the three-core nanowire transistor device, the second semiconductor core 114 may serve as a channel region of the nanowire transistor device to provide higher carrier mobility, thereby contributing to the improvement of the performance and electrical performance of the nanowire transistor device. In the three-core nanowire transistor device, the third semiconductor core 116 disposed between the gate and the second semiconductor core 114 is used to improve the interface between the nanowire 110 and the gate dielectric layer. In addition, the epitaxial layer 108 formed on the surface of the bonding pad 120 can be used as a place for forming metal silicide during a subsequent metal silicide fabrication process on the bonding pad 120, so as to avoid the problem that silicon germanium and other materials often form agglomeration (agglomeration) in the metal silicide fabrication process.

Referring to fig. 4 to 5, fig. 4 to 5 are schematic views illustrating a nanowire transistor device and a method for fabricating the same according to a third preferred embodiment of the present invention. It should be noted that, in the present preferred embodiment, the same elements in the second preferred embodiment as those in the first preferred embodiment are denoted by the same symbols and may include the same material selections, so that the following descriptions are omitted. According to the nanowire transistor device and the method for fabricating the same provided by the preferred embodiment, an SOI substrate 100 is provided, and the SOI substrate 100 may sequentially include a substrate, an insulating layer and a semiconductor layer, such as a single crystal silicon layer, as described above. By patterning the single crystal silicon layer and etching the insulating layer, a plurality of nanowires 110 and two connection pads 120 are formed on the substrate, and the connection pads 120 are respectively disposed at two ends of each nanowire 110. As described above, the insulating layer of the SOI substrate 100 further includes a groove at a position corresponding to the nanowire 110, so that the nanowire 110 is suspended on the SOI substrate 100, particularly, the insulating layer of the SOI substrate 100. In addition, in the preferred embodiment, the connecting pad 120 is disposed on the insulating layer, so that it can be isolated from the substrate by the insulating layer. In addition, as shown in FIG. 4, the nanowires 110 and the connecting pads 120 may have a stair-step pattern, the nanowires 110 serve as steps of the stair-step pattern, and the connecting pads 120 may be regarded as pillars of the stair-step pattern.

Please continue to refer to fig. 4. The nano-wires 110 may include the first semiconductor core 112, and in the preferred embodiment, the material selection of the first semiconductor core 112 and the bonding pad 120 is the same as that of the first preferred embodiment, and therefore, the detailed description thereof is omitted. In addition, a silicon layer trimming step may be optionally performed to further reduce the diameter of the first semiconductor core 112 of the nanowire 110, as desired.

Please continue to refer to fig. 4. Next, a patterned hard mask 122 is formed on the SOI substrate 100, and the patterned hard mask 122 completely covers the connecting pad 120. In addition, the patterned hard mask 122 may also cover a portion of the first semiconductor core 112. Next, a first SEG process is performed to form an epitaxial layer on the semiconductor layer. The epitaxial layer may comprise a material having a lattice constant different from that of the first semiconductor core 112, and the material selection of the epitaxial layer is the same as that of the first preferred embodiment, so that the description thereof is omitted here. As mentioned above, since the epitaxial layer is formed along the surface of the semiconductor layer (e.g., silicon layer) in the SEG process, only the exposed surface of the semiconductor layer of the nanowires 110 forms the epitaxial layer. And since the first semiconductor core 112 is completely suspended above the SOI substrate 100, the epitaxial layer surrounds and completely encapsulates the first semiconductor core 112, forming a second semiconductor core 114, and the second semiconductor core 114 is still suspended above the SOI substrate 100. And as previously described, the lattice constant of the second semiconductor core 114 is different from the lattice constant of the first semiconductor core 112.

After the first SEG process, a gate 130 is subsequently formed on the SOI substrate 100. The gate 130 surrounds and encapsulates a portion of each nanowire 110, particularly a central portion of each nanowire 110. The gate 130 may include a gate conductive layer (not shown) and a gate dielectric layer (not shown). One skilled in the art will appreciate that the gate 130 may comprise a gate dielectric layer and a gate conductive layer. In the preferred embodiment, the gate dielectric layer may comprise any suitable dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or any suitable high dielectric constant (high-k) material. The gate conductive layer may comprise polysilicon, or even a work function metal layer required for a metal gate. It is noted that the portion of the nanowire 110 covered by the gate 130 can serve as a nanowire channel. In addition, after the gate 130 is formed, the patterned hard mask 122 may be removed, and then, dopants may be implanted into the exposed nanowires 110 by an ion implantation process to form source/drain regions (not shown). Thus, the fabrication of the nanowire transistor element is completed. The following process includes forming an interlayer dielectric layer to fill the gap of the trench 104r and cover the gate, the source/drain, and forming appropriate metal interconnects to connect the gate, the source/drain, and the like, which are not described in detail herein.

It is noted that the patterned hard mask 122 may comprise any suitable dielectric layer, such as silicon nitride, silicon carbide nitride, or silicon oxynitride. In addition, the timing of the removal of the patterned hard mask may be adjusted according to the requirements of the metal silicide fabrication process, for example, the removal may be performed before or after the gate is formed, or the patterned hard mask may not be removed if no metal silicide is formed on the pad 120.

According to the nanowire transistor device and the method of fabricating the same provided by the preferred embodiment, no matter what kind of semiconductor material the first semiconductor core 112 of the nanowire 110 comprises, the second semiconductor core 114 is formed outside the first semiconductor core 112 by an SEG fabrication process, wherein the lattice constant of the second semiconductor core 114 is different from the lattice constant of the first semiconductor core 112. That is, the present preferred embodiment provides a two-core nanowire transistor element. In the two-core nanowire transistor device, the second semiconductor core 114 may serve as a channel region of the nanowire transistor device to provide higher carrier mobility, thereby contributing to the enhancement of performance and electrical performance of the nanowire transistor device. Since the channel region of the nanowire transistor element exists only at the overlapping portion of the nanowire 110 and the gate 130, which is mostly the center of the nanowire 110, the second semiconductor core 114 of the preferred embodiment is also formed only on a portion of the surface of the first semiconductor core 112, especially the surface of the central portion thereof, so as to enhance the carrier mobility of the channel region as described above. In the SEG process, the bonding pad 120 is protected by the patterned hard mask 122, so that the surface of the bonding pad does not grow an epitaxial layer, and a silicon layer surface is still maintained. Therefore, when the subsequent metal silicide manufacturing process is performed on the connecting pad 120, the silicon surface can be used as a forming place of the metal silicide, so as to avoid the problem that materials such as silicon germanium and the like often form agglomeration in the metal silicide manufacturing process.

Referring to fig. 6, fig. 6 is a schematic diagram of a variation of a nanowire transistor device and a method for fabricating the same according to the present invention. It should be noted that, in the preferred embodiment, the same elements as those in the previous preferred embodiment are denoted by the same symbols and may include the same material selections, so that the following description is omitted. According to the nanowire transistor device and the manufacturing method thereof provided by the present variation, a silicon substrate 102 is provided, and the silicon substrate 102 may include an insulating layer 104 therein. The silicon substrate 102 further includes a plurality of nanowires 110 and two connecting pads 120, and the connecting pads 120 are respectively disposed at two ends of each nanowire 110. The insulating layer of the silicon substrate 100 further includes a groove 104r corresponding to the nanowire 110, so that the nanowire 110 is suspended on the silicon substrate 102, especially on the insulating layer 104 of the silicon substrate 102. In addition, in the present variation, the bonding pad 120 and the silicon substrate 102 comprise the same silicon material. However, as shown in FIG. 6, the bonding pads 120 and the silicon substrate 102 may comprise complementary conductive types. For example, when the nanowire transistor is a p-type metal oxide semiconductor (pMOS) transistor device, the pad 120 includes p-type dopant, and the substrate 102 corresponding to the pad 120 includes an n-type doped region 102 d. When the nanowire transistor is an n-type metal oxide semiconductor (nMOS) transistor device, the pad 120 includes n-type dopants, and the substrate 102 corresponding to the pad 120 includes a p-type doped region 102d, such a complementary conductivity type ensures electrical isolation between the pad 120 and the substrate 102. As mentioned above, the connecting pad 120 and the nano-wires 110 may form a stair-step pattern, the nano-wires 110 serve as the stair steps of the stair-step pattern, and the connecting pad 120 may be regarded as the ladder pillars of the stair-step pattern.

Please continue to refer to fig. 6. The nano-wires 110 may include the first semiconductor core 112, and in the preferred embodiment, the material selection of the first semiconductor core 112 and the bonding pad 120 is the same as that of the first preferred embodiment, and therefore, the detailed description thereof is omitted. In addition, a silicon layer trimming step may be optionally performed to further reduce the diameter of the first semiconductor core 112 of the nanowire 110, as desired. Next, the first SEG process is performed on the nanowires 110 to form a second semiconductor core 114 on the surface of the first semiconductor core 112 of the nanowires 110 (shown in fig. 2B). Alternatively, a second SEG process may be performed to form a third semiconductor core 116 on the surface of the second semiconductor core 114 (shown in fig. 3B), depending on the product requirements. The material selection of the second semiconductor core 114 and the third semiconductor core 116 is the same as that of the previous embodiment, and therefore, the description thereof is omitted. Of course, the present variation can also be similar to the aforementioned third preferred embodiment, in which the second semiconductor core is formed only in the central portion of the nano-wire 110, and the bonding pad 120 still includes a silicon material surface.

Similarly, after the fabrication of the multi-core nanowires is completed, a gate (not shown) may be formed on the substrate 102, wherein the gate surrounds and covers a portion of each nanowire 110, and particularly, a central portion of each nanowire 110. The gate 130 may include a gate conductive layer (not shown) and a gate dielectric layer (not shown). It is noted that the portion of the nanowire 110 covered by the gate can be used as a nanowire channel. In addition, after the gate electrode is formed, a dopant may be further implanted into the exposed nanowire 110 through an ion implantation process to form a source/drain electrode (not shown). Thus, the fabrication of the nanowire transistor element is completed.

According to the nanowire transistor device and the manufacturing method thereof provided by the present variation, the present invention is not limited to the technical scheme of using the SOI substrate as the construction substrate of the nanowire transistor, but can adopt the existing common silicon substrate. In other words, the nanowire transistor device and the manufacturing method thereof provided by the invention have more flexible manufacturing process and can be directly integrated with the existing manufacturing process.

Referring to fig. 7 to 8, fig. 7 to 8 are schematic views of a nanowire transistor device and a method for fabricating the same according to a fourth preferred embodiment of the present invention. It should be noted that the fabrication method provided in the preferred embodiment can be used to fabricate a complementary metal-oxide-semiconductor (CMOS) device including a nanowire transistor. As shown in fig. 7, the CMOS device may be formed on a substrate 200, such as the aforementioned SOI substrate 200, and an nMOS device region 200n and a pMOS device region 200p may be defined on the SOI substrate 200. A plurality of nanowires 210n are formed in the nMOS device region 200n, and are connected to each other through connection pads 220n provided at both ends. Similarly, a plurality of nanowires 210p are formed in the pMOS element region 200p, and are connected to each other through connection pads 220p disposed at both ends. Next, a patterned hard mask 240 is formed in the nMOS device region 200n to cover and protect the nMOS device region 200 n. As described above, each of the nanowires 210n and 210p comprises a first semiconductor core, and the first semiconductor core and the bonding pad may comprise the same material. Since the material selection of the first semiconductor core is the same as that of the previous embodiment, it is not described herein again.

Next, the first SEG process is performed on the pMOS device region 200p to form a second semiconductor core surrounding and encapsulating the first semiconductor core on the surface of the first semiconductor core of the nanowire 210p, and to form an epitaxial layer on the bonding pad 220 p. Since the first SEG fabrication process is performed for the pMOS device, the second semiconductor core and the epitaxial layer preferably include SiGe, but are not limited thereto. Next, according to the product requirement, a second SEG manufacturing process is performed to form a third semiconductor core surrounding and wrapping the second semiconductor core on the surface of the second semiconductor core, and an epitaxial layer is formed on the connection pad 220p, and the third semiconductor core and the epitaxial layer preferably include silicon, but are not limited thereto. Cross-sectional views of the first semiconductor core, the second semiconductor core, and the third semiconductor core can be seen in fig. 2C and 3C, and are not shown here. Subsequently, the patterned hard mask 240 is removed, and the gate (shown in fig. 5), the source/drain, the metal silicide, and other manufacturing steps can be performed sequentially, which are not described herein again.

Of course, after removing the patterned hard mask 240, another patterned hard mask (not shown) may be formed on the pMOS device region 200 p. A first SEG process is further performed on the nMOS device region 200n to form a second semiconductor core surrounding and encapsulating the first semiconductor core on the surface of the nanowire 210n and to form an epitaxial layer on the bonding pad 220 n. Since this first SEG fabrication process is performed for nMOS devices, the second semiconductor core preferably includes SiC, but is not limited thereto. Next, according to the product requirement, a second SEG manufacturing process is performed to form a third semiconductor core surrounding and wrapping the second semiconductor core on the surface of the second semiconductor core, and an epitaxial layer is formed on the connection pad 220n, and the third semiconductor core and the epitaxial layer preferably include silicon, but are not limited thereto. Cross-sectional views of the first semiconductor core, the second semiconductor core, and the third semiconductor core can also be seen in fig. 2C and 3C, and are not shown here.

Please refer to fig. 8. After the SEG fabrication process is completed, a gate 230p covering a portion of each nanowire 210p is formed in the pMOS device region 200p, and a gate 230n covering a portion of each nanowire 210n is formed in the nMOS device region 200 n. One skilled in the art will appreciate that the gates 230p and 230n may comprise a gate dielectric layer and a gate conductive layer. In the preferred embodiment, the gate dielectric layer may comprise any suitable dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or any suitable high dielectric constant (high-k) material. The gate conductive layer may comprise polysilicon, or even a work function metal layer required for a metal gate. After the gates 230p and 230n are formed, source/drain and silicide fabrication steps may be performed, which are not described herein.

According to the nanowire transistor element and the method of fabricating the same provided in the preferred embodiment, the nMOS transistor and the pMOS transistor constituting the CMOS element may also include a multi-core nanowire. By using the second semiconductor core of the multi-core nanowire as a channel region, the carrier mobility can be increased through the characteristic that the lattice constant is different from that of the silicon substrate. In addition, the interface between the nanowire and the grid dielectric layer can be improved by utilizing the third semiconductor core of the multi-core nanowire, and the caking problem possibly caused by the metal silicide manufacturing process of the connecting pad is avoided. More importantly, the method provided by the invention can be completely integrated with the existing manufacturing process for manufacturing the CMOS element, and the CMOS element consisting of the nanowire pMOS transistor and the nanowire nMOS transistor is manufactured on the premise of not increasing the complexity of the manufacturing process.

According to the manufacturing method of the nanowire transistor element provided by the invention, the substrate formed with the nanowire is subjected to at least one SEG manufacturing process, and another semiconductor epitaxial layer with the lattice constant different from that of the nanowire is formed on the surface of the nanowire so as to increase the carrier mobility of the nanowire channel. Therefore, the nanowire transistor element provided by the invention is a multi-core nanowire transistor element, each nanowire channel of the multi-core nanowire transistor element respectively comprises at least a first semiconductor core and a second semiconductor core, the first semiconductor core is surrounded and coated by the second semiconductor core, and the second semiconductor core is used as a nanowire channel with higher carrier mobility. In addition, through the second SEG process, each nanowire channel of the multi-core nanowire transistor device may further include a third semiconductor core, and the second semiconductor core and the first semiconductor core are surrounded and wrapped by the third semiconductor core, and the third semiconductor core may improve an interface between the nanowire and the gate dielectric layer. In addition, the nanowire transistor element and the manufacturing method thereof provided by the invention can be integrated in the manufacturing process of an SOI substrate or a manufacturing process of a common silicon substrate, and the nanowire transistor element and the manufacturing method thereof provided by the invention can be further integrated in the manufacturing process of a CMOS element. In short, the nanowire transistor element and the manufacturing method thereof provided by the invention have great manufacturing process flexibility, and can be successfully integrated with the existing manufacturing process on the premise of not excessively increasing the complexity of the manufacturing process.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.