阅读说明：本技术 晶体管以及集成电路 (Transistor and integrated circuit ) 是由 刘君 于 2020-05-21 设计创作，主要内容包括：本申请实施例提供一种晶体管,包括衬底、网状栅极、源极以及漏极,网状栅极位于所述衬底上,所述网状栅极包括沿第一方向间隔分布的第一部分和沿第二方向间隔分布的第二部分,多个所述第一部分和多个所述第二部分交错分布将所述衬底分隔成多个分隔区域,其中,第一方向与第二方向垂直,所述源极和所述漏极沿第一方向交替分布于所述分隔区域中,且所述源极和所述漏极沿第二方向交替分布于所述分隔区域中。本申请实施例提供的晶体管不仅能够驱动较大的输出电流,还具有较小的面积。本申请实施例还提供一种集成电路,包括上述晶体管。(The embodiment of the application provides a transistor, which comprises a substrate, a mesh gate, a source electrode and a drain electrode, wherein the mesh gate is positioned on the substrate, the mesh gate comprises first parts and second parts, the first parts are distributed at intervals along a first direction, the second parts are distributed at intervals along a second direction, the substrate is divided into a plurality of separation areas by the staggered distribution of the first parts and the second parts, the first direction is vertical to the second direction, the source electrode and the drain electrode are alternately distributed in the separation areas along the first direction, and the source electrode and the drain electrode are alternately distributed in the separation areas along the second direction. The transistor provided by the embodiment of the application not only can drive larger output current, but also has smaller area. The embodiment of the application also provides an integrated circuit which comprises the transistor.)

1. A transistor, comprising:

a substrate;

the mesh grid is positioned on the substrate and comprises first parts distributed at intervals along a first direction and second parts distributed at intervals along a second direction, the first parts and the second parts are distributed in a staggered mode to divide the substrate into a plurality of divided areas, and the first direction is perpendicular to the second direction;

a source electrode; and

and the source electrodes and the drain electrodes are alternately distributed in the separation region along a first direction, and the source electrodes and the drain electrodes are alternately distributed in the separation region along a second direction.

2. The transistor of claim 1, wherein an area of the adjacent source electrode is not equal to an area of the drain electrode.

3. The transistor according to claim 1 or 2, wherein the transistor includes a plurality of contact holes in the separation region, and the number of the contact holes in at least one of the separation regions is plural.

4. The transistor of claim 3, wherein the transistor is an N-type metal oxide semiconductor field effect transistor, and wherein a total area of the drain is greater than a total area of the source.

5. The transistor according to claim 4, wherein the number of the contact holes in at least one of the drain electrodes is plural, and the plural contact holes in the drain electrode are distributed in a first direction and a second direction.

6. The transistor of claim 4, wherein the total number of contact holes in the drain is greater than the total number of contact holes in the source.

7. The transistor of claim 3, wherein the transistor is a P-type metal oxide semiconductor field effect transistor, and wherein a total area of the source electrodes is greater than a total area of the drain electrodes.

8. The transistor of claim 7, wherein the number of the contact holes in at least one of the source electrodes is plural, and the plural contact holes in the source electrode are distributed along a first direction and a second direction.

9. The transistor of claim 7, wherein the total number of contact holes within the source is greater than the total number of contact holes within the drain.

10. The transistor of claim 1 or 2, wherein a total number of the first portions is not equal to a total number of the second portions.

11. An integrated circuit, comprising: a transistor as claimed in any one of claims 1 to 10.

Technical Field

The present application relates to the field of semiconductor device technology, and more particularly, to a transistor and an integrated circuit.

Background

In many circuits, a metal oxide semiconductor field effect transistor capable of driving a large output current is required, and in order to achieve a suitable output current driving capability of the conventional metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor is generally large in size.

Disclosure of Invention

In view of the above, it is desirable to provide a transistor and an integrated circuit, the transistor having a smaller size. In order to achieve the above effect, the technical solution of the embodiment of the present application is implemented as follows:

an aspect of an embodiment of the present application provides a transistor, including:

a substrate;

the mesh grid is positioned on the substrate and comprises first parts distributed at intervals along a first direction and second parts distributed at intervals along a second direction, the first parts and the second parts are distributed in a staggered mode to divide the substrate into a plurality of divided areas, and the first direction is perpendicular to the second direction;

a source electrode; and

and the source electrodes and the drain electrodes are alternately distributed in the separation region along a first direction, and the source electrodes and the drain electrodes are alternately distributed in the separation region along a second direction.

Further, the area of the adjacent source electrode is not equal to the area of the drain electrode.

Further, the transistor comprises contact holes located in the separation regions, and the number of the contact holes in at least one of the separation regions is multiple.

Further, the transistor is an N-type metal oxide semiconductor field effect transistor, and the total area of the drain electrodes is larger than that of the source electrodes.

Further, the number of the contact holes in at least one of the drain electrodes is plural, and the plural contact holes in the drain electrode are distributed along a first direction and a second direction.

Further, the total number of the contact holes in the drain electrode is larger than the total number of the contact holes in the source electrode.

Further, the transistor is a P-type metal oxide semiconductor field effect transistor, and the total area of the source electrodes is larger than that of the drain electrodes.

Further, the number of the contact holes in at least one of the source electrodes is plural, and the plural contact holes in the source electrode are distributed along a first direction and a second direction.

Further, the total number of the contact holes in the source electrode is larger than the total number of the contact holes in the drain electrode.

Further, the total number of the first portions is not equal to the total number of the second portions.

In another aspect, an integrated circuit is provided, which includes the transistor described in any one of the above embodiments.

The transistor provided by the embodiment of the application not only can drive larger output current, but also has smaller area, so that parasitic resistance and parasitic capacitance of the transistor can be effectively reduced. The integrated circuit provided by the embodiment of the application comprises the transistor, and the transistor provided by the embodiment of the application has a smaller area, so that the occupation of excessive area of the integrated circuit can be avoided, the integrated circuit layout is more compact, the integration level is higher, and the occupied area of the integrated circuit is smaller.

Drawings

FIG. 1 is a schematic plan view of a MOSFET in a first embodiment of the prior art;

FIG. 2 is a schematic plan view of a MOSFET in a second embodiment of the prior art;

FIG. 3 is a schematic plan view of a transistor in a first embodiment of the present application;

FIG. 4 is a schematic plan view of the minimum unit cell of the transistor of FIG. 3;

FIG. 5 is a schematic plan view of a transistor in a second embodiment of the present application;

fig. 6 is a schematic plan view of the minimum unit cell of the transistor of fig. 4.

Description of the reference numerals

A transistor 100; n-type metal oxide semiconductor field effect transistors 100', 100 "; a mesh grid 10; a first portion 11; a second portion 12; a source electrode 20; a drain electrode 30; and contact holes 40.

Detailed Description

It should be noted that, in the present application, technical features in examples and embodiments may be combined with each other without conflict, and the detailed description in the specific embodiment should be understood as an explanation of the gist of the present application and should not be construed as an improper limitation to the present application.

The present application will now be described in further detail with reference to the accompanying drawings and specific examples. The term "μm" in the embodiments of the present application refers to the international unit of micrometers, and the orientation or positional relationship in the description of the present application is based on the orientation or positional relationship in fig. 3 and 5, it should be understood that these orientation terms are only used for convenience of description and simplification of the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and the embodiments of the present application are enlarged for convenience of illustration, and the dimensions in the drawings do not represent actual dimensions, and thus should not be construed as limiting the present application.

Referring to fig. 3 to 6, in one aspect, a transistor is provided according to an embodiment of the present invention, the transistor 100 includes a substrate, a mesh gate 10, a source 20, and a drain 30. A mesh gate 10 is located on the substrate. The mesh grid 10 includes first portions 11 spaced apart along a first direction and second portions 12 spaced apart along a second direction. The plurality of first portions 11 and the plurality of second portions 12 are alternately arranged to partition the substrate into a plurality of partitioned areas. Wherein the first direction is perpendicular to the second direction. The source electrodes 20 and the drain electrodes 30 are alternately distributed in the separation region along the first direction, and the source electrodes 20 and the drain electrodes 30 are alternately distributed in the separation region along the second direction.

For convenience of description in the embodiment of the present application, in fig. 3 to fig. 6, structures such as a substrate, an active region, and a contact hole of a mesh Gate are not shown, and it can be understood by those skilled in the art that the Transistor 100 of the embodiment of the present application may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), where ions are diffused on the substrate to form a Drain (Drain) and a Source (Source), an insulating layer is provided between the Gate dielectric and the substrate, the insulating layer and the Gate dielectric together form a Gate (Gate), the substrate under the insulating layer forms a channel, and the Drain and the Source are located at two sides of the channel. And the drain electrode, the source electrode and the grid electrode are respectively and electrically connected with the metal layer through the contact holes, so that the conduction of the integrated circuit is realized, and the length of the grid electrode is the length of the channel. The gate dielectric may be polysilicon. The substrate may be monocrystalline silicon, polycrystalline silicon, gallium arsenide, and other semiconductors, and the form of the substrate in the embodiment of the present application is not limited. The insulating layer between the gate dielectric and the substrate may be an oxide or other insulating substances, for example, the insulating layer may be silicon dioxide, silicon oxynitride, or the like, and the material of the insulating layer in this embodiment is not limited.

The mosfet generally includes a P-type mosfet and an N-type mosfet according to a difference in polarity of carriers of a channel under a gate. The P-type mosfet refers to a mosfet using holes as channel carriers, and the substrate of the P-type mosfet is usually an N-type substrate, but it is needless to say that an N-well may be formed on the P-type substrate, and ions may be diffused on the N-well to form a drain and a source. And the source electrode of the P-type metal oxide semiconductor field effect transistor is connected with the output end. An N-type mosfet refers to a mosfet that uses electrons as channel carriers, and a P-type mosfet usually has an N-type substrate as a substrate. It is of course also possible to form a P-well on an N-type substrate and then diffuse ions on the P-well to form the drain and source. The drain electrode of the N-type metal oxide semiconductor field effect transistor is connected with the output end.

In the embodiment of the present application, the adjacent first portion 11 and the second portion 12 together enclose a separation region (see fig. 4 and 6). The source electrodes 20 and the drain electrodes 30 are alternately distributed in the separation region along the first direction, and the source electrodes 20 and the drain electrodes 30 are alternately distributed in the separation region along the second direction. That is, the first portion 11 has the source electrode 20 and the drain electrode 30 on both sides in the first direction, and the second portion 12 has the source electrode 20 and the drain electrode 30 on both sides in the second direction. In this manner, a longer channel can be formed over a smaller area of the substrate, so that a transistor capable of driving a larger output current can be formed over a smaller area of the substrate. The transistor 100 provided by the embodiment of the application can drive a larger output current and has a smaller area, so that the parasitic resistance and the parasitic capacitance of the transistor 100 can be effectively reduced. Because the transistor 100 provided by the embodiment of the application has a smaller area, the occupation of excessive area of the integrated circuit can be avoided, so that the integrated circuit layout is more compact, the integration level is higher, and the occupied area of the integrated circuit is smaller.

In the present embodiment, the plurality means two or more. In the embodiment of the present application, the first portion 11 and the second portion 12 may have an elongated structure. For convenience and clarity, all the contact holes on the source electrode and all the drain electrode are not shown in fig. 3 to fig. 6, and those skilled in the art can directly obtain the distribution of the contact holes on the source electrode and the drain electrode according to the scheme described in the embodiments of the present application, and details thereof are not repeated herein.

In one embodiment, referring to fig. 5 and 6, the area of the adjacent source electrode 20 is not equal to the area of the drain electrode 30. That is, the source 20 and the drain 30 are asymmetric. In this manner, the area of the transistor 100 can be further reduced.

In another embodiment, referring to fig. 3 and 4, the area of the adjacent source 20 is equal to the area of the drain 30. That is, the source 20 and the drain 30 are symmetrical.

In one embodiment, referring to fig. 3 to 6, the transistor 100 includes a plurality of contact holes 40 in the partition regions, and the number of the contact holes 40 in at least one of the partition regions is plural. A plurality of contact holes 40 so that the source electrode 20 and/or the drain electrode 30 are better electrically connected with the metal layer. That is, there may be a plurality of contact holes 40 in at least one source electrode 20; a plurality of contact holes 40 may be formed in at least one of the drain electrodes 30; there may also be a plurality of contact holes 40 in each of the plurality of source electrodes 20 and the plurality of drain electrodes 30.

In one embodiment, referring to fig. 3-6, the transistor 100 is an nmos field effect transistor, and the total area of the drain 30 is larger than the total area of the source 20. I.e. the sum of the areas of all the drains 30 is larger than the sum of the areas of all the sources 30. Since the drain 30 of the nmos is electrically connected to the output terminal, so that the total area of the drain 30 is larger than the total area of the source 20, the area of the drain 30 is larger under the condition that the nmos has a smaller area, so that the drain 30 is better electrically connected to the output terminal.

In an embodiment, referring to fig. 3 to 6, the number of the contact holes 40 in at least one of the drain electrodes 30 is plural, and the plurality of contact holes 40 in the drain electrode 30 are distributed along the first direction and the second direction. That is, the one and/or more drain electrodes 30 have a plurality of contact holes 40 therein, and the plurality of contact holes 40 of the drain electrodes 30 are distributed in a two-dimensional matrix along the first direction and the second direction. In this way, more contact holes 40 can be provided in the drain electrode 30 so that the drain electrode 30 is better electrically connected with the metal layer.

In one embodiment, referring to fig. 3 to 6, the total number of the contact holes 40 in the drain 30 is greater than the total number of the contact holes 40 in the source 20. That is, the sum of the number of the contact holes 40 in all the drain electrodes 30 is greater than the sum of the number of the contact holes 40 in all the source electrodes 20. As the drain electrode 30 of the N-type metal oxide semiconductor field effect transistor is electrically connected with the output end, the more the contact holes 40 of the drain electrode 30 are, the larger the electric connection area with the bonding pad of an external device is, thereby better preventing the N-type metal oxide semiconductor field effect transistor from being damaged by electrostatic discharge and ensuring the better pressure resistance of the N-type metal oxide semiconductor field effect transistor.

In an embodiment not shown, the transistor 100 is a P-type metal oxide semiconductor field effect transistor, and the total area of the source 20 is greater than the total area of the drain 30. That is, the sum of the areas of all the source electrodes 20 is greater than the sum of the areas of all the drain electrodes 30. Since the source electrode 20 of the pmos fet is electrically connected to the output terminal, and thus the total area of the source electrode 20 is larger than that of the drain electrode 30, the area of the source electrode 20 is larger under the condition that the pmos fet has a smaller area, so that the source electrode 20 is better electrically connected to the output terminal.

In an embodiment, not shown, the number of the contact holes 40 in the at least one source electrode 20 is plural, and the plural contact holes 40 in the source electrode 20 are distributed along the first direction and the second direction. That is, the source electrode 20 and/or the source electrodes 20 have a plurality of contact holes 40 therein, and the plurality of contact holes 40 of the source electrode 20 are distributed in a two-dimensional matrix along the first direction and the second direction, so that more contact holes 40 can be provided in the source electrode 20 to better electrically connect the source electrode 20 with the metal layer.

In an embodiment not shown, the total number of contact holes 40 in the source electrode 20 is greater than the total number of contact holes 40 in the drain electrode 30. I.e. the sum of the number of contact holes 40 in all source electrodes 20 is larger than the sum of the number of contact holes 40 in all drain electrodes 30. Because the source electrode 20 of the P-type metal oxide semiconductor field effect transistor is electrically connected with the output end, the more the contact holes 40 of the source electrode 20 are, the larger the electric connection area with the bonding pad of an external device is, thereby better preventing electrostatic discharge from damaging the P-type metal oxide semiconductor field effect transistor and ensuring that the pressure resistance of the P-type metal oxide semiconductor field effect transistor is better.

In an embodiment, referring to fig. 6, the minimum pitch between two adjacent contact holes 40 is a, the minimum width of the contact holes 40 is B, the minimum pitch between the contact holes 40 and the mesh gate 20 is C, the pitch between two adjacent first portions 11 is L, and the number of the contact holes 40 distributed along the first direction in one partition region is N, where L is C2 + N B + (N-1) a. That is, the distance between two adjacent first portions 11 is set according to the minimum distance in accordance with the layout design rule, so that the area of the transistor 100 can be reduced as much as possible in accordance with the layout design rule.

In an embodiment, referring to fig. 6, the distance between two adjacent second portions 12 is H, and the number of the contact holes 40 distributed along the second direction in one partition region is S, where H ═ C × 2+ S × B + (S-1) × a. That is, the distance between two adjacent second portions 12 is set according to the minimum distance in accordance with the layout design rule, so that the transistor 100 can be minimized in accordance with the layout design rule.

In an embodiment, referring to fig. 3 to 6, the total number of the first portions 11 is not equal to the total number of the second portions 12. I.e. the sum of the number of all first portions 11 is not equal to the sum of the number of all second portions 12. In this way, the arrangement of the first and second portions 11, 12 is made more flexible.

In another not shown embodiment, the total number of first portions 11 is equal to the total number of second portions 12. I.e. the sum of the number of all first portions 11 is equal to the sum of the number of all second portions 12. In this manner, the area of the transistor 100 can be further reduced.

The embodiment of the present application further provides an integrated circuit, which includes the transistor 100 in any one of the above embodiments. Because the transistor provided by the embodiment of the application has smaller area, the excessive area of the integrated circuit can be avoided, so that the integrated circuit layout is more compact, the integration level is higher, and the area occupied by the integrated circuit is smaller.

A plurality of transistors 100 provided in the embodiments of the present application may be disposed on the same substrate, and the plurality of transistors 100 are connected in parallel, so that a larger output current may be further driven. Shallow Trench Isolation (STI) or Local Oxidation of silicon (LOCOS) Isolation may be disposed around each transistor 100, so as to avoid the problems of leakage and latch-up between the transistors 100.

In the embodiments of the present application, to further clarify that the transistor 100 adopting the embodiments of the present application has a smaller area, in the following exemplary description, it can be understood by those skilled in the art that, under different process conditions, the minimum distance a between adjacent contact holes 40, the minimum width B of the contact holes 40, and the minimum distance C between the contact holes 40 and the mesh gate 10 are different values; under the same process conditions, the minimum distance a between the adjacent contact holes 40, the minimum width B of the contact holes 40, and the minimum distance C between the contact holes 40 and the mesh gate 10 are the same. The minimum pitch a between the adjacent contact holes 40, the minimum width B of the contact holes 40, and the minimum pitch C between the contact holes 40 and the mesh gate 10, which are listed in the embodiments of the present application, are merely examples, and do not limit the transistor 100 provided in the embodiments of the present application, and each embodiment will be specifically described below.

Illustratively, taking the nmos fet 1001 in the first embodiment of the prior art as an example, it is assumed that, according to the requirements of the process conditions, the minimum pitch between two adjacent contact holes 104 is 0.26 μm, the minimum width of the contact hole 104 is 0.24 μm, and the minimum pitch between the contact hole 104 and the strip gate 101 is 0.8. It is understood that, since the first embodiment of the prior art, the second embodiment of the prior art, the first embodiment of the present application, and the second embodiment of the present application use the same process, the minimum pitch between two adjacent contact holes, the minimum width of the contact holes, and the minimum pitch between the contact holes and the bar gate or the mesh gate in the above embodiments are all the same.