阅读说明：本技术 一种薄膜晶体管结构及制作方法 (Thin film transistor structure and manufacturing method ) 是由 陈宇怀 于 2020-05-12 设计创作，主要内容包括：本发明公开了一种薄膜晶体管结构,包括基板和所述基板上的第一金属层、有源层、第二金属层；所述有源层包括:侧壁有源层,所述第一金属层为柱形结构,第一金属层的底面与基板上表面平行,所述侧壁有源层环绕所述第一金属层的侧面,所述侧壁有源层的侧面与第一金属层的侧面之间形成有源层电通道,且通道内还设有绝缘层；侧壁有源层的顶部两端分别连接有一第二金属层。有效利用第一金属层侧表面与有源层形成有源层导电通道,提高TFT器件反应速率与开态电流,有利于在超高分辨率面板中的应用。并且提供的TFT结构,在器件受到拉伸以及弯折时形变量更小,且可以更好的分散形变产生的应力,使器件保持为稳定,利于未来制造可弯折或可拉伸面板。(The invention discloses a thin film transistor structure, which comprises a substrate, and a first metal layer, an active layer and a second metal layer which are arranged on the substrate; the active layer comprises a side wall active layer, a first metal layer and a second metal layer, wherein the first metal layer is of a cylindrical structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the side wall active layer surrounds the side surface of the first metal layer, an active layer electric channel is formed between the side surface of the side wall active layer and the side surface of the first metal layer, and an insulating layer is further arranged in the channel; two ends of the top of the side wall active layer are respectively connected with a second metal layer. The side surface of the first metal layer and the active layer are effectively utilized to form an active layer conduction channel, so that the reaction rate and the on-state current of the TFT device are improved, and the application in the ultra-high resolution panel is facilitated. And the provided TFT structure has smaller deformation when the device is stretched and bent, and can better disperse the stress generated by deformation, so that the device is kept stable, and the bendable or stretchable panel can be manufactured in the future.)

1. A thin film transistor structure is characterized by comprising a substrate, and a first metal layer, an active layer and a second metal layer which are arranged on the substrate;

the active layer comprises a side wall active layer, a first metal layer and a second metal layer, wherein the first metal layer is of a cylindrical structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the side wall active layer surrounds the side surface of the first metal layer, an active layer electric channel is formed between the side surface of the side wall active layer and the side surface of the first metal layer, and an insulating layer is further arranged in the channel; two ends of the top of the side wall active layer are respectively connected with a second metal layer.

2. The thin film transistor structure of claim 1, further comprising: the buffer layer is arranged on the substrate, and the side wall active layer and the insulating layer are arranged on the buffer layer.

3. The thin film transistor structure of claim 2, wherein the active layer further comprises a bottom active layer disposed on the buffer layer, the bottom active layer being parallel to the upper surface of the substrate, and an insulating layer disposed between the bottom active layer and the first metal layer; the upper surface of the bottom active layer is connected with the bottom of the side wall active layer.

4. The thin film transistor structure of claim 1, further comprising: and the passivation layer is arranged on the top layer of the thin film transistor structure and used for protecting the TFT structure.

5. The thin film transistor structure of claim 1 or 3, further comprising: a third metal layer; the third metal layer is of a cylindrical structure with an opening at the top and a hollow interior, and is sleeved on the periphery of the active layer; the bottom of the third metal layer is connected with the substrate, and an insulating layer is arranged between the third metal layer and the active layer.

6. The thin film transistor structure of claim 1, wherein the first metal layer is a plurality of metal layers; or the first metal layer is in a cylindrical, curved surface cylindrical or square cylindrical structure; or the top of the first metal layer protrudes out of the upper surface of the second metal layer.

7. A method for manufacturing a thin film transistor structure is characterized by comprising the following steps:

manufacturing a first insulating layer, manufacturing a first through hole and manufacturing a side wall active layer;

manufacturing a second metal layer on the top of the side wall active layer, wherein the two ends of the top of the side wall active layer are respectively connected with the second metal layer;

and depositing a first metal layer by a second insulating layer and a second through hole in the middle of the second insulating layer, so that the side wall active layer surrounds the side surface of the first metal layer.

8. The method as claimed in claim 7, wherein the step of forming the first insulating layer, forming the first via, and forming the sidewall active layer comprises the steps of:

depositing a first insulating layer, and etching a first through hole on the first insulating layer;

depositing a sidewall active layer in the first via.

9. The method as claimed in claim 7, wherein the step of depositing the first metal layer through the second insulating layer and the second via hole comprises the steps of:

and etching the first insulating layer and the second insulating layer to prepare a second through hole, and depositing a first metal layer in the second through hole.

10. The method as claimed in claim 9, further comprising, before the step of forming the first via hole by forming the first insulating layer, the steps of: and manufacturing a buffer layer on the substrate, and manufacturing a bottom active layer on the buffer layer.

Technical Field

The invention relates to the field of TFT (thin film transistor) device manufacturing, in particular to a thin film transistor structure and a manufacturing method thereof.

Background

In recent years, manufacturers have been distributing 8K display panels and VR glasses mounted with ultra-high resolution displays. From the market reaction, the 4K resolution, the curved screen and the ultra-wide ratio become the key points of attention of consumers, and the display will continue to develop towards high resolution, curved and ultra-wide ratio in the future. For television, or VR, one important factor in determining the experience is ppd (pixel per degree), which is the number of pixels that can be perceived per view angle. For a person with standard vision of 1.0, the optimal PPD is 60 to be completely free of screen graininess. To improve the immersive experience of VR applications, the resolution must reach 8K or more to improve the "screen effect" commonly existing in VR heads, and the screen effect is even further improved to 12K and 24K in the future. Therefore, as the resolution of the panel is increased, the size of the pixels and the TFT devices behind the pixels are reduced.

Disclosure of Invention

Therefore, it is desirable to provide a thin film transistor structure and a method for fabricating the same to reduce the size of the TFT device behind the pixel.

To achieve the above object, the inventors provide a thin film transistor structure comprising a substrate and a first metal layer, an active layer, a second metal layer on the substrate;

the active layer comprises a side wall active layer, a first metal layer and a second metal layer, wherein the first metal layer is of a cylindrical structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the side wall active layer surrounds the side surface of the first metal layer, an active layer electric channel is formed between the side surface of the side wall active layer and the side surface of the first metal layer, and an insulating layer is further arranged in the channel; two ends of the top of the side wall active layer are respectively connected with a second metal layer.

Further, still include: the buffer layer is arranged on the substrate, and the side wall active layer and the insulating layer are arranged on the buffer layer.

The active layer also comprises a bottom active layer, a first metal layer and a second metal layer, wherein the bottom active layer is arranged on the buffer layer and is parallel to the upper surface of the substrate; the upper surface of the bottom active layer is connected with the bottom of the side wall active layer.

Further, still include: and the passivation layer is arranged on the top layer of the thin film transistor structure and used for protecting the TFT structure.

Further, still include: a third metal layer; the third metal layer is of a cylindrical structure with an opening at the top and a hollow interior, and is sleeved on the periphery of the active layer; the bottom of the third metal layer is connected with the substrate, and an insulating layer is arranged between the third metal layer and the active layer.

Further, the number of the first metal layers is multiple; or the first metal layer is in a cylindrical, curved surface cylindrical or square cylindrical structure; or the top of the first metal layer protrudes out of the upper surface of the second metal layer.

The inventor provides a manufacturing method of a thin film transistor structure, which comprises the following steps:

manufacturing a first insulating layer, manufacturing a first through hole and manufacturing a side wall active layer;

manufacturing a second metal layer on the top of the side wall active layer, wherein the two ends of the top of the side wall active layer are respectively connected with the second metal layer;

and depositing a first metal layer by a second insulating layer and a second through hole in the middle of the second insulating layer, so that the side wall active layer surrounds the side surface of the first metal layer.

Further, the step of manufacturing the first insulating layer, the first through hole and the sidewall active layer includes:

depositing a first insulating layer, and etching a first through hole on the first insulating layer;

depositing a sidewall active layer in the first via.

Further, the step of "second insulating layer, middle second via, depositing first metal layer" comprises:

and etching the first insulating layer and the second insulating layer to prepare a second through hole, and depositing a first metal layer in the second through hole.

Further, before the step of "making the first insulating layer and making the first through hole", the method further comprises the steps of: and manufacturing a buffer layer on the substrate, and manufacturing a bottom active layer on the buffer layer.

The above technical solution provides a thin film transistor structure, and in the present invention, a first metal layer having a pillar structure and an active layer surrounding the first metal layer are provided. The side surface of the first metal layer and the active layer are effectively utilized to form an active layer conduction channel, so that the reaction rate and the on-state current of the TFT device are improved, the size of the TFT is reduced, and the application in an ultrahigh-resolution panel is facilitated. And the provided TFT structure has smaller deformation when the device is stretched and bent, and can better disperse the stress generated by deformation, so that the device is kept stable, and the bendable or stretchable panel can be manufactured in the future.

Drawings

FIG. 1 illustrates a TFT structure according to an embodiment;

FIG. 2 is a prior art TFT structure;

FIG. 3 is an active layer conductive via;

FIG. 4 is a stress comparison graph of a TFT structure

FIG. 5 is a top view of a TFT structure;

FIG. 6 is a cross-sectional view of a TFT structure;

FIG. 7 is a diagram of a plurality of first metal layer structures;

FIG. 8 is a diagram illustrating the structure of the bottom active layer in one embodiment;

FIG. 9 is a diagram illustrating a first metal layer structure according to one embodiment;

FIG. 10 is a diagram illustrating a structure of an insulating layer according to an embodiment;

FIG. 11 is a diagram illustrating the structure of the sidewall active layer according to one embodiment;

FIG. 12 is a diagram illustrating a second metal layer structure according to an embodiment;

FIG. 13 is a diagram illustrating a passivation layer structure according to an embodiment;

FIG. 14 is a diagram illustrating a structure of fabricating a first metal layer and an insulating layer according to a second embodiment;

FIG. 15 is a diagram illustrating the structure of the sidewall active layer and the second metal layer according to the second embodiment;

FIG. 16 is a diagram illustrating the structure of the passivation layer according to the second embodiment;

FIG. 17 is a diagram of the structure of the buffer layer and the bottom active layer in the third embodiment;

FIG. 18 is a diagram of a third embodiment of fabricating an insulating layer and a sidewall active layer;

FIG. 19 is a diagram illustrating the structure of fabricating a first metal layer and a second metal layer in the third embodiment;

FIG. 20 is a diagram of a third junction of an embodiment;

FIG. 21 is a diagram illustrating the structure of the buffer layer and the bottom active layer in the fourth embodiment;

FIG. 22 is a diagram illustrating a fourth embodiment of fabricating an insulating layer and a sidewall active layer;

FIG. 23 is a diagram illustrating a second metal layer structure according to a fourth embodiment;

FIG. 24 is a diagram illustrating a structure of fabricating a first metal layer and a passivation layer according to the fourth embodiment;

FIG. 25 is a diagram showing a structure of a fourth embodiment;

FIG. 26 is a diagram showing a fifth construction in accordance with the embodiment;

FIG. 27 is a diagram of a structure of fabricating a buffer layer and a bottom active layer in accordance with the sixth embodiment;

FIG. 28 is a diagram illustrating a structure of a sixth embodiment in which a first metal layer is formed;

FIG. 29 is a diagram showing a structure of a sixth embodiment of fabricating a sidewall active layer;

FIG. 30 is a diagram illustrating a second metal layer structure according to a sixth embodiment;

FIG. 31 is a sixth structural view of the embodiment;

FIG. 32 is a diagram illustrating a structure of a buffer layer removal according to an embodiment;

FIG. 33 is a diagram showing a seventh construction of the embodiment;

FIG. 34 is a view showing an eighth construction of the embodiment;

description of reference numerals:

1. a first metal layer; 2. a second metal layer; 3. a third metal layer; 4. an active layer; 5. a substrate; 6. a buffer layer;

41. a bottom active layer; 42. a sidewall active layer.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 34, the present embodiment provides a method for fabricating a thin film transistor structure, which can be fabricated on a substrate, a wafer or a chip. The eight embodiments can more effectively utilize the side surface and the bottom surface of the grid electrode to form the active layer 4 conductive channel, improve the response rate and the on-state current of the TFT device, reduce the size of the TFT and facilitate the application in the ultra-high resolution panel. And the provided TFT structure has smaller deformation when the device is stretched and bent, and can better disperse the stress generated by deformation, so that the device is kept stable, and the bendable or stretchable panel can be manufactured in the future.

Referring to fig. 8 to 13, one embodiment includes the following steps: manufacturing a buffer layer on a substrate; specifically, the buffer layer is formed on the substrate, and the material may be an inorganic oxide or an insulating compound, such as silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide, aluminum oxide, or the like, and may be a single-layer coating or a multi-layer coating, or other organic insulating material as the buffer layer. Of course, the buffer layer may not be formed in some embodiments.

After the buffer layer is manufactured, manufacturing a bottom active layer 41 on the buffer layer, wherein the bottom active layer 41 is used as a part of the active layer 4; specifically, the buffer layer is coated with an active layer 4 material, such as polysilicon, an oxide semiconductor, graphene, carbon nanotubes, an organic semiconductor, and the like. Among them, the oxide semiconductor may be an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (A1), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In) and zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), indium aluminum oxide (In-Al-O), indium zinc aluminum oxide (In-Zn-A1-O), Indium tin aluminum oxide (In-Sn-Al-O), indium aluminum gallium oxide (In-Al-Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O) and hafnium zinc oxide (Hf-In-Zn-O), the organic semiconductor may be any one of pentacene (pentacene), Polythianol (Poly (3-alkyl) thiophene), phthalocyanine compound (phthalocyamine compound), and the like. Or the buffer layer may not be made.

In some embodiments, the bottom active layer 41 may be replaced with a conductive material as a conductive layer, and the conductive film may be an oxide conductive film, such as ITO, or one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and other metals with excellent conductivity, carbon nanotube, graphene, and the like.

In the first embodiment, the conductivity or semiconductivity is improved wholly or locally. The surface of the bottom active layer 41 or the edge surface of the bottom active layer 41 may be treated with a gas such as H2, O2, NO2, CH4, or the like.

Then, a first insulating layer is formed on the bottom active layer 41; a first insulating layer is deposited, which may be a single layer or multiple layers of inorganic oxide or compound with insulating properties, such as SiOx, SiNx, titanium oxide, aluminum oxide, etc., and covers the bottom active layer 41. The insulating layer includes a plurality of insulating layers, which may also be regarded as a single layer, and specifically, in the TFT structure, the insulating layer has a single-layer structure; in the method for manufacturing a TFT structure, since the insulating layer functions to mold a metal, it is necessary to sequentially manufacture a plurality of insulating layers.

After the first insulating layer is manufactured, manufacturing a first metal layer 1 on the first insulating layer on the bottom active layer 41; the first metal layer 1 is plated with one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and other metals with excellent conductivity, and alloys, and the first metal layer 1 is formed on the first insulating layer on the bottom active layer 41. The width of the first metal layer 1 is smaller than the width of the bottom active layer 41. In the present application, the first metal layer 1, which serves as a gate of the TFT, may be a cylindrical shape, a curved pillar shape, a square pillar shape, and any other geometric pillar shape. Compared with the traditional flat shape, the first metal layer 1 with the columnar structure can more effectively utilize the side surface and the bottom surface of the grid electrode to form an active layer conductive channel, improve the response rate and the on-state current of a TFT (thin film transistor) device, reduce the size of the TFT and be beneficial to application in an ultrahigh-resolution panel.

After the first metal layer 1 is manufactured, manufacturing a second insulating layer on the first insulating layer and the first metal layer 1; and plating a second insulating layer material, wherein the material can be inorganic oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide, aluminum oxide and the like, and performing single-layer plating or multi-layer plating. Then, through holes penetrating through the second insulating layer and the first insulating layer are etched in the bottom active layer 41 on two sides of the first metal layer 1, and the upper surfaces of the bottom active layer 41 on two sides of the first metal layer 1 are exposed, and the through holes are used for manufacturing a side wall active layer 42 of the active layer.

Then, a sidewall active layer 42 is formed on the second insulating layer, the material selection range of the sidewall active layer 42 is the same as that of the bottom active layer 41, and the materials of the bottom active layer 41 and the sidewall active layer 42 can be freely matched, but not limited to the same material. The sidewall active layer 42 is connected to the bottom active layer 41 through a via hole in the second insulating layer, the sidewall active layer 42 surrounds the first metal layer 1, and the sidewall active layer 42 and the first metal layer 1 form an active layer electrical channel. The sidewall active layer 42 also has a face on top of the second insulating layer, and the sidewall active layer 42 and the bottom active layer 41 together function as an active layer of the TFT. Among them, in order to make the active layer more favorably fill the third insulating layer via hole, the sidewall active layer 42 may be preferably formed by a solution method.

Similarly, a gas treatment such as H2, O2, NO2, CH4, or the like may be performed on the upper surface of the sidewall active layer 42 or the edge surface of the sidewall active layer 42 to improve the overall or local conductivity or semiconductivity.

After the sidewall active layer 42 is formed, the second metal layer 2 having a pillar shape is formed on the sidewall active layer 42 and the second insulating layer. Plating a second metal layer 2 material, wherein the second metal layer 2 material can be one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity, and alloys. A second metal layer 2 is then formed on the sidewall active layer 42 and the second insulating layer. The second metal layer 2 includes a source electrode connected to the sidewall active layer 42 of one side of the first metal layer 1 and a drain electrode connected to the sidewall active layer 42 of the other side of the first metal layer 1.

Finally, a passivation layer can be manufactured on the second metal layer 2; specifically, a passivation layer material is plated, and a single-layer plating film or a multi-layer plating film is performed on the passivation layer material by using an inorganic oxide or an insulating compound, such as SiOx, SiNx, titanium oxide, aluminum oxide, or the like, or another organic insulating material, so as to form a passivation layer covering the second metal layer 2 and the second metal layer 2. The passivation layer is arranged on the top layer of the thin film transistor structure and used for protecting the TFT structure.

Referring to fig. 7, in a further embodiment, the first metal layers 1 are arranged in an array, and then active layers (bottom active layer 41 and sidewall active layer 42) surround between the first metal layers 1, the active layers are connected to the second metal layers (source and drain) at two ends.

Referring to fig. 14 to 16, in the second embodiment, based on the first embodiment, a partial process improvement is performed, which includes the following steps: the first metal layer 1 is directly formed on the substrate (without forming the buffer layer and the bottom active layer 41 of the first embodiment), in the same manner as the first embodiment. After the first metal layer 1 is manufactured, a first insulating layer covering the first metal layer 1 is manufactured on the first metal layer 1, and through holes are etched in the first insulating layer on two sides of the first metal layer 1, wherein the bottoms of the through holes can be the substrate or the positions of the first insulating layer close to the substrate. Then, a sidewall active layer 42 is formed in the via hole on the first insulating layer, and then a second metal layer 2 (source and drain) is formed on the sidewall active layer 42, wherein the material, structure and distribution of the sidewall active layer 42 and the second metal layer 2 are the same as those of the first embodiment. And finally, manufacturing a passivation layer on the TFT, wherein the passivation layer can protect the TFT. The second embodiment can save two insulating layers and a bottom active layer 41 compared to the first embodiment.

Referring to fig. 17 to 20, in the third embodiment, based on the first embodiment, a partial process improvement is performed, which includes the following steps: similarly, a buffer layer is formed on the substrate in the same manner as in the first embodiment. Next, a bottom active layer 41 is formed on the buffer layer in the same manner as in the first embodiment. Then, a first insulating layer is formed on the bottom active layer 41 in the same manner as the first embodiment. The difference is that a hole for placing the first metal layer 1 and the sidewall active layer 42 is simultaneously formed on the first insulating layer. The first insulating layer is exposed through the gray-scale photomask, and the etching time is controlled through the etching rate, so that holes with different depths are manufactured on the first insulating layer. The gray tone mask may be a mask having a light-shielding region, a light-transmitting region and a semi-light-transmitting region, wherein the semi-light-transmitting region corresponds to the third hole (for accommodating the first metal layer 1), and the light-transmitting region or the light-shielding region (depending on the positive photoresist or the negative photoresist) corresponds to the first hole and the second hole. The first hole and the second hole expose the surface of the bottom active layer 41 at the outer sides, the third hole is a blind hole, and no surface of the active layer is exposed between the first hole and the second hole. Likewise, the exposed bottom active layer 41 may be subjected to a gas treatment. Then, a sidewall active layer 42 is formed on the first insulating layer, and the sidewall active layer 42 is connected to the bottom active layer 41 through the first and second holes and is located on the first insulating layer surface. After the sidewall active layer 42 is completed, the fabrication of the first metal layer 1 (gate electrode) having a pillar shape is continued so as to be filled in the third hole on the second insulating layer. Similarly, the second metal layer 2 (source and drain) is formed on the sidewall active layer 42 and the first insulating layer, the source is connected to the sidewall active layer 42 on one side of the first metal layer 1, and the drain is connected to the sidewall active layer 42 on the other side of the first metal layer 1. The materials, structures and connections of the first metal layer 1, the second metal layer 2 and the insulating layer are the same as those of the first embodiment, but one insulating layer is saved compared with the first embodiment.

Referring to fig. 21 to 25, in the fourth embodiment, based on the third embodiment, a partial process improvement is performed; the method comprises the following steps: a buffer layer is fabricated on the substrate, then a bottom active layer 41 is fabricated on the buffer layer, and then a first insulating layer is fabricated on the bottom active layer 41. In the third embodiment, a first hole, a second hole and a third hole are formed in the first insulating layer, in the fourth embodiment, the first hole and the second hole are formed in the first insulating layer, and the bottom of the first hole and the bottom of the second hole are the bottom active layer 41. Then, a sidewall insulating layer is formed on the first insulating layer, and the sidewall insulating layer is connected to the bottom active layer 41 through the first hole and the second hole. Next, a second metal layer 2 (source and drain) is formed on the sidewall insulating layer and the first insulating layer, and a sidewall active layer 42 on each side to which the source and drain are connected is formed. And manufacturing a second insulating layer covering the second metal layer 2 on the second metal layer 2 and the first insulating layer, wherein the second insulating layer is used for forming the shape of the first metal layer 1.

After the second metal layer 2 and the second insulating layer are manufactured, the second insulating layer is etched to the first insulating layer on the second insulating layer in the middle area of the sidewall active layer 42 by controlling the etching time, so as to form a third hole, the third hole is a blind hole, the bottom of the third hole is a part of the first insulating layer close to the bottom active layer 41, and the surface of the active layer is not exposed.

Then, a pillar-shaped first metal layer 1 (gate) is formed in the third hole in the second insulating layer, and the first metal layer 1 is also located on the second insulating layer and surrounded by the outer sidewall active layer 42 and the second metal layer 2. Unlike the previous embodiments, the first metal layer 1 has a height exceeding the second metal layer 2, which facilitates the design layout of the TFT in the panel.

Referring to fig. 26, based on the fourth embodiment, in order to save the process cost and steps, in the fifth embodiment, without fabricating the buffer layer and the bottom active layer 41 in the fourth embodiment, a first insulating layer is fabricated on the substrate, and a first hole and a second hole are etched, and then a sidewall active layer 42, a second metal layer 2, a second insulating layer (fabricating a third hole), a first metal layer 1 and a passivation layer are sequentially fabricated. An insulating layer and a bottom active layer 41 can be saved.

Referring to fig. 27 to 31, in the sixth embodiment, based on the first embodiment, a partial process improvement is performed, which includes the following steps: the buffer layer is fabricated on the substrate in the same manner as in the first embodiment. After the buffer layer is manufactured, the bottom active layer 41 is manufactured on the buffer layer, in the same manner as in the first embodiment. Then, a first insulating layer covering the bottom active layer 41 is formed on the buffer layer and the bottom active layer 41, in the same manner as in the first embodiment. Next, a pillar-shaped first metal layer 1 is formed on the first insulating layer in the bottom active layer 41 region, in the same manner as in the first embodiment. After the first metal layer 1 is manufactured, a second insulating layer covering the first metal layer 1 is manufactured on the first metal layer 1 and the first insulating layer. Then, a via hole is formed in the second insulating layer on both sides of the first metal layer 1, and the bottom of the via hole is a bottom active layer 41. At this time, a gas treatment, such as H2, O2, NO2, CH4, SiH4, or the like, may be performed on the surface of the second insulating layer after the via hole is fabricated, so as to improve the via hole surface contact characteristics. Example six compared to embodiments one and four, the insulating layer is thinner and requires a lower depth of the hole.

Then, a sidewall active layer 42 is formed on the second insulating layer, the sidewall active layer 42 is connected to the bottom active layer 41 through the second insulating layer via holes on both sides of the first metal layer 1, two portions of the sidewall active layer 42 are closely attached to the second insulating layer covering the first metal layer 1, and the sidewall active layer 42 has a portion on the second insulating layer covering the first metal layer 1.

After the sidewall active layer 42 is formed, a third insulating layer is formed on the second insulating layer and the sidewall active layer 42, and then two through holes communicating with the sidewall active layer 42 are formed on the third insulating layer on the sidewall active layer 42. And then, a second metal layer 2 (a source electrode and a drain electrode) is manufactured on the third insulating layer, the source electrode is connected with the side wall active layer 42 on one side of the first metal layer 1 through a through hole on one third insulating layer, and the drain electrode is connected with the side wall active layer 42 on the other side of the first metal layer 1 through a through hole on the other third insulating layer. It is of course possible to leave the portion of the second metal layer 2 on the third insulation level outside the via as a connection point for external circuitry. And finally, manufacturing a passivation layer with a protection effect on the second metal layer 2 and the third insulating layer. In the sixth embodiment, the contact surface between the TFT structure and the second insulating layer is not affected by etching gas when most regions are used for forming the through holes, so that the contact surface is smoother, which is beneficial to electrical debugging of the TFT.