阅读说明：本技术 用于在存储器系统中传输映射信息的装置和方法 (Apparatus and method for transferring mapping information in memory system ) 是由 边谕俊 于 2019-12-09 设计创作，主要内容包括：本公开的实施例涉及一种用于在存储器系统中传输映射信息的装置和方法。存储器系统包括：存储器设备,其包括非易失性存储器单元；以及控制器,其被配置为生成映射信息,该映射信息用于将从主机输入的逻辑地址转换为指示数据存储在存储器设备中的位置的物理地址。控制器被配置为：向主机传输映射信息中的至少一些映射信息,存储关于传输到主机的映射信息中的至少一些映射信息的日志,并在初始操作期间,基于日志向主机再次传输映射信息中的至少一些映射信息。(Embodiments of the present disclosure relate to an apparatus and method for transmitting mapping information in a memory system. The memory system includes: a memory device including a non-volatile memory cell; and a controller configured to generate mapping information for converting a logical address input from the host into a physical address indicating a location where data is stored in the memory device. The controller is configured to: the method includes transmitting at least some of the mapping information to the hosts, storing logs regarding the at least some of the mapping information transmitted to the hosts, and, during an initial operation, retransmitting at least some of the mapping information to the hosts again based on the logs.)

1. A memory system, comprising:

a memory device including a non-volatile memory cell; and

a controller configured to generate mapping information for converting a logical address input from a host into a physical address indicating a location of data stored in the memory device,

wherein the controller is configured to:

transmitting at least some of the mapping information to the host;

storing a log of the at least some of the mapping information transmitted to the host; and

during an initial operation, re-transmitting the at least some of the mapping information to the host based on the log.

2. The memory system of claim 1, wherein the controller is configured to: transmitting the at least some of the mapping information in response to a request received from the host.

3. The memory system of claim 1, wherein the controller is configured to send a query for transmitting the at least some of the mapping information to the host, and is configured to transmit the at least some of the mapping information based on a determination made by the host regarding the query.

4. The memory system of claim 1, wherein the controller is configured to:

performing an operation corresponding to a command input from the host;

inserting the at least some of the mapping information into a response to the command; and

communicating the response to the host including the inserted at least some of the mapping information.

5. The memory system of claim 1, wherein the controller is configured to:

determining that a command input from the host includes a logical address and a physical address;

determining whether the physical address entered with the command is valid;

determining whether to use the physical address based on the validity of the physical address; and

performing an operation corresponding to the command using the physical address.

6. The memory system of claim 5, wherein the controller is configured to: when the physical address is invalid, ignoring the physical address, and searching for a valid physical address corresponding to the logical address from the mapping information stored in the memory device before executing the command.

7. The memory system of claim 1, wherein the controller is configured to: determining an amount of the mapping information included in the log based on a size of the mapping information that can be transmitted to the host.

8. The memory system of claim 1, wherein during the initial operation, the controller is configured to: executing the firmware; loading a boot image; relinquishing control authority and handing over the control authority to the host; and transferring the at least some of the mapping information after handing over the control grant to the host.

9. The memory system of claim 1, wherein the log is stored prior to the memory system being powered down and the initial operation is performed directly after power to the memory system is restored.

10. A method for operating a memory system, comprising:

generating mapping information for converting a logical address input from a host into a physical address indicating a location of data stored in a memory device of the memory system;

transmitting at least some of the mapping information to the host;

storing a log about the at least some of the mapping information; and

during initial operation, re-transmitting the at least some of the mapping information to the host based on the log or history.

11. The method of claim 10, further comprising:

receiving a command from the host regarding the at least some of the mapping information prior to transmitting the at least some of the mapping information to the host.

12. The method of claim 10, further comprising:

sending a query for transmitting the at least some of the mapping information to the host,

wherein the at least some of the mapping information is transmitted to the host based on a determination made by the host regarding the query.

13. The method of claim 10, further comprising:

performing an operation corresponding to a command input from the host; and

inserting the at least some of the mapping information into a response to the command,

wherein the at least some of the mapping information inserted is transmitted to the host with the response.

14. The method of claim 10, further comprising:

determining that a command input from the host includes a logical address and a physical address;

determining whether the physical address entered with the command is valid;

determining a use case of the physical address based on the validity of the physical address; and

performing an operation corresponding to the command using the physical address.

15. The method of claim 14, further comprising:

when the physical address is determined to be invalid, ignoring the physical address; and

searching for a valid physical address corresponding to the logical address from the mapping information stored in the memory device before executing the command.

16. The method of claim 10, further comprising:

determining an amount of the mapping information included in the log based on a size of the mapping information that can be transmitted to the host.

17. The method of claim 10, further comprising:

during the initial operation, executing firmware;

loading a boot image; and

relinquishing control authority, and handing over the control authority to the host,

wherein transmitting the at least some of the mapping information is communicated after the control grant is handed over.

18. A data processing system comprising:

a host configured to perform at least one of: generating, changing or updating a logical address corresponding to a plurality of data; and

a memory system configured to:

storing the plurality of data at locations identified by physical addresses distinguishable from the logical addresses;

transmitting to the host at least some mapping information for translating the logical address to the physical address;

storing a log of the at least some mapping information; and

during initial operation, re-transmitting the at least some mapping information to the host based on the log.

19. The data processing system of claim 18, wherein the memory system is configured to:

determining that a command input from the host includes a logical address and a physical address;

determining whether the physical address included in the command is valid;

determining whether to use the physical address based on the validity of the physical address; and

performing an operation corresponding to the command using the physical address.

20. The data processing system of claim 18, wherein the memory system is configured to: determining an amount of the mapping information included in the log based on a size of the mapping information that can be transmitted to the host.

Technical Field

Various embodiments relate to memory systems, and more particularly, to methods and apparatus for transmitting mapping information to a host or computing device.

Background

Recently, the paradigm for computing environments has shifted to ubiquitous computing, which allows computer systems to be accessed almost anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like is rapidly increasing. Such portable electronic devices typically use or include a memory system that uses or embeds at least one memory device (i.e., a data storage device). The data storage device may be used as a primary or secondary storage device for the portable electronic device.

Unlike a hard disk, a data storage device using a nonvolatile semiconductor memory device has advantages in that: it has excellent stability and durability because it does not have a mechanical driving part (e.g., a robot arm), and has high data access speed and low power consumption. In the context of memory systems having such advantages, exemplary data storage devices include USB (universal serial bus) memory devices, memory cards with various interfaces, Solid State Drives (SSDs), and the like.

Disclosure of Invention

One embodiment of the present disclosure may provide a data processing system and method for operating a data processing system that includes components and resources, such as a memory system and a host, and is capable of dynamically allocating a plurality of data paths for data communication between the components based on usage of the components and resources.

Additionally, one embodiment of the present disclosure may provide methods and apparatus for improving or enhancing the operation or performance of a memory system. When power is restored after power is not supplied to the memory system and the host (or computing device) of the data processing system, the memory system may transmit mapping information to the host (or computing device) based on the record, log, and/or history. As used herein, the word "log" is extended to include the records and/or history indicated above. The host (or computing device) may transmit a command to the memory system based on the mapping information. The memory system can reduce the time spent on address translation due to information input along with a command transmitted from the host to the memory system.

Additionally, one embodiment of the present disclosure may provide a method or apparatus that enables a host (or computing device) or a computing device to transmit a command that includes a physical location of data to be read within a memory system even after power is supplied or restored in a data processing system that includes the host and the memory system. A method or apparatus for transferring mapping information based on a record, log, or history may more quickly satisfy a user's request.

In one embodiment, a memory system may include: a memory device including a non-volatile memory cell; and a controller configured to generate mapping information for converting a logical address input from the host into a physical address indicating a location of data stored in the memory device. The controller may be configured to: transmitting at least some of the mapping information to the host; storing a log or history regarding at least some of the mapping information; and transmitting at least some of the mapping information to the host during an initial operation based on the log or the history.

By way of example, and not limitation, the controller may be configured to: at least some of the mapping information is transmitted in response to a request by the host.

The controller may be configured to: the method further includes sending a query for transmitting at least some of the mapping information to the host, and transmitting at least some of the mapping information based on a determination by the host regarding the query.

The controller may be configured to: the method includes performing an operation corresponding to a command input from a host, inserting at least some of mapping information into a response regarding the command, and delivering the response including the at least some of the mapping information.

The controller may be configured to: checking whether a command input from a host includes a logical address and a physical address; determining whether a physical address input with the command is valid; determining whether to use the physical address based on the validity of the physical address; and executing the operation corresponding to the command according to the use condition of the physical address.

The controller may be configured to: the physical address is ignored when the physical address is invalid, and a valid physical address corresponding to the logical address is searched from mapping information stored in the memory device before executing the command.

The controller may be configured to: the amount of mapping information included in the log or history is determined in response to the size of the mapping information that can be transmitted to the host.

In an initial operation, the controller may be configured to: the method includes executing firmware, loading a boot image (boot image), relinquishing and handing over control authority to the host, and passing at least some of the mapping information after handing over the control authority.

The log or history may be stored before the power is turned off, and the initial operation may be directly performed after the power is turned on or the power is restored.

In one embodiment, a method for operating a memory system may include: generating mapping information for converting a logical address input from a host into a physical address indicating a location of data stored in a memory device; communicating at least some of the mapping information to the host; storing a log or history about at least some of the mapping information; and during an initial operation, transmitting at least some of the mapping information to the host based on the log or history.

The method may further comprise: receiving a host command regarding at least some of the mapping information prior to transmitting the at least some of the mapping information.

The method may further comprise: a query is sent for transmitting at least some of the mapping information to the host. At least some of the mapping information may be transmitted based on a determination by the host regarding the query.

The method may further comprise: executing an operation corresponding to a command input from a host; and inserting at least some of the mapping information into a response regarding the command. At least some of the mapping information may be transmitted with the response.

The method may further comprise: checking whether a command input from a host includes a logical address and a physical address; determining whether a physical address input with the command is valid; determining a usage of the physical address based on a validity of the physical address; and executing the operation corresponding to the command according to the use condition of the physical address.

The method may further comprise: when the physical address is invalid, ignoring the physical address; and searching for an effective physical address corresponding to the logical address from mapping information stored in the memory device before executing the command.

The method may further comprise: the amount of mapping information included in the log or history is determined in response to the size of the mapping information that can be transmitted to the host.

The method may further comprise: in an initial operation, firmware is executed; loading a boot image; and relinquishes control authorization and hands it over to the host. At least some of the mapping information may be communicated after the handover control grant.

In one embodiment, a data processing system may include: a host configured to generate, change or update a logical address corresponding to data; and a memory system configured to store data at a location identified by a physical address, the physical address being distinguishable from the logical address. The memory system may be configured to: transmitting at least some of mapping information for converting logical addresses to physical addresses; storing a log or history regarding at least some of the mapping information; and transmitting at least some of the mapping information to the host during an initial operation based on the log or history.

The memory system is configured to: checking whether a command input from a host includes a logical address and a physical address; determining whether a physical address input with the command is valid; determining whether to use the physical address based on the validity of the physical address; and executing the operation corresponding to the command according to the use condition of the physical address.

The memory system may be configured to: the amount of mapping information included in the log or history is determined in response to the size of the mapping information that can be transmitted to the host.

Drawings

The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout, and wherein:

FIG. 1 illustrates a method for sharing mapping information between a host and a memory system in a data processing system according to one embodiment of the present disclosure;

FIG. 2 illustrates a data processing system including a memory system according to one embodiment of the present disclosure;

FIG. 3 illustrates a memory system according to one embodiment of the present disclosure;

FIG. 4 illustrates a configuration of a host and a memory system in a data processing system according to one embodiment of the present disclosure;

FIG. 5 illustrates a read operation of a host and a memory system in a data processing system according to one embodiment of the present disclosure;

FIG. 6 illustrates a first example of a transaction between a host and a memory system in a data processing system according to one embodiment of the present disclosure;

FIG. 7 illustrates a first operation of a host and memory system according to one embodiment of the present disclosure;

FIG. 8 illustrates initial operation of a memory system according to one embodiment of the present disclosure;

FIG. 9 illustrates a second example of a transaction between a host and a memory system in a data processing system according to one embodiment of the present disclosure;

FIG. 10 illustrates a second operation of the host and memory system according to one embodiment of the present disclosure;

FIG. 11 illustrates a third operation of the host and memory system according to one embodiment of the present disclosure; and

FIG. 12 illustrates a fourth operation of the host and memory system according to one embodiment of the present disclosure.

Detailed Description

Various embodiments of the present disclosure are described below with reference to the drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments. Accordingly, the present teachings are not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art to which the present teachings pertain. Note that references to "one embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment(s).

It will be understood that, although the terms first, second, third, etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Thus, a first element in one instance may also be termed a second or third element in another instance without departing from the spirit and scope of the present teachings.

The drawings are not necessarily to scale and, in some instances, features of embodiments may have been exaggerated in scale to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it is understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via intervening elements therebetween. Additionally, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise. The articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

It will be further understood that the terms "comprises", "comprising", "includes" and "including", when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all terms used herein including technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. The teachings disclosed herein may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the teachings disclosed herein.

It should also be noted that in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless expressly stated otherwise, as would be apparent to one skilled in the relevant art.

Embodiments of the present disclosure are described with reference to the drawings, wherein like reference numerals refer to like elements throughout.

Referring to FIG. 1, it is described how mapping information is shared between a host and a memory system in a data processing system according to one embodiment of the present disclosure.

Referring to FIG. 1, a host 102 and a memory system 110 may be operatively engaged. Host 102 may include a computing device and may be implemented in the form of a mobile device, computer, server, or the like. The memory system 110, which is operatively engaged with the host 102, may receive commands from the host 102 and store or output data in response to the received commands.

The memory system 110 may have a storage space including non-volatile memory cells. For example, the memory system 110 may be implemented in the form of a flash memory, a Solid State Drive (SSD), or the like.

To store data in a memory space that includes non-volatile memory cells in response to a request by host 102, memory system 110 may perform a mapping operation for associating a file system used by host 102 with the memory space that includes non-volatile memory cells. This may be referred to as address translation between logical and physical addresses. For example, an address identifying data according to a file system used by the host 102 may be referred to as a logical address or a logical block address, and an address indicating a physical location of the data in a storage space including the nonvolatile memory unit may be referred to as a physical address or a physical block address. When the host 102 sends a read command with a logical address to the memory system 110, the memory system 110 may search for a physical address corresponding to the logical address and then read and output data stored in a physical location indicated by the physical address. During these processes, a mapping operation or address translation may be performed while the memory system 110 searches for a physical address corresponding to a logical address input from the host 102. The mapping operation or address translation may be performed based on mapping information, such as a mapping table, which may associate logical addresses with physical addresses.

If the host 102 can perform the mapping operation performed by the memory system 110, the amount of time it takes for the memory system 110 to read and output data corresponding to the read command transmitted by the host 102 may be reduced. The host 102 may store and access at least some of the mapping information used to perform the mapping operation to transfer a read command having a physical address into the memory system 110 via the mapping operation.

Referring to fig. 1, the memory system 110 may transmit mapping information MAP _ INFO to the host 102. The host 102 receiving the mapping information MAP _ INFO transmitted from the memory system 110 may store the mapping information MAP _ INFO in a memory included in the host 102. When the memory system 110 sends the entire mapping information to the host 102, and the host 102 may store the entire mapping information in memory, the memory system 110 may not need to write a log on the transferred mapping information. However, it may be difficult for the host 102 to allocate memory space in memory for storing the entire mapping information generated and transferred by the memory system 110. Thus, when the host has limited storage space for storing mapping information, the memory system 110 may select or select a portion of the mapping information related to data or logical addresses that are frequently used or accessed by the host 102 and transmit the selected or selected mapping information to the host 102.

At the same time, the memory system 110 that transmits at least some of the mapping information to the host 102 may generate a log or history record about the transmitted mapping information. The log or history may have one of various formats, structures, flags, variables, or types, and may be stored in a storage area or memory device that includes non-volatile memory cells. According to one embodiment, each time the memory system 110 transmits mapping information to the host 102, the log or history may include a type of data related to the transmitted mapping information. Further, the memory system 110 may determine an amount of mapping information recorded in a log or history corresponding to a size of the mapping information that may be transmitted to the host 102. For example, it may be assumed that the size of the mapping information that the memory system 110 may transmit to the host 102 is 512 KB. Although the memory system 110 may transmit more than 512KB of mapping information to the host 102 in the log or history, the amount of transmitted mapping information recorded in the log or history may be limited to 512 KB. The amount of mapping information that the memory system 110 may send to the host 102 at one time may be less than the amount of mapping information that the host 102 may store in memory. For example, the mapping information may be transmitted to the host 102 in units of sectors. The memory system 110 may transfer the segments of mapping information to the host 102 several times, and the segments of mapping information may be transferred to the host 102 continuously or intermittently.

According to one embodiment, when the memory system 110 transfers more than 1MB of mapping information to the host 102, the host 102 may delete old mapping information (i.e., mapping information previously transferred from the memory system 110 and stored in memory) according to the timeline. Additionally, the mapping information transmitted from the memory system 110 to the host 102 may include update information. Because the space allocated by the host 102 to store the mapping information transferred from the memory system 110 includes volatile memory cells (supports overwriting), the host 102 can update the mapping information based on the update information without performing an additional operation of erasing another mapping information.

The host 102 may add the physical address PBA to the command transferred to the memory system 110 based on the mapping information. In a mapping operation, the host 102 may search for and find a physical address PBA in mapping information stored in memory based on a logical address corresponding to a command transferred into the memory system 110. When a physical address is present and found, the host 102 may transmit a command having a logical address and a physical address into the memory system 110.

The memory system 110 receiving a command having a logical address and a physical address input from the host 102 may perform a command operation corresponding to the command. As described above, when the host 102 transmits a physical address corresponding to a read command, the memory system 110 may use the physical address to access and output data stored in a location indicated by the physical address using the corresponding physical address. The memory system 110 may perform an operation in response to a read command without performing address translation, so that the memory system 110 may reduce time spent on the operation.

When power is not supplied to the host 102 and the memory system 110, all mapping information stored in the memory including volatile memory cells in the host 102 will be lost or disappear. Powering down or on at the host 102 and the memory system 110 may occur at the request of the user, or regardless of the request of the user, even under undesirable circumstances. Upon supplying power to the host 102 and the memory system 110, the memory system 110 may log or history information regarding the mapping information transmitted to the host 102. Thereafter, upon resuming power after a power outage, the memory system 110 may transmit mapping information to the host 102 based on the log or history, such that the host 102 may perform mapping operations and transmit commands having logical and physical addresses to the memory system 110. After power is restored, the host 102 can quickly restore the operating state associated with the mapping operation, which is substantially the same as the state before power was removed or not.

The demand and usage patterns of a user using a data processing system including host 102 and memory system 110 may be similar or different before power is removed and after power is restored. When the user's needs and usage patterns have not changed, the host 102 may have attempted to access or read the same data at a high frequency. When the host 102 performs a mapping operation with respect to such data and the memory system 110 can output data faster in response to a read command input with a logical address and a physical address, it is likely that the user can be satisfied with the performance of the data processing system including the host 102 and the memory system 110.

Referring to FIG. 2, a data processing system 100 is depicted in accordance with one embodiment of the present disclosure. Referring to FIG. 2, data processing system 100 may include a host 102 interfacing with memory system 110 or operating with memory system 110.

For example, the host 102 may include a portable electronic device such as a mobile phone, an MP3 player, and a laptop computer, or an electronic device such as a desktop computer, a game console, a Television (TV), a projector, and the like.

The host 102 may also include at least one Operating System (OS) that may generally manage and control functions and operations performed in the host 102. the OS may provide interoperability between the host 102 interfacing with the memory system 110 and users that need and use the memory system 110. the OS may support functions and operations corresponding to the user's requests.As an example and not by way of limitation, the OS may be divided into a general-purpose operating system and a Mobile operating system depending on the mobility of the host 102. the general-purpose operating system may be divided into a personal operating system and an enterprise operating system depending on system requirements or user environments.

The memory system 110 may operate or perform particular functions or operations in response to requests from the host 102, and may in particular store data to be accessed by the host 102. The memory system 110 may be used as a primary memory system or a secondary memory system for the host 102. Memory system 110 may be implemented with any of various types of memory devices that may be electrically coupled to host 102, depending on the protocol of the host interface. Non-limiting examples of suitable storage devices include Solid State Drives (SSDs), multimedia cards (MMCs), embedded MMCs (emmcs), small-scale MMCs (RS-MMCs), micro MMCs, Secure Digital (SD) cards, small SD cards, micro SD cards, Universal Serial Bus (USB) storage devices, Universal Flash Storage (UFS) devices, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, and the like.

Storage devices for memory system 110 may be implemented with volatile memory devices (e.g., Dynamic Random Access Memory (DRAM) and static RAM (sram)) and/or non-volatile memory devices (e.g., Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), ferroelectric RAM (fram), phase change RAM (pram), magnetoresistive RAM (mram), resistive RAM (RRAM or ReRAM), and flash memory).

Memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102. The controller 130 may control the storage of data in the memory device 150.

The controller 130 and the memory device 150 may be integrated into a single semiconductor device, which may be included in any of the various types of memory systems as discussed in the examples above.

By way of example and not limitation, controller 130 and memory device 150 may be integrated into a single semiconductor device. The controller 130 and the memory device 150 may be integrated into the SSD to increase the operation speed. When the memory system 110 is used as an SSD, the operation speed of the host 102 connected to the memory system 110 can be increased as compared with the host 102 implemented with a hard disk. Additionally, the controller 130 and the memory device 150 may be integrated into one semiconductor device to form a memory card such as a PC card (PCMCIA), a compact flash Card (CF), a memory card such as a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a general flash memory, or the like.

The memory system 110 may be configured as part of: for example, a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a Web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional (3D) television, a smart television, a digital recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a memory configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a computer, A Radio Frequency Identification (RFID) device or one of various components configuring a computing system.

Memory device 150 may be a non-volatile memory device and may retain data stored therein even if no power is provided, memory device 150 may store data provided from host 102 via a write operation while providing data stored therein to host 102 via a read operation, memory device 150 may include a plurality of memory blocks 152, 154, 156, each of which may include a plurality of pages, each of which may include a plurality of memory cells, to which a plurality of wordlines (W L) are electrically coupled, memory device 150 further includes a plurality of memory dies, each of which includes a plurality of planes, each of which includes a plurality of memory blocks 152, 154, 156, additionally, memory device 150 may be a non-volatile memory device (e.g., a flash memory), wherein the flash memory may be embodied as a three-dimensional stack structure.

The controller 130 may control the overall operation (e.g., read, write, program, and erase operations) of the memory device 150. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide data read from the memory device 150 to the host 102. The controller 130 may also store data provided by the host 102 in the memory device 150.

Controller 130 may include a host interface (I/F)132, a processor 134, an Error Correction Code (ECC) component 138, a Power Management Unit (PMU)140, a memory interface (I/F)142, and a memory 144, all operatively coupled via an internal bus.

The host interface 132 may process commands and data provided by the host 102 and may communicate with the host 102 via at least one of various interface protocols (e.g., Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE)).

The ECC component 138 may correct erroneous bits of data to be processed in the memory device 150 (e.g., output from the memory device 150), and the ECC component 138 may include an ECC encoder and an ECC decoder. Here, the ECC encoder may error correction encode data to be programmed in the memory device 150 to generate encoded data to which parity bits are added and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder may detect and correct errors contained in the data read from the memory device 150. In other words, after performing error correction decoding on the data read from the memory device 150, the ECC component 138 may determine whether the error correction decoding was successful and output an instruction signal (e.g., a correction success signal or a correction failure signal). The ECC component 138 may use the parity bits generated during the ECC encoding process to correct the erroneous bits of the read data. When the number of error bits is greater than or equal to the threshold number of error-correctable bits, the ECC component 138 may not correct the error bits, but may output an error correction failure signal indicating failure in correcting the error bits.

The ECC component 138 may perform error correction operations based on coded modulation such as low density parity check (L DPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), Block Coded Modulation (BCM), and the like.

PMU 140 may manage the power provided in controller 130.

Memory interface 142 may serve as an interface for processing commands and data transferred between controller 130 and memory device 150 to allow controller 130 to control memory device 150 in response to requests communicated from host 102. when memory device 150 is a flash memory and particularly where memory device 150 is a NAND flash memory, memory interface 142 may generate control signals for memory device 150 and may process data input into or output from memory device 150 under the control of processor 134. memory interface 142 may provide an interface for processing commands and data between controller 130 and memory device 150 (e.g., the operation of a NAND flash interface, particularly between controller 130 and memory device 150. according to one embodiment, memory interface 142 may be implemented by way of firmware called a flash interface layer (FI L) as a component for exchanging data with memory device 150.

The memory 144 may support operations performed by the memory system 110 and the controller 130. The memory 144 may store temporary or transactional data that occurs or is transferred for operation in the memory system 110 and the controller 130. In response to a request from the host 102, the controller 130 may control the memory device 150. The controller 130 may transfer data read from the memory device 150 into the host 102. The controller 130 may store data input by way of the host 102 within the memory device 150. Memory 114 may be used to store data for controller 130 and memory device 150 to perform operations such as read operations or program/write operations.

The memory 144 may be implemented as a volatile memory. Memory 144 may be implemented using Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), or both. Although fig. 2 illustrates the second memory 144 disposed within the controller 130, for example, embodiments are not limited thereto. That is, the memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and/or signals between the memory 144 and the controller 130.

The memory 144 may store data necessary to perform the following operations: such as data writes and data reads requested by the host 102 and/or data transfers between the memory device 150 and the controller 130 for background operations such as garbage collection and wear leveling as described above. According to one embodiment, to support operations in memory system 110, memory 144 may include program memory, data memory, write buffers/caches, read buffers/caches, data buffers/caches, map buffers/caches, and so forth.

The processor 134 may be implemented using a microprocessor or Central Processing Unit (CPU). the memory system 110 may include one or more processors 134. the processor 134 may control the overall operation of the memory system 110. by way of example and not limitation, the processor 134 may control program operations or read operations of the memory device 150 in response to write requests or read requests input from the host 102. according to one embodiment, the processor 134 may use or execute firmware to control the overall operation of the memory system 110. herein, the firmware may be referred to as a flash translation layer (FT L). FT L may perform operations as an interface between the host 102 and the memory device 150. the host 102 may transmit requests for write and read operations to the memory device 150 via FT L.

Also, with an address mapping operation based on the mapped data, when the controller 130 attempts to update data stored in a particular page, due to the characteristics of the flash memory device, the controller 130 may program the updated data on another empty page and may invalidate old data of the particular page (e.g., update a physical address corresponding to the logical address of the updated data from a previous particular page to another newly programmed page).

For example, when an operation requested from the host 102 is performed in the memory device 150, the controller 130 uses the processor 134 implemented in a microprocessor or a Central Processing Unit (CPU) or the like. The processor 134, in conjunction with the memory device 150, may process instructions or commands corresponding to commands input from the host 102. The controller 130 may execute a command operation corresponding to a command input from the host 102 (e.g., a program operation corresponding to a write command, a read operation corresponding to a read command, an erase/discard operation corresponding to an erase/discard command, and a parameter setting operation corresponding to a set parameter command or a set feature command with a set command) as a foreground operation.

For another example, the controller 130 may perform background operations on the memory device 150 with the processor 134, as an example and not by way of limitation, background operations for the memory device 150 include operations to copy and store data stored in one of the memory blocks 152, 154, 156 in the memory device 150 to another memory block (e.g., Garbage Collection (GC) operations.) background operations may include operations to move or swap data stored in at least one of the memory blocks 152, 154, 156 to at least another one of the memory blocks 152, 154, 156 (e.g., wear leveling (W L) operations.) during background operations, the controller 130 may use the processor 134 to store mapping data stored in the controller 130 to at least one of the memory blocks 152, 154, 156 in the memory device 150 (e.g., refresh operations.) check or search for failed block management operations for failed blocks in the memory blocks 152, 154, 156 is another example of operations performed by the processor 134.

In the memory system 110, the controller 130 performs a plurality of command operations corresponding to a plurality of commands input from the host 102. For example, when a plurality of program operations corresponding to a plurality of program commands, a plurality of read operations corresponding to a plurality of read commands, and a plurality of erase operations corresponding to a plurality of erase commands are sequentially, randomly, or alternately executed, the controller 130 may determine which channel or channels or paths among a plurality of channels (or paths) for connecting the controller 130 to a plurality of memory dies included in the memory 150 are suitable for performing each operation. The controller 130 may send or transmit data or instructions via the determined channel or pathway for performing each operation. After each operation is completed, the multiple memory dies included in the memory 150 may transmit the operation results via the same channel or pass, respectively. The controller 130 may then transmit a response or acknowledgement signal to the host 102. In one embodiment, the controller 130 may check the status of each channel or each lane. In response to a command input from the host 102, the controller 130 may select at least one channel or lane based on the state of each channel or each lane so that instructions and/or operation results related to data may be transmitted via the selected channel(s) or lane(s).

By way of example and not limitation, controller 130 may identify status regarding a plurality of channels (or lanes) associated with a plurality of memory dies included in memory device 150. The controller 130 may determine the status of each channel or each lane as one of a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or lane the instructions (and/or data) are transferred by may be associated with the physical block address (e.g., to which die(s) the instructions (and/or data) are transferred). The controller 130 may refer to the descriptor transferred from the memory device 150. The descriptor may include a block or page that describes parameters about certain contents of the memory device 150, which is data having a predetermined format or structure. For example, the descriptors may include device descriptors, configuration descriptors, unit descriptors, and the like. The controller 130 may reference or use the descriptors to determine via which channel or channels or paths to exchange instructions or data.

A management unit (not shown) may be included in the processor 134. The management unit may perform fault block management on the memory device 150. The management unit may find a defective memory block in the memory device 150 that is in an unsatisfactory condition and cannot be used further, and perform defective block management on the defective memory block. When the memory device 150 is a flash memory (e.g., a NAND flash memory), a program failure may occur during a write operation (e.g., during a program operation) due to the characteristics of the NAND logic function. During fault block management, a program-faulty memory block or data of a faulty memory block may be programmed into a new memory block. The defective block may seriously deteriorate the utilization efficiency of the memory device 150 having the 3D stack structure and the reliability of the memory system 110. Thus, reliable fault block management may enhance or improve the performance of the memory system 110.

Referring to FIG. 3, a controller in a memory system according to another embodiment of the present disclosure is depicted, controller 130 cooperates with host 102 and memory device 150, as shown, controller 130 includes host interface 132, flash translation layer (FT L) 40, and host interface 132, memory interface 142, and memory 144 previously defined in connection with FIG. 2.

Although not shown in FIG. 3, according to one embodiment, ECC unit 138 described with reference to FIG. 2 may be included in flash translation layer (FT L) 40 in another embodiment, ECC unit 138 may be implemented as a separate module, circuit, firmware, etc. included in controller 130 or associated with controller 130.

The host interface 132 is used to process commands, data, and the like transmitted from the host 102. By way of example and not limitation, host interface 132 may include command queue 56, buffer manager 52, and event queue 54. The command queue 56 may sequentially store commands, data, etc. received from the host 102 and output them to the buffer manager 52 in the order in which they were stored. Buffer manager 52 may sort, manage, or adjust commands, data, etc. received from command queue 56. The event queue 54 may sequentially transmit events for processing commands, data, etc. received from the buffer manager 52.

The host interface 132 may store the commands, data, etc. sequentially to the command queue 56, thereafter, the host interface 132 may estimate or predict what internal operations the controller 130 will perform based on the characteristics of the commands, data, etc. that have been input from the host 102. the host interface 132 may determine the order and priority of processing of the commands, data, etc. based on at least their characteristics, the buffer manager 52 in the host interface 132 is configured to determine whether the buffer manager should store the commands, data, etc. in the memory 144, or whether the buffer manager should transmit the commands, data, etc. to the flash memory system 102 in response to the commands, data, etc. received from the flash memory system 102, the buffer manager 3552 in response to the commands, data, etc. received from the flash memory system 102, the buffer manager 84, the buffer manager may transmit the commands, data, etc. to the flash memory system 110 in response to the commands, data, etc. (read commands, write commands, etc. mixed or scrambled by the host 102. the host interface 132 may store the commands, data, etc. to the command queue 56.

According to one embodiment, the host interface 132 described with reference to fig. 3 may perform some of the functions of the controller 130 described with reference to fig. 1-2. As shown in fig. 6 or 9, the host interface 132 may set the memory 106 as a slave in the host 102 and add the memory 106 as additional storage space that may be controlled or used by the controller 130.

According to one embodiment, flash translation layer (FT L) 40 may include a Host Request Manager (HRM)46, a Mapping Manager (MM)44, a state manager 42, and a block manager 48. Host Request Manager (HRM)46 may manage events incoming from event queue 54. Mapping Manager (MM)44 may process or control mapping data. state manager 42 may perform Garbage Collection (GC) or wear leveling (W L.) Block manager 48 may perform commands or instructions on blocks in memory device 150.

By way of example and not limitation, the Host Request Manager (HRM)46 may process requests according to read and program commands and events communicated from the host interface 132 using the Mapping Manager (MM)44 and the block manager 48. The Host Request Manager (HRM)46 may send an inquiry request to the mapping data manager (MM)44 to determine a physical address corresponding to a logical address entered with an event. The Host Request Manager (HRM)46 may send a read request with a physical address to the memory interface 142 to process the read request (process event). On the other hand, the Host Request Manager (HRM)46 may send a program request (write request) to the block manager 48 to program data to a specific empty page (no data) in the memory device 150, and then may transmit a mapping update request corresponding to the program request to the Mapping Manager (MM)44 to update an item related to the program data in the information mapping the logical-physical addresses to each other.

Here, the block manager 48 may convert program requests communicated from the Host Request Manager (HRM)46, the mapping data manager (MM)44, and/or the status manager 42 into flash program requests for the memory device 150 to manage flash blocks in the memory device 150. To maximize or enhance program or write performance of memory system 110 (see fig. 2), block manager 48 may collect program requests and send flash program requests to memory interface 142 for multiple planes and a single programming operation. In one embodiment, block manager 48 sends several flash program requests to memory interface 142 to enhance or maximize parallel processing for multi-channel and multi-directional flash controllers.

In another aspect, the block manager 48 may be configured to: managing blocks in the memory device 150 according to the number of valid pages, selecting and erasing blocks that do not have valid pages when free blocks are needed, and selecting blocks that include the fewest number of valid pages when garbage collection is determined to be needed. The state manager 42 may perform garbage collection to move valid data to empty blocks and erase blocks containing the moved valid data so that the block manager 48 may have enough free blocks (empty blocks with no data). If block manager 48 provides information to status manager 42 regarding the block to be erased, status manager 42 may check all flash pages of the block to be erased to determine if each page is valid. For example, to determine the validity of each page, state manager 42 may identify a logical address recorded in an out-of-band (OOB) area of each page. To determine whether each page is valid, the state manager 42 may compare the physical address of the page to the physical address mapped to the logical address obtained from the inquiry request. The state manager 42 sends a program request to the block manager 48 for each valid page. When the program operation is complete, the mapping table may be updated with updates by mapping manager 44.

Mapping manager 44 may manage a logical-physical mapping table. The mapping manager 44 may process requests, such as queries, updates, etc., generated by a Host Request Manager (HRM)46 or the state manager 42. Mapping manager 44 may store the entire mapping table in memory device 150 (e.g., flash/non-volatile memory) and cache mapping entries according to the storage capacity of memory 144. When a mapping cache miss occurs while processing a query or update request, mapping manager 44 may send a read request to memory interface 142 to load the associated mapping table stored in memory device 150. When the number of dirty cache blocks in mapping manager 44 exceeds a certain threshold, a program request may be sent to block manager 48 so that clean cache blocks are formed and a dirty mapping table may be stored in memory device 150.

On the other hand, when performing garbage collection, the state manager 42 copies the valid page(s) into a free block, and the Host Request Manager (HRM)46 can program the latest version of data for the same logical address of the page and currently issue an update request. When state manager 42 requests a mapping update in a state where copying of the valid page(s) is not normally completed, mapping manager 44 may not perform a mapping table update. This is because, if the state manager 42 requests a mapping update and later completes a valid page copy, old physical information is sent to the mapping request. The mapping manager 44 may perform a mapping update operation to ensure accuracy only if the latest mapping table still points to the old physical address.

According to one embodiment, at least one of state manager 42, mapping manager 44, or block manager 48 may include circuitry to perform its own operations. As used in this disclosure, the term "circuit device" refers to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation in analog and/or digital circuitry only) and (b) a combination of circuitry and software (and/or firmware), such as (as desired): (i) a combination of processor(s), or (ii) processor (s)/software (including portions of digital signal processor(s), software, and memory (s)) that work together to cause a device, such as a mobile phone or server, to perform various functions, and (c) circuitry (e.g., microprocessor(s) or a portion of microprocessor (s)) that requires software or firmware to operate even though software or firmware is not actually present. The definition of "circuit device" applies to all uses of the term in this application, including any claims. As another example, as used in this application, the term "circuitry" also encompasses implementations of just one processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. The term "circuit arrangement" also covers an integrated circuit for a memory device, for example if applicable to a particular claim element.

Depending on the number of bits that may be stored or represented in one memory unit, the multiple memory blocks may be any different type of memory block (e.g., a single level cell (S L C) memory block, a multi-level cell (M L C) memory block, etc.). here, the S L C memory block includes multiple pages implemented by memory units each storing one bit of data.s L C memory block may have higher data I/O operation performance and higher endurance.m L C memory block includes multiple pages implemented by memory units each storing multiple bits of data (e.g., two or more bits). compared to the S L C memory block, the M L C memory block may have a larger storage capacity in the same space.m L C memory block may be highly integrated in view of the storage capacity.

In one embodiment of the present disclosure, the memory device 150 is implemented as a non-volatile memory (e.g., a flash memory such as a NAND flash memory, a NOR flash memory, etc.). Alternatively, the memory device 150 may be implemented by at least one of a Phase Change Random Access Memory (PCRAM), a Ferroelectric Random Access Memory (FRAM), a spin injection magnetic memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), and the like.

Fig. 4 and 5 illustrate a case where a part of the memory included in the host may be used as a cache device for storing metadata used in the memory system.

Referring to fig. 4, the host 102 may include a processor 104, a memory 106, and a host controller interface 108. Memory system 110 may include a controller 130 and a memory device 150. Herein, the controller 130 and the memory device 150 described with reference to fig. 4 may correspond to the controller 130 and the memory device 150 described with reference to fig. 1 to 3.

Hereinafter, differences between the controller 130 and the memory device 150 shown in fig. 4, which may be technically distinguished, and the controller 130 and the memory device 150 shown in fig. 1 to 3 are mainly described in detail in particular, the logic block 160 in the controller 130 may correspond to the flash translation layer (FT L) 40 described with reference to fig. 3, however, according to one embodiment, the logic block 160 in the controller 130 may perform additional functions not described in the flash translation layer (FT L) 40 shown in fig. 3.

The host 102 may include a processor 104 and a memory 106, the processor 104 having higher performance than the memory system 110, the memory 106 capable of storing a larger amount of data than the memory system 110 in cooperation with the host 102. The processor 104 and memory 106 in the host 102 may have advantages in terms of space and scalability. For example, the processor 104 and the memory 106 may have fewer space limitations than the processor 134 and the memory 144 in the memory system 110. Processor 104 and memory 106 may be replaceable to upgrade their performance, unlike processor 134 and memory 144 in memory system 110. In an embodiment, the memory system 110 may utilize resources owned by the host 102 to improve the operating efficiency of the memory system 110.

As the amount of data that can be stored in the memory system 110 increases, the amount of metadata corresponding to the data stored in the memory system 110 also increases. When the storage capacity for loading metadata into the memory 144 of the controller 130 is limited or restricted, an increase in the amount of loaded metadata may cause an operational burden of the operation of the controller 130. For example, some but not all of the metadata may be loaded due to limitations in the space or area allocated for the metadata in the memory 144 of the controller 130. If the loaded metadata does not include the particular metadata for the physical location that the host 102 intends to access, the controller 130 must store the loaded metadata back into the memory device 150 and load the particular metadata for the physical location that the host 102 intends to access, in the event that some of the loaded metadata has been updated. These operations should be performed with respect to the controller 130 to perform read or write operations required by the host 102 and may reduce the performance of the memory system 110.

The storage capacity of the memory 106 included in the host 102 may be several tens or hundreds of times greater than the storage capacity of the memory 144 included in the controller 130. The memory system 110 may transfer the metadata 166 used by the controller 130 to the memory 106 in the host 102 so that at least a portion of the memory 106 in the host 102 may be accessed by the memory system 110. At least a portion of the memory 106 may be used as a cache for storing address translations needed to read or write data in the memory system 110. In this case, the host 102 translates the logical address to a physical address based on the metadata 166 stored in the memory 106 before transmitting the logical address to the memory system 110 along with the request, command, or instruction. The host 102 may then transmit the translated physical address to the memory system 110 with a request, command, or instruction. The memory system 110 receiving the translated physical address with a request, command, or instruction may skip the internal process of translating the logical address to the physical address and access the memory device 150 based on the passed physical address. In this case, overhead (e.g., operational burden) of the controller 130 loading metadata for address translation from the memory device 150 may disappear, and the operational efficiency of the memory system 110 may be enhanced.

On the other hand, even if the memory system 110 transmits the metadata 166 to the host 102, the memory system 110 may control the mapping information based on the metadata 166 (e.g., metadata generation, erasure, update, etc.). The controller 130 in the memory system 110 may perform background operations such as garbage collection and wear leveling depending on the operating state of the memory device 150 and may determine the physical address (i.e., which physical location in the memory device 150 the data transferred from the host 102 is to be stored in). Because the physical address of data stored in the memory device 150 can be changed, and the host 102 does not recognize the changed physical address, the memory system 110 can actively control the metadata 166.

While the memory system 110 controls the metadata for address translation, it may be determined that the memory system 110 needs to modify or update the metadata 166 previously transmitted to the host 102. The memory system 110 may send a signal or metadata to the host 102 to request an update of the metadata 166 stored in the host 102. The host 102 may update the metadata 166 stored in the memory 106 in response to requests transmitted from the memory system 110. This allows the metadata 166 stored in the memory 106 in the host 102 to be kept up-to-date, so that even if the host controller interface 108 uses the metadata 166 stored in the memory 106, no problems arise in the operation of converting logical addresses into physical addresses and in the operation of transmitting the converted physical addresses to the memory system 110 together with the logical addresses.

Meanwhile, the metadata 166 stored in the memory 106 may include mapping information for converting logical addresses into physical addresses. Referring to FIG. 4, the metadata associating logical addresses with physical addresses may include two distinguishable items: a first mapping information item for converting a logical address into a physical address; and a second mapping information item for converting the physical address into the logical address. Among other things, the metadata 166 stored in the memory 106 may include first mapping information. The second mapping information may be primarily used for internal operations of the memory system 110, but may not be used for operations requested by the host 102 to store data in the memory system 110 or to read data corresponding to a specific logical address from the memory system 110. According to one embodiment, the second mapping information item may not be transmitted by the memory system 110 to the host 102.

Meanwhile, the controller 130 in the memory system 110 may control (e.g., create, delete, update, etc.) the first mapping information item or the second mapping information item and store the first mapping information item or the second mapping information item to the memory device 150. Because the memory 106 in the host 102 is a type of volatile memory, the metadata 166 stored in the memory 106 may disappear when an event occurs, such as an interruption of power to the host 102 and the memory system 110. Thus, the controller 130 in the memory system 110 may not only maintain the latest state of the metadata 166 stored in the memory 106 of the host 102, but may also store the latest state of the first mapping information item or the second mapping information item in the memory device 150.

Referring to fig. 4 and 5, operations are described in which the host 102 requests to read data stored in the memory system 110 when the metadata 166 is stored in the memory 106 of the host 102.

Power is supplied to the host 102 and the memory system 110, and the host 102 and the memory system 110 may then engage each other when the host 102 and the memory system 110 cooperate, the metadata (L2P MAP) stored in the memory device 150 may be transferred to the host memory 106.

After receiving the Read command, the host controller interface 108 searches for a physical address corresponding to the logical address corresponding to the Read command in the metadata (L2P MAP) stored in the host memory 106. based on the metadata (L2P MAP) stored in the host memory 106, the host controller interface 108 may identify the physical address corresponding to the logical address.

The host controller interface 108 passes a Read command (Read CMD) having a logical address as well as a physical address into the controller 130 of the memory system 110. The controller 130 may access the memory device 150 based on the physical address entered with the read command. Data stored at a location corresponding to a physical address in the memory device 150 may be transferred to the host memory 106 in response to a Read command (Read CMD).

An operation of reading data stored in the memory device 150 including a nonvolatile memory may take more time than an operation of reading data stored in the host memory 106 or the like as a volatile memory. In the above-described operation for processing a Read command (Read CMD), the controller 130 may skip or omit address translation corresponding to a logical address input from the host 102 (e.g., search for and identify a physical address associated with the logical address). For example, in address translation, when controller 130 cannot find metadata for address translation in memory 144, controller 130 may not have to load metadata from memory device 150 or replace the metadata stored in memory 144. This allows the memory system 110 to perform read operations requested by the host 102 more quickly.

FIG. 6 illustrates a first example of a transaction between a host 102 and a memory system 110 in a data processing system according to one embodiment of this disclosure.

Referring to fig. 6, a host 102 storing mapping information (MAP INFO) may transfer a READ COMMAND including a logical address L BA and a physical address PBA to a memory system 110 when a physical address PBA corresponding to a logical address L BA transferred to the memory system 110 using the READ COMMAND (READ COMMAND) is found in the mapping information stored in the host 102, the host 102 may transfer a READ COMMAND (READ COMMAND) having a logical address L BA and a physical address PBA into the memory system 110, however, when a physical address PBA corresponding to a logical address L BA transferred using the READ COMMAND (READ COMMAND) is not found in the mapping information stored by the host 102, the host 102 may transfer a READ COMMAND (READ COMMAND) including only the logical address L BA into the memory system 110 without the physical address PBA.

Although fig. 6 describes operations in response to a READ COMMAND (READ COMMAND) as an example, one embodiment of the disclosure may be applied to write COMMANDs or erase COMMANDs that host 102 may pass into memory system 110.

In detail, FIG. 7 illustrates detailed operations in which the host transmits a command including a logical address L BA and a physical address PBA and the memory system receives a command having a logical address L BA and a physical address PBA, similar to the host 102 and the memory system 110 described with reference to FIG. 6.

Referring to FIG. 7, the host may generate a COMMAND COMMAND that includes logical address L BA (step 812). thereafter, the host may check whether the physical address PBA corresponding to logical address L BA is in the mapping information (step 814). if no physical address PBA exists ("NO" of step 814), the host may transmit a COMMAND COMMAND that includes logical address L BA without a physical address PBA (step 818).

On the other hand, if there is a physical address PBA (YES at step 814), the host may add the physical address PBA to a COMMAND including logical address L BA (step 816). the host may transmit a COMMAND including logical address L BA and physical address PBA (step 818).

The memory system may receive a command transmitted from the outside (step 822). The memory system may check whether a command with physical address PBA is entered (step 824). When a command with a physical address PBA is not input ("no" in step 824), the memory system may perform a mapping operation or address translation (e.g., search for a physical address corresponding to a logical address input with the command) (step 832).

When a command with physical address PBA is entered (YES at step 824), the memory system may check whether the physical address PBA is valid (step 826). The memory system has transmitted the mapping information to the host, and the host may perform a mapping operation based on the mapping information transmitted from the memory system to transfer a command having a physical address PBA to the memory system. However, after the memory system transmits the mapping information to the host, the transmitted mapping information managed or controlled by the memory system may be changed and updated. When the mapping information is dirty, it may not be possible to access data using the physical address PBA transferred from the host, and thus the memory system may determine whether the physical address PBA input with the command is valid, i.e., whether the mapping information corresponding to the physical address PBA has been changed or updated. When the physical address PBA entered with the command is valid (yes at step 826), the memory system may perform the operation corresponding to the command using the physical address PBA (step 830).

When the physical address PBA entered with the command is invalid ("NO" of step 826), the memory system may ignore the physical address PBA entered with the command (step 828). in this case, the memory system may search for the physical address PBA based on the logical address L BA entered with the command (step 832).

FIG. 8 illustrates initial operation of a memory system according to one embodiment of the present disclosure. FIG. 8 illustrates that during the operations described with reference to FIG. 1, initial operations may be performed in the memory system 110 when power is supplied to the host 102 and the memory system 110. For example, the initial operations may include a boot sequence or operations that may be performed after power is applied before the host requests user data from the memory system. The operation of the memory system shown in fig. 8 may vary depending on whether the memory system is installed on a mobile device, a notebook computer, or a computing device such as a desktop computer.

Referring to fig. 8, the operation of the memory system via firmware includes: the subject platform is set up (step 91), hardware abstraction is performed (step 93), the bootable image is loaded (step 95), control is relinquished and handed over to the computing device (which is associated or interfaced with the memory device) (step 97), and the mapping information is passed to the computing device (step 99). Herein, the computing device may include the host 102 shown in fig. 1-7.

The setting step 91 of the subject platform may be performed by preparing an environment for booting an Operating System (OS), thereby confirming whether the subject platform has been initialized. In this step, the exact kernel type and platform should be found and identified because the same executable image can be executed on different kernels or platforms. By way of example and not limitation, the type of core may be stored in coprocessor register 0. The type of platform may be determined by checking for the presence of a particular peripheral or reading information stored in the chip.

Additionally, according to one embodiment, in the set subject platform step 91, diagnostic software may be used to determine whether a hardware component is defective.

Additionally, according to one embodiment, in the step 91 of setting up the subject platform, any problems of the hardware found by means of the diagnostic software may be debugged according to debugging code or the like.

The step 93 of hardware abstraction may be performed by means of a hardware abstraction layer (HA L), HA L being a software layer that hides the hardware by means of a defined set of programming interfaces, by way of example and not limitation, the hardware abstraction layer (HA L) may comprise software or drivers that enable a processor within the controller 130 to communicate with specific peripheral hardware.

The step 95 of loading the bootable image may include forwarding or executing an operating system or application included in the user data area to a host or computing device that is interfaced or associated with the memory system.

The step 97 of handing over (or transferring) control to the computing device engaged with the memory system may be performed by a boot loader included in the firmware. The step of handing over control (step 97) may include the step of transferring control of the identified platform from the firmware into the operating system or application.

The step 99 of communicating the mapping information to the computing device may include: the step of transferring the mapping from the memory system 100 to the host 102 after power-up as described with reference to FIG. 1. After the memory system 110 may select mapping information based on a log or history stored prior to the power outage, the selected mapping information may be passed to a computing device or host. An operation or process for the memory system to transfer the mapping information to the computing device or host will be described in detail below with reference to fig. 9 to 12.

During initial operation after power is applied, the operation for the memory system to transfer mapping information to the computing device or host may be different or distinct from another operation that processes commands or instructions received from the host and then transmits the mapping information to the computing device or host according to the processing results. The memory system may identify a frequency of use of data requested by the computing device or the host by a process of processing a plurality of commands or instructions input from the computing device or the host. However, it may be difficult to determine which mapping information the memory system transfers to the computing device or host because the initial operation after power-on is performed before multiple operations in response to multiple commands or instructions transmitted from the computing device or host. When the memory system transmits mapping information relating to data that is not frequently accessed or used by the computing device or host into the computing device or host, the transmitted mapping information may be useless, i.e., the effect achieved by sharing the mapping information between the memory system and the computing device or host may be insufficient or not good. However, in one embodiment of the present disclosure, selected mapping information is shared between the memory system and the computing device or host based on a log or history stored in the memory system, thereby improving or enhancing the operation of a data processing system including the memory system and the computing device or host (e.g., input/output (I/O) throughput of the memory system).

FIG. 9 illustrates a second example of a transaction between a host and a memory system in a data processing system according to one embodiment of this disclosure.

Referring to fig. 9, the memory system 110 may communicate mapping information (MAP INFO) to the host 102. The memory system 110 may use a RESPONSE to the command of the host 102 to transfer the mapping information (MAP INFO). Herein, the RESPONSE is a message or packet transmitted after the memory system fully performs an operation in RESPONSE to a command input from the host 102.

In one embodiment, there may be no particular limitation on the response for transmitting the mapping information. For example, the memory system 110 may transmit the mapping information to the host 102 by using a response corresponding to a read command, a write command, or an erase command.

The memory system 110 and the host 102 may exchange commands or responses with each other in a particular format arrangement according to a predetermined protocol. For example, the format of the RESPONSE may include a base header, a result or status of success or failure according to a command input from the host 102, and additional information indicating the operating status of the memory system 110. The memory system 110 may add or insert the mapping information into the format of the RESPONSE to transmit the mapping information to the host 102.

FIG. 10 illustrates a second operation between a host and a memory system according to one embodiment of the present disclosure. Specifically, fig. 10 illustrates an operation in which the host 102 first requests the mapping information from the memory system 110, and then the memory system 110 transmits the mapping information in response to the request of the host 102.

Referring to fig. 10, mapping information may be needed at the host 102. For example, if the host 102 can allocate space to store mapping information, or if the host 102 desires the memory system 110 to more quickly input/output (I/O) data in response to a host command, the host 102 can request the mapping information from the memory system 110. Additionally, the need for mapping information may also be generated in the host 102 at the request of the user.

The host 102 may request the mapping information from the memory system 110, and the memory system 110 may prepare the mapping information in response to the request from the host 102. In one embodiment, the host 102 may request particular mapping information, such as a particular range of mapping information, from the memory system 110. In another embodiment, the host 102 may generally request mapping information from the memory system 110, and the memory system 110 may determine which mapping information to provide to the host 102.

After the memory system 110 transfers the prepared mapping information to the host 102, the host 102 may store the transferred mapping information in an internal storage space (e.g., the memory 106 described with reference to fig. 4).

Using the stored mapping information, host 102 may add physical address PBA in the format of a COMMAND transmitted to memory system 110 and transmit the format of a COMMAND including physical address PBA. The memory system 110 may then use the physical address PBA input from the host 102 using the COMMAND to perform an operation corresponding to the COMMAND.

FIG. 11 illustrates a third operation between a host and a memory system according to one embodiment of the present disclosure. Specifically, fig. 11 illustrates an operation in which the memory system 110 queries the host 102 to transmit mapping information, the host 102 determines whether to allow transmission from the memory system 110, and the host 102 receives the mapping information in response to the query of the memory system 110.

Referring to FIG. 11, the memory system 110 may notify the host 102 to transfer the mapping information. The host 102 may determine whether the host 102 may store mapping information associated with a notification regarding the transmission of the mapping information (communicated from the memory system 110). If the host 102 can receive and store mapping information input from the memory system 110, the host 102 may allow the memory system 100 to communicate the mapping information. According to one embodiment, the memory system 110 may prepare mapping information to be transmitted and then transmit the prepared mapping information to the host 102.

The host 102 may store the received mapping information in an internal storage space (e.g., the memory 106 described with reference to fig. 4). The host 102 may include the physical address PBA in the command to be transmitted to the memory system 110 after performing the mapping operation based on the stored mapping information.

The memory system 110 may check whether the physical address PBA is included in the command transferred from the host 102, and apply the physical address PBA to perform an operation corresponding to the command.

With regard to the transmission of the mapping information, the host 102 may actively perform the operations between the host 102 and the memory system 110 described with reference to fig. 10. However, the memory system 110 may actively perform the operations between the host 102 and the memory system 110 described with reference to fig. 11. The memory system 110 may perform the transmission of the mapping information differently according to different embodiments. The memory system 102 and the host 110 may selectively use the method for transmitting the mapping information described with reference to fig. 10 to 11 according to an operating condition or environment.

FIG. 12 illustrates a fourth operation between the host and the memory system according to one embodiment of the present disclosure. In detail, fig. 12 illustrates a case where the memory system attempts to transmit mapping information to the host when the host and the memory system are operatively engaged with each other.

Referring to fig. 12, the memory system may determine whether an operation corresponding to the command transmitted from the host is completed (step 862). After the operation corresponding to the command is completed, the memory system may check whether there is mapping information to be transmitted to the host before transmitting the response corresponding to the command (step 864). If there is no mapping information to be transferred to the host ("no" at step 864), the memory system may transmit a RESPONSE (step 866) that includes information regarding whether the operation corresponding to the command sent from the host has completed (e.g., success or failure).

When the memory system identifies mapping information to be transferred to the host (yes at step 864), the memory system may check whether a notification has been made to transfer the mapping information (step 868). The notification may be similar to the notification described with reference to fig. 11. When the memory system is to send the mapping information but has not previously made a notification that the memory system sent the mapping information to the host ("no" at step 868), the memory system may add a notification NOTICE to the RESPONSE. Additionally, the memory system may transmit a RESPONSE with a notify to the host (step 870).

When a notification NOTICE has been made to query the transmission of the mapping information (YES at step 868), the memory system may add the mapping information to the response (step 872). Thereafter, the memory system may transmit a response including the mapping information (step 874). According to one embodiment, the host may send permission to transfer the mapping information to the memory system before the memory system transfers the mapping information to the host.

The host may receive at least one of a RESPONSE, a RESPONSE including a notification (RESPONSE WITH notify), or a RESPONSE including mapping information (RESPONSE WITH MAP INFO) transmitted by the memory system and received by the host (step 842).

The host may verify whether the received response includes a notification (step 844). If the received response includes a notification (YES at step 844), the host may prepare to receive and store mapping information that may be transmitted later (step 846). Thereafter, the host may check for a response corresponding to the command previously transmitted to the memory system (step 852). For example, the host may check the response to confirm whether the operation corresponding to the previously sent command succeeded or failed in the memory system.

When the received response does not include a notification (no at step 844), the host may determine whether the response includes mapping information (step 848). When the response does not include mapping information (no at step 848), the host may check for a response corresponding to a command previously transferred to the memory system (step 852).

When the received response includes mapping information (yes at step 848), the host may store the mapping information included in the response in the memory space or update mapping information already stored in the memory space (step 850). The host may then check for a response corresponding to the command previously transmitted to the memory system (step 852).

Based on the above embodiments, the memory system may transmit the mapping information to the host. After processing the command transmitted by the host, the memory system may transmit mapping information with a response associated with the transmitted command. Additionally, the memory system may transmit the mapping information to the host and then generate and store a log or history record about the transmitted mapping information. Even if power is restored after the host and the memory system are powered down, the memory system can transmit the mapping information to the host using the log or the history as described above. The host may transmit a command having logical and physical addresses to the memory system after performing a mapping operation or address translation based on the transmitted mapping information. Data input/output (I/O) performance of a memory system may be improved or enhanced by commands having logical and physical addresses.

According to embodiments of the present disclosure, a data processing system, a method for operating the data processing system, and a method for controlling operations in the data processing system may provide a memory system capable of transmitting mapping information to a host within a short time after power is restored. Therefore, even if the host loses the mapping information due to a Sudden Power Off (SPO) or the like, the memory system can transmit the mapping information, and the host can restore the mapping information. The host may use the recovered mapping information and send commands to the memory system along with the mapping information, and the memory system may omit operations for address translation to increase input/output (I/O) throughput.

In one embodiment of the present disclosure, the memory system may store a record, log, or history of mapping information shared with the host or computing device prior to power down. When power is restored, the memory system may classify and transmit the mapping information based on the record, log, or history to share the mapping information, thereby improving the operating efficiency of the memory system.

Additionally, according to one embodiment of the present disclosure, when a usage pattern of a user using a data processing system or a computing device including a memory system and a host is not significantly or drastically changed before power-off, since shared mapping information may be selected and transmitted based on the usage pattern after power-on, operational efficiency of the data processing system may be improved.

While the present teachings have been illustrated and described with respect to particular embodiments, it will be apparent to those skilled in the art in light of this disclosure that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the following claims.