阅读说明：本技术 一种基于srt算法的高基除法器电路 (High-radix divider circuit based on SRT algorithm ) 是由 彭春雨 纪俊康 吴秀龙 卢文娟 蔺智挺 陈军宁 于 2020-04-16 设计创作，主要内容包括：本发明公开了一种基于SRT算法的高基除法器电路,所述电路包括商值选择模块QCHS,所述商值选择模块QCHS中包含多个数值比较模块,采用数值比较的方法产出指定的商值选择编码,利用该商值选择编码产出指定的商值和过程余数,其中的过程余数用于下一次迭代运算的执行,直至产出所有商值和最终余数。上述电路采用迭代循环思想,同时采用相对较高基值产出多位商值,以减少迭代周期数,同时优化迭代电路,减少单个周期运行时间,从而提高运算性能。(The invention discloses a high-radix divider circuit based on an SRT algorithm, which comprises a quotient value selection module QCHS, wherein the quotient value selection module QCHS comprises a plurality of numerical value comparison modules, a numerical value comparison method is adopted to generate a designated quotient value selection code, the quotient value selection code is used to generate a designated quotient value and a process remainder, and the process remainder is used for executing next iterative operation until all quotient values and final remainders are generated. The circuit adopts an iterative cycle idea, and simultaneously adopts a relatively high base value to produce a multi-bit quotient value so as to reduce the number of iterative cycles, and simultaneously optimizes the iterative circuit to reduce the running time of a single cycle, thereby improving the operational performance.)

1. A high radix divider circuit based on SRT algorithm is characterized in that the circuit mainly comprises a quotient value selection module QCHS, a dividend shift selection module, a divisor sorting module, a quotient value shift sorting module and an output sorting module RESU L T _ ORDER, wherein:

the quotient value selection module QCHS comprises a plurality of numerical value comparison modules, generates a designated quotient value selection code by adopting a numerical value comparison method, and generates a designated quotient value and a process remainder by utilizing the quotient value selection code, wherein the process remainder is used for executing next iterative operation until all quotient values and final remainders are generated;

the dividend shifting selection module consists of a shifter and is used for selecting the bit value of the dividend by each iterative operation;

the divisor sorting module mainly comprises a shifter and an adder and is used for outputting multiples of divisors; the adder is composed of a carry look ahead adder;

the quotient shifting and sorting module is also composed of a shifter and is used for sorting quotient values produced by each iterative operation, specifically, the quotient values produced by each iteration are placed at a low position, left shifting is carried out after the iteration is finished until the iteration is finished, and a final quotient value is generated;

the output sorting module RESU L T _ ORDER is used for sorting the output quotient value and the process remainder, wherein the quotient value is given by the quotient value shifting and sorting module, and the process remainder is given by the quotient value selecting module QCHS.

2. The SRT algorithm-based high radix divider circuit of claim 1,

the numerical comparison module adopts a plurality of XOR gate cascade structures and is used for judging the size of the multi-bit binary number to generate a designated quotient value selection code.

3. The SRT algorithm-based high radix divider circuit of claim 2, wherein the numerical comparison module is implemented by:

carrying out bitwise XOR on each bit of the input binary numbers A and B to obtain an intermediate result T, wherein the value of each bit of the T is '0' to indicate that the operand has the same value on the bit, and the value of each bit of the T is '1' to indicate that the operand has different values on the bit;

judging bit by bit from the highest bit of T until finding the first bit of '1', judging the value of operand A at the corresponding position, if the bit A is '1', the A is larger than B; if the bit A is '0', A is smaller than B;

and judging bit by bit, if all the bits of T are 0, then A is equal to B.

4. The SRT algorithm-based high radix divider circuit of claim 1,

the quotient value selection module QCHS outputs a quotient value selection code whose bit width is determined by the selected base value, which is the bit width of the selected base value minus 1, and which exactly corresponds to the maximum quotient value supported by the selected base value.

5. The SRT algorithm based high radix divider circuit of claim 1, wherein the quotient selection code rule is:

0000000 for quotient value 0, 0000001 for quotient value 1, 0000011 for quotient value 2, and so on;

the number of "1" in the code represents the quotient value generated by the operation.

6. The SRT algorithm-based high radix divider circuit of claim 1,

iterative cycles of remainder of the output process of the quotient value selection module QCHS can be transmitted by combining clock signals, namely, the number of executable iterations in one clock period is controlled by a clock.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a high-radix divider circuit based on an SRT algorithm.

Background

Arithmetic components are particularly important in today's chip cores. With the improvement of the functional complexity of the computer, the computing demand of people on the computer is also increasing. The arithmetic elements are generally based on four basic arithmetic operations, such as adders, multipliers and dividers. The addition and multiplication generally adopt a carry look ahead adder and a Booth multiplier. The design of the divider is relatively complex, the general design idea is to adopt the idea of shift subtraction and calculate bit by bit, each calculation calculates a quotient value and a corresponding remainder, and then, the calculation is continued on the remainder of the previous bit until the last bit, and the final quotient value and the remainder are calculated.

In today's high performance computer chips, the design of the divider generally employs a divider based on the SRT algorithm, the divider is based on shift subtraction, but the difference is that a plurality of quotient values can be calculated by one operation, the number of digits of the quotient values is determined by a base selected by an operation part, an SRT (sequence random Access) algorithm is a high-performance linear convergence division algorithm, a plurality of quotient values of fixed digits can be calculated by each operation until iteration operation is completed, the final correct quotient value and remainder are calculated, the core of the SRT algorithm is an operation unit of multiple iterations, the operation is one of a digital loop algorithm, the key of the SRT algorithm is the size of the base, the number of the quotient values which can be generated by each iteration is determined, the more digits are, the fewer the iteration times are, the smaller the operation period is, and the higher the algorithm performance is, however, the corresponding hardware design is complicated, and no corresponding solution exists in the prior art.

Disclosure of Invention

The invention aims to provide a high-radix divider circuit based on an SRT algorithm, which adopts an iterative loop idea and simultaneously adopts a relatively high radix value to generate a multi-bit quotient value so as to reduce the number of iterative cycles, optimize an iterative circuit and reduce the running time of a single cycle, thereby improving the operational performance.

The purpose of the invention is realized by the following technical scheme:

a high radix divider circuit based on SRT algorithm, the circuit mainly comprises a quotient value selection module QCHS, a dividend shift selection module, a divisor sorting module, a quotient value shift sorting module and an output sorting module RESU L T _ ORDER, wherein:

the quotient value selection module QCHS comprises a plurality of numerical value comparison modules, generates a designated quotient value selection code by adopting a numerical value comparison method, and generates a designated quotient value and a process remainder by utilizing the quotient value selection code, wherein the process remainder is used for executing next iterative operation until all quotient values and final remainders are generated;

the dividend shifting selection module consists of a shifter and is used for selecting the bit value of the dividend by each iterative operation;

the divisor sorting module mainly comprises a shifter and an adder and is used for outputting multiples of divisors; the adder is composed of a carry look ahead adder;

the quotient shifting and sorting module is also composed of a shifter and is used for sorting quotient values produced by each iterative operation, specifically, the quotient values produced by each iteration are placed at a low position, left shifting is carried out after the iteration is finished until the iteration is finished, and a final quotient value is generated;

the output sorting module RESU L T _ ORDER is used for sorting the output quotient value and the process remainder, wherein the quotient value is given by the quotient value shifting and sorting module, and the process remainder is given by the quotient value selecting module QCHS.

The technical scheme provided by the invention can be seen that the circuit adopts an iterative loop idea, and simultaneously adopts a relatively high base value to generate a multi-bit quotient value so as to reduce the number of iterative cycles, optimize the iterative circuit and reduce the running time of a single cycle, thereby improving the operational performance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic diagram of a circuit structure of a high-radix divider based on an SRT algorithm according to an embodiment of the present invention;

fig. 2 is a schematic flow chart illustrating an implementation process of the numerical comparison module according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The embodiments of the present invention will be further described in detail with reference to the accompanying drawings, and as shown in fig. 1, is a schematic diagram of a circuit structure of a high-radix divider based on an SRT algorithm according to an embodiment of the present invention, where the circuit mainly includes a quotient selection module QCHS, a dividend shift selection module, a divisor sorting module, a quotient shift sorting module, and an output sorting module resuru L T _ ORDER, where:

the quotient value selection module QCHS comprises a plurality of numerical value comparison modules, generates a designated quotient value selection code by adopting a numerical value comparison method, and generates a designated quotient value and a process remainder by utilizing the quotient value selection code, wherein the process remainder is used for executing next iterative operation until all quotient values and final remainders are generated;

the dividend shifting selection module consists of a shifter and is used for selecting the bit value of the dividend by each iterative operation; for example, by adopting the base 8 operation, the three-bit value of the dividend is selected in turn from the highest bit to participate in the operation, and after the operation is finished, the dividend is shifted to the left by three bits;

the divisor sorting module mainly comprises a shifter and an adder and is used for outputting multiples of divisors; the adder is composed of a carry look ahead adder; in the specific implementation, even multiplication is directly calculated by a shifter, for example, 2-time divisor is shifted to the left by one bit; 4 times of divisor, the divisor is shifted to the left by two bits, and so on; odd multiplication is generated by adding a divisor value to an adjacent divisor multiplication value, for example, a divisor of 3 times is generated by adding a divisor value to a divisor of 2 times;

the quotient shifting and sorting module is also composed of a shifter and is used for sorting quotient values produced by each iterative operation, specifically, the quotient values produced by each iteration are placed at a low position, left shifting is carried out after the iteration is finished until the iteration is finished, and a final quotient value is generated;

the output sorting module RESU L T _ ORDER is used for sorting the output quotient value and the process remainder, wherein the quotient value is given by the quotient value shift sorting module, and the process remainder is given by the quotient value selection module QCHS.

In specific implementation, the numerical comparison module adopts a plurality of exclusive-or gate cascade structures and is used for judging the size of the multi-bit binary number to generate a specified quotient value selection code. Fig. 2 is a schematic diagram illustrating an implementation process of the numerical comparison module according to the embodiment of the present invention, where the implementation process of the numerical comparison module specifically includes:

carrying out bitwise XOR on each bit of the input binary numbers A and B to obtain an intermediate result T, wherein the value of each bit of the T is '0' to indicate that the operand has the same value on the bit, and the value of each bit of the T is '1' to indicate that the operand has different values on the bit;

judging bit by bit from the highest bit of T until finding the first bit of '1', judging the value of operand A at the corresponding position, if the bit A is '1', the A is larger than B; if the bit A is '0', A is smaller than B;

and judging bit by bit, if all the bits of T are 0, then A is equal to B.

As shown in FIG. 2, an output result of "1" indicates that operand A is greater than or equal to B, and a "0" indicates that A is less than B.

In addition, the quotient value selection module QCHS generates a quotient value selection code whose bit width is determined by the selected base value, which is the bit width of the selected base value minus 1, and which exactly corresponds to the maximum quotient value supported by the selected base value. For example, the base value is 4, the coding bit width is 3; the base value is 8 and the coding bit width is 7.

The rule of the quotient value selection coding is as follows:

0000000 for quotient value 0, 0000001 for quotient value 1, 0000011 for quotient value 2, and so on;

the number of "1" in the code represents the quotient value generated by the operation.

For example, a general iterative formula of the SRT algorithm is as follows:

j＝1，2，...，k

wherein, W is a process remainder; r is a selected group; z is a dividend with a plurality of digits corresponding to the base; q is the multi-digit quotient value of the corresponding base; d is a divisor; the value of k represents the number of times that the operand requires iterative operation; r is the remainder.

The above formula has two important parameters, a base r and a redundancy factor of the quotient, for a given base (typically r ═ 2)^θ) The SRT algorithm calculates the quotient of e bits by iteration each time, and the selection of the cardinal number determines the iteration times k:

k＝[Width÷log₂r]_max

rounding up, it can be seen that the larger the radix r, the smaller the iteration number k.

Parallel comparison rW by the value comparison module_[j]+Z_[j-1]And the relative multiple of the divisor d, and the comparison result is coded, taking the division of base 8 as an example, by coding the product value by:

COMP_CODE：0000000→q＝0

COMP_CODE：0000001→q＝1

COMP_CODE：0000011→q＝2

COMP_CODE：0000111→q＝3

COMP_CODE：0001111→q＝4

COMP_CODE：0011111→q＝5

COMP_CODE：0111111→q＝6

COMP_CODE：1111111→q＝7

each bit value of the seven-bit code is generated by a numerical value comparison module; COMP _ CODE [0 ]]rW for 1_[j]+Z_[i-1]D is greater than or equal to d; COMP _ CODE [1 ]]rW for 1_[j]+Z_[i-1]Greater than or equal to 2 d; COMP _ CODE [3 ]]rW for 1_[j]+Z_[i-1]Greater than or equal to 3 d; and analogizing in turn, so the quotient value can be determined according to the number of 1 in the code, and the number of '1' in the code represents the quotient value quantity produced by the operation.

The COMP _ CODE encoding also requires control of the production of a corresponding process remainder, where the process remainder W is generated in relation to the quotient, the upper-order process remainder, and the divisor d, and the calculation formula is:

W_[j-1]＝rW_[j]+Z_[j-1]-q_[j-1]d

process remainder W_j-1The adder is realized by addition according to the formula, the adder in the embodiment adopts a carry-look-ahead adder to write Verilog codes on each module, the Verilog codes are realized and verified at the RT L level, and the verification at the RT L level is performed by using a Candense front-end simulation tool NC-Verilog.

In this example, 32-bit division based on 8 is adopted, 11 quotient value selection modules QCHS need to be instantiated in the design code, and a proper value comparison module and a carry look ahead adder are designed according to the bit width of the operand. The quotient value selection module QCHS iterates mutually to sequentially generate 3-bit quotient values, and meanwhile, 7 numerical value comparison modules with corresponding bit widths are instantiated in the quotient value selection module QCHS and are used for simultaneously generating each bit coding value of COMP _ CODE; and the main module and each sub-module are provided with an adder for multiple instantiations so as to be prepared for sorting data of each phase.

In addition, since radix 8 iterates through three quotient values at one time, the operation of selecting 32-bit operands cannot be divided; in this example, the 32-bit operand can be widened, that is, the 32-bit operand is expanded into a 33-bit operand by supplementing a bit "0" to the upper bit; similarly, for a 64-bit operand, i.e. two "0" bits are filled in the upper bits, and the corresponding quotient value bit width also needs to be defined as 33 bits, but since the highest bit is always "0", the highest bit of the quotient is also always "0".

It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.