阅读说明：本技术 一种机载雷达空时自适应处理器 (Airborne radar space-time adaptive processor ) 是由 苏涛 彭宇 张永振 于 2020-03-02 设计创作，主要内容包括：本发明涉及一种机载雷达空时自适应处理器,包括：第一预处理板卡、第二预处理板卡、第一自适应板卡、第二自适应板卡、交换板卡、机箱和上位机,其中,第一预处理板卡连接在机箱上,并且连接上位机；第二预处理板卡连接在机箱上,并且连接上位机；第一自适应板卡连接在机箱上；第二自适应板卡连接在机箱上；交换板卡连接在机箱上；上位机连接交换板卡。该空时自适应处理器运算处理器少,成本低,功耗低,尽可能采用更少的运算处理器,实现整个机载雷达空时自适应处理器。(The invention relates to an airborne radar space-time adaptive processor, which comprises: the system comprises a first preprocessing board card, a second preprocessing board card, a first self-adaptive board card, a second self-adaptive board card, a switching board card, a case and an upper computer, wherein the first preprocessing board card is connected to the case and is connected with the upper computer; the second preprocessing board card is connected to the case and is connected with the upper computer; the first self-adaptive board card is connected to the chassis; the second self-adaptive board card is connected to the case; the exchange board card is connected to the chassis; the upper computer is connected with the exchange board card. The space-time adaptive processor has the advantages of few operation processors, low cost and low power consumption, adopts fewer operation processors as far as possible, and realizes the whole airborne radar space-time adaptive processor.)

1. An airborne radar space-time adaptive processor, comprising: a first preprocessing board card, a second preprocessing board card, a first self-adaptive board card, a second self-adaptive board card, a switching board card, a case and an upper computer,

the first preprocessing board card is connected to the case, connected to the upper computer, and used for receiving the AD sampling data sent by the upper computer, preprocessing the AD sampling data, and obtaining and outputting first distance Doppler data;

the second preprocessing board card is connected to the case, connected to the upper computer, and used for receiving the AD sampling data sent by the upper computer, preprocessing the AD sampling data, and obtaining and outputting second distance Doppler data;

the first adaptive board card is connected to the chassis and is used for receiving the first range Doppler data and the second range Doppler data, and sequentially performing channel merging and space-time adaptive processing on the first range Doppler data and the second range Doppler data to obtain and output first speed range power information of a detection target;

the second adaptive board card is connected to the chassis and is used for receiving the first range Doppler data and the second range Doppler data, and sequentially performing channel merging and space-time adaptive processing on the first range Doppler data and the second range Doppler data to obtain and output second speed range power information of a detection target;

the switching board card is connected to the chassis and is used for receiving the first speed distance power information and the second speed distance power information;

and the upper computer is connected with the switching board card and is used for receiving and displaying the first speed distance power information and the second speed distance power information in real time through the switching board card.

2. The airborne radar space-time adaptive processor of claim 1, wherein the first pre-processing board, the second pre-processing board, the first adaptive board, and the second adaptive board each include: an FPGA chip, a first DSP processor, a second DSP processor, an Ethernet exchange chip and a srio exchange chip, wherein,

the FPGA chip is connected with the Ethernet switch chip, is connected with the outside through an optical fiber interface of x4, is connected to the SRIO switch chip through an SRIO of x4, and is connected to a back plate of the case through an Ethernet interface; three groups of DDR3 chips are hung on the FPGA chip;

the first DSP processor and the second DSP processor are both connected with the Ethernet switching chip and are both connected to the SRIO switching chip through SRIO of x 4; the first DSP processor and the second DSP processor are respectively mounted with a group of DDR3 chips;

the Ethernet switching chip is connected with the RJ45 network port and is connected to the back panel of the case through the SGMII interface;

the SRIO switch chip is connected to the backplane of the chassis through 4 x4 SRIO.

3. The airborne radar space-time adaptive processor of claim 2,

the FPGA chip in the first preprocessing board card is used for sequentially performing pulse compression and moving target detection on signals of 20 channels in the AD sampling data, combining the signals subjected to moving target detection into 10 channels of signals to obtain first range-doppler data, and then directly sending the range-doppler data to the first adaptive board card;

the srio exchange chip in the first preprocessing board card is used for receiving the range-doppler data and sending the range-doppler data to the second adaptive board card while the FPGA chip directly sends the range-doppler data to the first adaptive board card.

4. The airborne radar space-time adaptive processor of claim 2,

the FPGA chip in the second preprocessing board card is used for sequentially performing pulse compression and moving target detection on signals of 20 channels in the AD sampling data, combining the signals subjected to moving target detection into 10 channels of signals to obtain the range-Doppler data, and then directly sending the range-Doppler data to the second adaptive board card;

the srio exchange chip in the second preprocessing board card is used for receiving the range-doppler data and sending the range-doppler data to the first adaptive board card while the FPGA chip directly sends the range-doppler data to the second adaptive board card.

5. The airborne radar space-time adaptive processor of claim 2,

the FPGA chips in the first adaptive board card and the second adaptive board card are used for sequentially carrying out target guide constraint sample selection and GIP vector inner product sample selection on the data after channel combination;

the first DSP processors in the first self-adaptive board card and the second self-adaptive board card are used for sequentially carrying out inversion and normalization processing on the data selected by the GIP vector inner product sample;

and the second DSP processor in the first self-adaptive board card and the second self-adaptive board card is used for carrying out mDT clutter suppression processing on the data selected by the GIP vector inner product sample to respectively obtain the first speed distance power information and the second speed distance power information.

Technical Field

The invention belongs to the field of airborne radar signal processing, and particularly relates to an airborne radar space-time adaptive processor.

Background

The airborne radar can effectively improve the aerial monitoring capability, one airborne radar is equivalent to the coverage area of dozens of ground radars with the same standard, and the carrier has strong viability, is not easy to destroy, and is greatly helpful for detecting ships, airplanes, guided missiles and the like.

However, the working state of the airborne radar is always in a downward-looking state, in this state, the searching and tracking capability of the airborne radar on a target can be seriously influenced by strong ground clutter and sea clutter, and meanwhile, the relative carrier speeds of ground scatterers with different directions are different due to the motion of a carrier, so that the spectrum of the ground clutter is seriously widened, and the ground clutter has strong coupling in an airspace and a time domain. Therefore, the premise that the airborne radar can effectively detect and track the target is that the clutter suppression problem must be solved. To solve this problem, space-time adaptive processing (STAP) algorithms have been proposed and are gaining wide attention and research. The space-time adaptive processing can effectively suppress clutter and interference, but the computation amount is very large and is difficult to realize. Then, the dimension reduction space-time self-adaptive processing is carried out at the same time, and a theoretical basis is provided for engineering realization. Although the dimension is reduced, the calculation amount is still large, the calculation precision requirement is high, and the design difficulty of the radar signal processor is also large.

With the rapid development of microelectronic technology, the FPGA device of xilinx corporation can provide rich programmable logic units and embedded hardware multipliers, and the FPGA of Virtex 7 series supports floating point operation. The FPGA has rich operation and storage units, and the parallel processing structure of the FPGA ensures that the operation processing speed is high, thereby providing possibility for realizing space-time self-adaptive processing hardware.

But the FPGA logic development difficulty is higher, and the debugging period is longer; in addition, the FPGA is suitable for processing parallel repeated simple algorithms, complex algorithms such as SVD matrix separation, matrix inversion, Cholesky decomposition and the like are relatively difficult to design, however, the algorithms are common algorithms for space-time adaptive processing, and the complex algorithms are difficult to realize by the existing processor.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an airborne radar space-time adaptive processor. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides an airborne radar space-time adaptive processor, which comprises: a first preprocessing board card, a second preprocessing board card, a first self-adaptive board card, a second self-adaptive board card, a switching board card, a case and an upper computer,

the first preprocessing board card is connected to the case, connected to the upper computer, and used for receiving the AD sampling data sent by the upper computer, preprocessing the AD sampling data, and obtaining and outputting first distance Doppler data;

the second preprocessing board card is connected to the case, connected to the upper computer, and used for receiving the AD sampling data sent by the upper computer, preprocessing the AD sampling data, and obtaining and outputting second distance Doppler data;

the first adaptive board card is connected to the chassis and is used for receiving the first range Doppler data and the second range Doppler data, and sequentially performing channel merging and space-time adaptive processing on the first range Doppler data and the second range Doppler data to obtain and output first speed range power information of a detection target;

the second adaptive board card is connected to the chassis and is used for receiving the first range Doppler data and the second range Doppler data, and sequentially performing channel merging and space-time adaptive processing on the first range Doppler data and the second range Doppler data to obtain and output second speed range power information of a detection target;

the switching board card is connected to the chassis and is used for receiving the first speed distance power information and the second speed distance power information;

and the upper computer is connected with the switching board card and is used for receiving and displaying the first speed distance power information and the second speed distance power information in real time through the switching board card.

In an embodiment of the present invention, the first pre-processing board, the second pre-processing board, the first adaptive board, and the second adaptive board each include: an FPGA chip, a first DSP processor, a second DSP processor, an Ethernet exchange chip and a srio exchange chip, wherein,

the FPGA chip is connected with the Ethernet switch chip, is connected with the outside through an optical fiber interface of x4, is connected to the SRIO switch chip through an SRIO of x4, and is connected to a back plate of the case through an Ethernet interface; three groups of DDR3 chips are hung on the FPGA chip;

the first DSP processor and the second DSP processor are both connected with the Ethernet switching chip and are both connected to the SRIO switching chip through SRIO of x 4; the first DSP processor and the second DSP processor are respectively mounted with a group of DDR3 chips;

the Ethernet switching chip is connected with the RJ45 network port and is connected to the back panel of the case through the SGMII interface;

the SRIO switch chip is connected to the backplane of the chassis through 4 x4 SRIO.

In an embodiment of the present invention, the FPGA chip in the first preprocessing board is configured to sequentially perform pulse compression and moving-target detection on 20 channels of signals in the AD sampling data, combine the signals subjected to moving-target detection into 10 channels of signals, obtain the first range-doppler data, and then directly send the range-doppler data to the first adaptive board;

the srio exchange chip in the first preprocessing board card is used for receiving the range-doppler data and sending the range-doppler data to the second adaptive board card while the FPGA chip directly sends the range-doppler data to the first adaptive board card.

In an embodiment of the present invention, the FPGA chip in the second preprocessing board is configured to sequentially perform pulse compression and moving-target detection on 20 channels of signals in the AD sampling data, combine the signals subjected to moving-target detection into 10 channels of signals, obtain the range-doppler data, and then directly send the range-doppler data to the second adaptive board;

the srio exchange chip in the second preprocessing board card is used for receiving the range-doppler data and sending the range-doppler data to the first adaptive board card while the FPGA chip directly sends the range-doppler data to the second adaptive board card.

In an embodiment of the present invention, the FPGA chips in the first adaptive board and the second adaptive board are both used for sequentially performing target-oriented constrained sample selection and GIP vector inner product sample selection on the data after channel merging;

the first DSP processors in the first self-adaptive board card and the second self-adaptive board card are used for sequentially carrying out inversion and normalization processing on the data selected by the GIP vector inner product sample;

and the second DSP processor in the first self-adaptive board card and the second self-adaptive board card is used for carrying out mDT clutter suppression processing on the data selected by the GIP vector inner product sample to respectively obtain the first speed distance power information and the second speed distance power information.

Compared with the prior art, the invention has the beneficial effects that:

1. the space-time adaptive processor has the advantages of few operation processors, low cost and low power consumption, and adopts fewer operation processors as far as possible to realize the whole airborne radar space-time adaptive processor.

2. The space-time adaptive processor has high real-time performance, processes 40 array element signals, 128 Doppler channels and 1536 distance units of data every 25ms, and reports a detection target result in real time.

3. The space-time adaptive processor has good performance of the space-time adaptive algorithm, improves the performance of calculating clutter suppression by adopting algorithms such as target-oriented constrained sample selection, GIP vector sample selection, small sample independent processing and the like, and reduces false alarm and false alarm probability.

Drawings

Fig. 1 is a general hardware structure diagram of a space-time adaptive processor according to an embodiment of the present invention;

fig. 2 is a block diagram of a hardware board card for preprocessing a board card and a self-adaptive board card according to an embodiment of the present invention;

fig. 3 is a block diagram of a software processing flow of a space-time adaptive processor system according to an embodiment of the present invention;

FIG. 4 is a block diagram of a sample selection procedure for target-oriented constraint provided by an embodiment of the present invention;

FIG. 5 is a block diagram of a GIP inner product sample selection process according to an embodiment of the present invention;

fig. 6 is a block diagram of a hardware design according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.