阅读说明：本技术 一种探测器及其制作方法 (Detector and manufacturing method thereof ) 是由 唐波 张鹏 李志华 李彬 刘若男 于 2020-01-20 设计创作，主要内容包括：本发明涉及半导体工艺技术领域,尤其涉及一种探测器及其制作方法,包括：在SOI衬底上形成第一介质层；将所述第一介质层刻蚀至所述SOI表面,形成凹槽；在所述凹槽内形成探测层；在所述第一介质层和所述探测层上形成非晶硅层,由于在该探测层上形成非晶硅层,从而将该探测层进行了钝化,该非晶硅层可以阻止外界杂质向探测层上表面扩散,从而防止后续的沉积工艺过程中的离子损伤,为后续探测层表面注入时的缓冲层,降低注入对探测层的晶格损伤,从而降低该探测器的暗电流。(The invention relates to the technical field of semiconductor technology, in particular to a detector and a manufacturing method thereof, wherein the detector comprises the following steps: forming a first dielectric layer on an SOI substrate; etching the first dielectric layer to the surface of the SOI to form a groove; forming a detection layer in the groove; the amorphous silicon layer is formed on the first dielectric layer and the detection layer, so that the detection layer is passivated, and the amorphous silicon layer can prevent external impurities from diffusing to the upper surface of the detection layer, so that ion damage in the subsequent deposition process is prevented, the buffer layer is formed on the surface of the subsequent detection layer during injection, lattice damage to the detection layer during injection is reduced, and dark current of the detector is reduced.)

1. A method of fabricating a detector, comprising:

forming a first dielectric layer on an SOI substrate;

etching the first dielectric layer to the surface of the SOI to form a groove;

forming a detection layer in the groove;

and forming an amorphous silicon layer on the first dielectric layer and the detection layer.

2. The method of claim 1, further comprising:

and forming a second dielectric layer on the amorphous silicon layer.

3. The method of claim 1, wherein the etching the first dielectric layer to the SOI surface to form a recess comprises:

etching the first dielectric layer by adopting a dry etching process to form a first groove with a first preset depth, wherein the first preset depth is smaller than the thickness of the first dielectric layer;

and etching the bottom of the first groove by adopting a wet etching process to form a second groove with a second preset depth, wherein the sum of the first preset depth and the second preset depth is equal to the thickness of the first medium layer, and the first groove and the second groove are combined into the groove.

4. The method of claim 1, wherein forming a probe layer within the recess comprises:

forming a detection layer with the thickness larger than that of the first medium layer in the groove;

and carrying out planarization treatment on the detection layer to enable the upper surface of the detection layer to be flush with the first medium layer.

5. The method of claim 1, wherein prior to forming the first dielectric layer on the SOI, further comprising:

forming the SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer from bottom to top;

and doping the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region, and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the detection layer is positioned right above the intrinsic region.

6. The method of claim 1, further comprising:

a first through hole and a second through hole reaching the surface of the SOI substrate are formed in the second medium layer, the first through hole is abutted with the N-type heavily doped region, and the second through hole is abutted with the P-type heavily doped region;

filling conductive materials into the first through hole and the second through hole to form a first conductive plug and a second conductive plug respectively;

and respectively depositing metal films on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.

7. The method of claim 1, wherein forming an amorphous silicon layer on the first dielectric layer and the probe layer specifically comprises:

and forming an amorphous silicon layer on the first dielectric layer and the detection layer by adopting a low-pressure chemical vapor deposition process.

8. The method of claim 1, wherein the amorphous silicon layer has a thickness of 10nm to 100 nm. .

9. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are both silicon dioxide layers.

10. The method according to claim 1, characterized in that the detection layer is in particular a germanium layer or a silicon germanium layer.

11. A probe, comprising:

an SOI substrate;

the detection layer is arranged in the middle of the surface of the SOI substrate, and the first dielectric layer is arranged outside the middle of the surface of the SOI substrate;

and the amorphous silicon layer is positioned on the detection layer and the first dielectric layer.

Technical Field

The invention relates to the technical field of semiconductor processes, in particular to a detector and a manufacturing method thereof.

Background

Nowadays, the technology fields such as information industry and biomedicine are more and more concerned, and novel photoelectron and optical communication technologies are inevitably developed at a faster speed. The silicon-based photoelectronic integration adopts a mature and cheap microelectronic processing technology to integrate an optical device with a microelectronic circuit with multiple functions, and is an effective way for realizing popularization and development of optical communication and optical interconnection. The silicon-based photoelectric detector is one of key devices of a silicon-based optical communication system, and with the breakthrough development of silicon-based germanium material epitaxy technology in recent years, the germanium detector becomes a hot spot of current research because of taking silicon-based photoelectron integration and efficient detection of optical communication wave bands into consideration.

In a conventional germanium detector, dark current is an important parameter index of a silicon-based germanium detector, and the sensitivity and noise of the germanium detector, the epitaxial interface quality, the in-vitro epitaxial quality and the epitaxial germanium surface quality are all key factors influencing the dark current.

Therefore, how to improve the quality of the outer detector extension interface and thus reduce the dark current is a technical problem to be solved.

Disclosure of Invention

In view of the above, the present invention has been developed to provide a detector and a method of manufacturing the same that overcome, or at least partially address, the above-mentioned problems.

In one aspect, an embodiment of the present invention provides a method for manufacturing a detector, including:

forming a first dielectric layer on an SOI substrate;

etching the first dielectric layer to the surface of the SOI to form a groove;

forming a detection layer in the groove;

and forming an amorphous silicon layer on the first dielectric layer and the detection layer.

Further, the etching the first dielectric layer to the surface of the SOI to form a groove specifically includes:

etching the first dielectric layer by adopting a dry etching process to form a first groove with a first preset depth, wherein the first preset depth is smaller than the thickness of the first dielectric layer;

and etching the bottom of the first groove by adopting a wet etching process to form a second groove with a second preset depth, wherein the sum of the first preset depth and the second preset depth is equal to the thickness of the first medium layer, and the first groove and the second groove are combined into the groove.

Further, forming a detection layer in the groove specifically includes:

forming a detection layer with the thickness larger than that of the first medium layer in the groove;

and carrying out planarization treatment on the detection layer to enable the upper surface of the detection layer to be flush with the first medium layer.

Further, before forming the first dielectric layer on the SOI, the method further includes:

forming the SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer from bottom to top;

and doping the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region, and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the detection layer is positioned right above the intrinsic region.

Further, still include:

and forming a second dielectric layer on the amorphous silicon layer.

Further, still include:

a first through hole and a second through hole reaching the surface of the SOI substrate are formed in the second medium layer, the first through hole is abutted with the N-type heavily doped region, and the second through hole is abutted with the P-type heavily doped region;

filling conductive materials into the first through hole and the second through hole to form a first conductive plug and a second conductive plug respectively;

and respectively depositing metal films on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.

Further, forming an amorphous silicon layer on the first dielectric layer and the detection layer specifically includes:

and forming an amorphous silicon layer on the first dielectric layer and the detection layer by adopting a low-pressure chemical vapor deposition process.

Further, the thickness of the amorphous silicon layer is 10nm to 100 nm.

Further, the first dielectric layer and the second dielectric layer are both silicon dioxide layers.

Further, the detection layer is specifically a germanium layer or a germanium-silicon layer.

On the other hand, an embodiment of the present invention further provides a detector, including:

an SOI substrate;

the detection layer is arranged in the middle of the surface of the SOI substrate, and the first dielectric layer is arranged outside the middle of the surface of the SOI substrate;

and the amorphous silicon layer is positioned on the detection layer and the first dielectric layer.

One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

the invention provides a manufacturing method of a detector, which comprises the following steps: forming a first dielectric layer on the SOI substrate, and etching the first dielectric layer to the surface of the SOI substrate to form a groove; forming a detection layer in the groove; the amorphous silicon layer is formed on the first dielectric layer and the detection layer, so that the detection layer is passivated, and the amorphous silicon layer can prevent external impurities from diffusing to the upper surface of the detection layer, so that ion damage in the subsequent deposition process is prevented, the damage of the injection to the crystal lattice of the detection layer is reduced for the buffer layer when the surface of the subsequent detection layer is injected, and the dark current of the detector is reduced.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a flow chart illustrating steps of a method for fabricating a probe according to a first embodiment of the present invention;

FIGS. 2-13 are schematic diagrams illustrating a process for fabricating a detector according to a first embodiment of the invention;

fig. 14 shows a schematic structural diagram of a detector in the first embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.